US8312190B2 - Protocol translation in a serial buffer - Google Patents
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- US8312190B2 US8312190B2 US12/043,929 US4392908A US8312190B2 US 8312190 B2 US8312190 B2 US 8312190B2 US 4392908 A US4392908 A US 4392908A US 8312190 B2 US8312190 B2 US 8312190B2
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- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/387—Information transfer, e.g. on bus using universal interface adapter for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
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- the present invention relates to a multi-port serial buffer designed to provide reliable connections between a first system that implements first serial protocol and a second system that implements a second serial protocol.
- a multi-port serial buffer it is desirable for a multi-port serial buffer to be able to efficiently and flexibly store and retrieve packet data. It would further be desirable to have a multi-port serial buffer that enables efficient and flexible transfer of packet data between the various ports, particularly if the ports are implementing different serial protocols.
- the present invention provides a multi-port serial buffer having a first port configured to implement an sRIO protocol (to enable connection to an sRIO endpoint), and a second port to be configured to implement a Lite-weight protocol (to enable connection to a field programmable device, such as an FPGA).
- the serial buffer implements protocol translation to translate from Lite-weight protocol on the second port to sRIO protocol on the first port (and vice versa).
- the serial buffer includes sRIO-to-Lite translation logic, which translates incoming sRIO protocol packets (sRIO packets) received from the first port into Lite-weight protocol packets (Lite packets), which are transmitted to the second port.
- the sRIO-to-Lite translation logic translates an incoming sRIO packet to an outgoing Lite packet by modifying the header of the incoming sRIO packet to create a header that is consistent with the Lite-weight protocol. More specifically, a source identification (ID) value in the header of the incoming sRIO packet is used to look up a corresponding case number value, which is included in the header of the translated Lite packet.
- ID source identification
- the serial buffer includes Lite-to-sRIO translation logic, which translates incoming Lite packets received from the second port into sRIO packets, which are transmitted to the first port.
- the Lite-to-sRIO translation logic translates an incoming Lite packet to an outgoing sRIO packet by modifying the header of the incoming Lite packet to create a header that is consistent with the sRIO protocol.
- the Lite-to-sRIO translation logic may be configured to operate in either a packet-based mode or a queue-based mode.
- a case number value in the header of the received Lite packet is used to look up predetermined sRIO header information, which is included in the header of the translated sRIO packet.
- the incoming Lite packet is stored in a queue of the serial buffer.
- a case number value associated with this queue is used to look up predetermined sRIO header information, which is included in the header of the translated sRIO packet.
- the Lite-to-sRIO translation logic also includes logic for segmenting received Lite packets that are not double-word aligned in the manner required by the sRIO protocol.
- FIG. 1 is a block diagram of a multi-port serial buffer in accordance with one embodiment of the present invention.
- FIG. 2 is a block diagram illustrating translation logic present within the serial buffer of FIG. 1 , in accordance with one embodiment of the present invention.
- FIG. 3 is a flow diagram illustrating the operation of the translation logic of FIG. 2 , in accordance with one embodiment of the present invention.
- FIG. 4 is a block diagram illustrating additional translation logic present within the serial buffer of FIG. 1 , in accordance with one embodiment of the present invention.
- FIG. 5 is a flow diagram illustrating the operation of the translation logic of FIG. 4 , in accordance with one embodiment of the present invention.
- FIG. 1 is a block diagram of a serial buffer 100 in accordance with one embodiment of the present invention.
- Serial buffer 100 includes a first port 1 , a second port 2 , memory queues Q 0 -Q 7 , write control logic 101 , read control logic 102 , sRIO-to-Lite translation logic 111 , Lite-to-sRIO translation logic 112 , and output multiplexers 121 - 122 .
- the first port 1 of serial buffer 100 is configured to operate in accordance with an sRIO protocol, and provides an interface to an sRIO endpoint (not shown).
- the second port 2 of serial buffer 100 is configured to operate in accordance with a Lite-weight protocol, and provides an interface to a Lite-weight protocol device, such as a field programmable device (not shown).
- a Lite-weight protocol device such as a field programmable device (not shown).
- sRIO-to-Lite translation logic 111 is enabled, such that incoming sRIO packets received from the first port 1 are translated to create corresponding Lite packets.
- Write control logic 101 causes these translated Lite packets to be written to queues Q 4 -Q 7 .
- Read control logic 102 subsequently causes these translated Lite packets to be read from queues Q 4 -Q 7 , and transferred to the second port 2 (through output multiplexer 122 ).
- serial buffer 100 translates sRIO packets received by the first port 1 into Lite packets, which are transmitted to the second port 2 .
- Write control logic 101 also causes Lite packets received from the second port 2 to be written to queues Q 0 -Q 3 .
- Read control logic 102 subsequently causes these Lite packets to be read from queues Q 0 -Q 3 , and transferred to Lite-to-sRIO translation logic 112 (through output multiplexer 121 ).
- Lite-to-sRIO translation logic 112 is enabled, such that the received Lite packets are translated into corresponding sRIO packets.
- serial buffer 100 translates Lite packets received by the second port 2 into sRIO packets, which are transmitted to the first port 1 .
- sRIO-to-Lite translation logic 111 translates an incoming sRIO packet to a corresponding Lite packet by modifying a header of the incoming sRIO packet to create a header that is consistent with the Lite-weight protocol. More specifically, a source identification (ID) value in the header of the incoming sRIO packet is used to look up a corresponding case number value, which is included in the header of the translated Lite packet.
- ID source identification
- Lite-to-sRIO translation logic 112 translates a received Lite packet into a corresponding sRIO packet by modifying the header of the received Lite packet to create a header that is consistent with the sRIO protocol.
- Lite-to-sRIO translation logic 112 may be configured to operate in either a packet-based mode or a queue-based mode. In the packet-based mode, a case number value in the header of the received Lite packet is used to look up predetermined sRIO header information, which is included in the header of the translated sRIO packet. In the queue-based mode, the identity of a queue in which the Lite packet is stored is used to look up predetermined sRIO header information, which is included in the header of the translated sRIO packet.
- FIG. 2 is a block diagram illustrating circuitry present within Lite-to-SRIO translation logic 112 in accordance with one embodiment of the present invention.
- Lite-to-SRIO translation logic 112 includes case mode registers 200 - 203 , multiplexers 210 - 215 and case scenario registers SC 0 -SC 15 .
- a TT value of ‘0’ indicates that a corresponding sRIO packet includes 8-bit source and destination ID values
- a TT value of ‘1’ indicates that a corresponding sRIO packet includes 16-bit source and destination ID values.
- each case scenario register SC n can be used to construct sRIO packet headers in a manner understood by those of ordinary skill in the art.
- each of the case scenario registers SC 0 -SC 15 is programmed to store different corresponding sRIO packet header information.
- Case mode registers 200 - 203 store case number values assigned to queues Q 0 -Q 3 , respectively. More specifically, case mode registers 200 , 201 , 202 and 203 store case number values CASE_NO_Q 0 [3:0], CASE_NO_Q 1 [3:0], CASE_NO_Q 2 [3:0], and CASE_NO_Q 3 [3:0], respectively, which are assigned to queues Q 0 , Q 1 , Q 2 and Q 3 , respectively.
- case number values CASE_NO_Q 0 [3:0], CASE_NO_Q 1 [3:0], CASE_NO_Q 2 [3:0] and CASE_NO_Q 3 [3:0] are assigned to specific queues, these case number values may be referred to as queue-based case number values.
- Each of the queue-based case number values CASE_NO_Q 0 [3:0], CASE_NO_Q 1 [3:0], CASE_NO_Q 2 [3:0] and CASE_NO_Q 3 [3:0] specifies one of the case scenario registers SC 0 -SC 15 .
- Queue-based case number values CASE_NO_Q 0 [3:0], CASE_NO_Q 1 [3:0], CASE_NO_Q 2 [3:0] and CASE_NO_Q 3 [3:0] are provided to inputs of multiplexers 210 , 211 , 212 and 213 , respectively.
- the other inputs of multiplexers 210 - 213 are configured to receive a case number value (CASE_NO[3:0]), which is present in a Lite packet header read from one of queues Q 0 -Q 3 . Because the case number value CASE_NO[3:0] is defined by the contents of a Lite packet, this case number value may be referred to as a packet-based case number value.
- Each packet-based case number value CASE_NO[3:0] specifies one of the case scenario registers SC 0 -SC 15 . It is important to note that successive Lite packets may include different packet-based case number values, and may therefore specify different ones of the case scenario registers SC 0 -SC 15 .
- the control terminals of multiplexers 210 , 211 , 212 and 213 are configured to receive configuration bits Q_PKT_CASE[ 0 ], Q_PKT_CASE[ 1 ], Q_PKT_CASE[ 2 ], and Q_PKT_CASE[ 3 ], respectively.
- Each configuration bit Q_PKT_CASE[m] causes the corresponding multiplexer to route either the corresponding queue-based case number value (CASE_NO_Qm[3:0]) or the packet-based case number value (CASE_NO[3:0]).
- a configuration bit Q_PKT_CASE[m] having a logic ‘1’ value will cause the corresponding multiplexer to route the corresponding queue-based case number value (CASE_NO_Qm[3:0]), while a configuration bit Q_PKT_CASE[m] having a logic ‘0’ value will cause the corresponding multiplexer to route the packet-based case number value (CASE_NO[3:0]).
- the configuration bits Q_PKT_CASE[3:0] are used to determine whether a queue-based case number value or a packet-based case number value will be used to select one of the case scenario registers SC 0 -SC 15 .
- the configuration bits Q_PKT_CASE[3:0] are stored in a programmable register of serial buffer 100 .
- the outputs of multiplexers 210 , 211 , 212 and 213 are provided to the inputs of multiplexer 214 as the case number values CASE_SEL 0 [3:0], CASE_SEL 1 [3:0], CASE_SEL 2 [3:0], and CASE_SEL 3 [3:0], respectively.
- the control terminals of multiplexer 214 are configured to receive a first port queue read select value P 1 _Q_RD_SEL[3:0], which is provided by read control logic 102 .
- the first port queue read select value P 1 _Q_RD_SEL[3:0] specifies the highest priority queue having a Lite packet to be transferred out to the first port 1 .
- Multiplexer 214 routes the received case number value (i.e., CASE_SEL 0 [3:0], CASE_SEL 1 [3:0], CASE_SEL 2 [3:0] or CASE_SEL 3 [3:0]) associated with the queue specified by the first port queue read select value P 1 _Q_RD_SEL[3:0] as a selected case number value CASE_SEL[3:0].
- CASE_SEL 0 [3:0] CASE_SEL 1 [3:0]
- CASE_SEL 2 [3:0] CASE_SEL 3 [3:0]
- case scenario registers SC 0 -SC 15 are provided to corresponding inputs of multiplexer 215 .
- the control terminals of multiplexer 215 are configured to receive the selected case number value CASE_SEL[3:0].
- multiplexer 215 routes the contents of one of the case scenario registers SC 0 -SC 15 as the sRIO packet header information, PRIO[1:0], TT, FTYPE[3:0], TTYPE[3:0] and DEST_ID[3:0].
- Lite-to-sRIO translation logic 112 uses the sRIO packet header information routed by multiplexer 215 to construct an sRIO header for the corresponding packet to be transferred to the first port 1 .
- FIG. 3 is a flow diagram 300 illustrating the operation of Lite-to-sRIO translation logic 112 in accordance with one embodiment of the present invention.
- Lite-to-sRIO translation logic 112 is initially in an IDLE state 301 .
- Lite-to-sRIO translation logic 112 will remain in IDLE state 301 as long as no Lite packets are read from queues Q 0 -Q 3 (Step 302 , No branch).
- IDLE state 301 if the water level of any of queues Q 0 -Q 3 reaches its corresponding watermark (Step 302 , Yes branch), read control logic 102 will initiate a read operation, thereby causing a Lite packet to be read from the selected queue and provided to Lite-to-sRIO translation logic 112 .
- read control logic 102 will read a Lite packet from the highest priority queue.
- Read control logic 102 generates the first port queue read select signal P 1 _Q_RD_SEL[3:0], which identifies the queue from which the Lite packet is being read. For example, upon determining that a Lite packet is being read from queue Q 0 , read control logic 102 will generate a first port queue read select signal P 1 _Q_RD_SEL[3:0] having a value of ‘0001’. As indicated by FIG.
- this first port queue read select signal will cause multiplexer 214 to route the case number value CASE_SEL 0 [3:0] provided by multiplexer 210 to multiplexer 215 as the selected case number CASE_SEL[3:0]. Processing proceeds to HEADER_READ state 303 .
- Lite-to-sRIO translation logic 112 reads the packet header of the Lite packet read from the selected queue. In the present example, Lite-to-sRIO translation logic 112 reads a Lite packet header from queue Q 0 .
- Lite-to-sRIO translation logic 112 determines whether the selected queue should be processed in a queue-based case mode or a packet-based case mode (Step 304 ).
- the configuration bits Q_PKT_CASE[ 0 ], Q_PKT_CASE[ 1 ], Q_PKT_CASE[ 2 ] and Q_PKT_CASE[ 3 ] specify whether the corresponding queues Q 0 , Q 1 , Q 2 and Q 3 should be operated in the queue-based case mode or the packet-based case mode.
- a configuration bit Q_PKT_CASE[m] having a logic ‘1’ value specifies that the corresponding queue Qm will operate in the queue-based case mode
- a configuration bit Q_PKT_CASE[m] have a logic ‘0’ value specifies that the corresponding queue Qm will operate in the packet-based case mode. If the configuration bit Q_PKT_CASE[m] associated with the selected queue Qm specifies the queue-based case mode (Step 304 , Q-BASED CASE branch), then processing proceeds to QUEUE_CASE state 305 .
- Step 304 processing proceeds to PACKET_CASE state 306 .
- Lite-to-sRIO translation logic 112 will retrieve the case number value assigned to the selected queue. More specifically, Lite-to-sRIO translation logic 112 will retrieve the queue-based case number value stored in the case mode register 200 - 203 associated with the selected queue.
- the configuration bit Q_PKT_CASE[ 0 ] associated with the selected queue Q 0 will have a logic ‘1’ value, thereby causing multiplexer 210 to route the queue-based case number value CASE_NO_Q 0 [3:0] stored in case mode register 200 .
- the retrieved queue-based case number value (e.g., CASE_NO_Q 0 [3:0]) is routed to multiplexer 215 as the selected case number value CASE_SEL[3:0].
- Lite-to-sRIO translation logic 112 uses the retrieved queue-based case number (i.e., CASE_SEL[3:0]) to select one of the sixteen case scenario registers SC 0 -SC 15 .
- each of the sixteen case scenario registers SC 0 -SC 15 stores corresponding sRIO packet header information.
- the sRIO packet header information in the selected case scenario register is routed through multiplexer 215 . Processing then proceeds to A_DATA_TRANSFER state 307 .
- Step 304 if the configuration bit Q_PKT_CASE[m] associated with the selected queue Qm specifies the packet-based case mode, then processing proceeds to PACKET_CASE state 306 . Under these conditions, Lite-to-sRIO translation logic 112 will retrieve a case number value specified by the Lite packet read from the selected queue. More specifically, Lite-to-sRIO translation logic 112 will retrieve the case number value (CASE_NO[3:0]) from the header of the Lite packet read from the selected queue.
- the configuration bit Q_PKT_CASE[ 0 ] associated with the selected queue Q 0 would have a logic ‘0’ value in the packet-based case mode, thereby causing multiplexer 210 to route the packet-based case number value CASE_NO[3:0] from the Lite packet header.
- the retrieved packet-based case number value (e.g., CASE_NO[3:0]) is routed to multiplexer 215 as the selected case number value CASE_SEL[3:0].
- Lite-to-sRIO translation logic 112 uses the retrieved packet-based case number (i.e., CASE_SEL[3:0]) to select one of the sixteen case scenario registers SC 0 -SC 15 .
- each of the sixteen case scenario registers SC 0 -SC 15 stores corresponding sRIO packet header information.
- the sRIO packet header information in the selected case scenario register is routed through multiplexer 215 . Processing then proceeds to ASC_DATASC_TRANSFER state 307 , and continues in the manner described above.
- Lite packets received on the second port 2 can be translated to sRIO packets transmitted to the first port 1 , using predetermined sRIO protocol information stored in sixteen case scenario registers SC 0 -SC 15 .
- Different sRIO packet types can be supported by different case scenario registers.
- different Lite packets stored in the same queue can be translated to sRIO packets having different sRIO protocol information.
- a Lite packet read from the selected queue is not double-word aligned, data segmentation is performed, and the Lite packet data is sent out in two sRIO packets.
- the first sRIO packet transfers all packet data until the last double-word of the Lite packet data.
- the second sRIO packet will transfer the remaining bytes within the last double-word of the Lite packet data.
- FIG. 4 is a block diagram 400 illustrating circuitry present within sRIO-to-Lite translation logic 111 in accordance with one embodiment of the present invention.
- SRIO-to-Lite translation logic 111 includes comparator 401 , multiplexer 402 and case select registers SL 0 -SL 15 .
- the case number value stored in each case select register SL n can be used to construct Lite packet headers in a manner understood by those of ordinary skill in the art.
- each of the case select registers SL 0 -SL 15 is programmed to store a different corresponding case number value.
- Each case select register SL n is also programmed to store a corresponding source ID value, PKT_SOURCE_IDSC n [15:0].
- Comparator 401 is configured to compare the source ID value (SRIO_SOURCE_ID[15:0]) of each incoming sRIO packet received from the first port 1 with each of the source ID values stored in case select registers SL 0 -SL 15 . Upon detecting a match, comparator 401 activates a corresponding bit within match indicator signal, PKT_SOURCE_ID_MATCH[15:0].
- comparator 401 determines that the incoming source ID value SRIO_SOURCE_ID[15:0] matches the source ID value stored in case select register SL n , then comparator 401 activates the corresponding match indicator bit, PKT_SOURCE_ID_MATCH[n].
- the match indictor signal PKT_SOURCE_ID_MATCH[15:0] is used to control multiplexer 402 . More specifically, an activated bit PKT_SOURCE_ID_MATCH[n] within the match indicator signal PKT_SOURCE_ID_MATCH[15:0] causes multiplexer 402 to route the case number CASE_NO_n[3:0] from the corresponding case select register SL n .
- FIG. 5 is a flow diagram 500 illustrating the operation of sRIO-to-Lite translation logic 111 in accordance with one embodiment of the present invention.
- sRIO-to-Lite translation logic 111 is initially in an IDLE state 501 .
- sRIO-to-Lite translation logic 111 will remain in IDLE state 501 as long as no sRIO packets are available from sRIO port 1 (Step 502 , No branch).
- IDLE state 501 if a sRIO packet is available from sRIO port 1 (Step 502 , Yes branch), then processing will proceed to CASE_SELECTION state 503 .
- the incoming sRIO packet will include a source ID value, which identifies the source of the incoming sRIO packet, and a destination ID value, which identifies the queue to which the incoming sRIO packet should be written.
- This identified queue is hereinafter referred to as the selected write queue. Note that in the described embodiments, the selected write queue is one of queues Q 4 -Q 7 .
- sRIO-to-Lite translation logic 111 extracts the source ID value (SRIO_SOURCE_ID[15:0]) from the header of the incoming sRIO packet, and compares this extracted source ID value with the source ID values stored in case selection registers SL 0 -SL 15 . As described above in connection with FIG. 4 , this comparison operation is performed within comparator 401 .
- Step 504 If comparator 401 does not detect a match (Step 504 , No branch), then processing proceeds to PROG_ERROR state 506 .
- sRIO-to-Lite translation logic 111 indicates a software programming error exists, and will reprogram the source ID values stored in case selection registers SL 0 -SL 15 , or request that the incoming packet header be changed to include a valid source ID value.
- sRIO-to-Lite translation logic 111 identifies the case selection register SL n that stores the source ID value (PKT_SOURCE_ID_n[15:0]) that matches the source ID value of the incoming sRIO packet. SRIO-to-Lite translation logic 111 then retrieves the case number value (CASE_NO_n[3:0]) stored in this identified case selection register SL n . SRIO-to-Lite translation logic 111 then uses this retrieved case number value to construct a Lite packet header.
- SRIO-to-Lite translation logic 111 inserts the retrieved case number value into a case number field of a Lite packet header. SRIO-to-Lite translation logic 111 also inserts other header information derived from the incoming sRIO packet header (e.g., as packet ID) into the constructed Lite packet header. Processing then proceeds to PACKET_WRITE state 507 .
- SRIO-to-Lite translation logic 111 causes write control logic 101 to write the constructed Lite packet header into the selected write queue.
- SRIO-to-Lite translation logic 111 then causes write control logic 101 to write all packet data from the incoming sRIO packet into the selected write queue. Processing then returns to IDLE state 501 .
- IDLE state 501 Note that a packet written to the selected write queue in the above-described manner has been effectively translated to be consistent with the Lite-weight protocol. Thus, when this translated packet is subsequently read out, the second port 2 is able to identify the packet type and origin of this packet.
- sRIO-to-Lite translation logic 111 is located between the first port 1 and the queues Q 4 -Q 7 in the described embodiments, it is understood that sRIO-to-Lite translation logic may be located between queues Q 4 -Q 7 and the second port 2 in other embodiments.
- Lite-to-sRIO translation logic 112 is located between queues Q 0 -Q 3 and the second port in the described embodiments, it is understood that Lite-to-sRIO translation logic 112 may be located between the second port and queues Q 0 -Q 3 in other embodiments.
- queues Q 4 -Q 7 are assigned to sRIO-to-Lite translation logic 111
- queues Q 0 -Q 3 are assigned to Lite-to-sRIO translation logic 112
- queue assignments are possible in other embodiments of the present invention.
- the present invention is limited only by the following claims.
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