US8309991B2 - Nanowire FET having induced radial strain - Google Patents

Nanowire FET having induced radial strain Download PDF

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US8309991B2
US8309991B2 US12/631,218 US63121809A US8309991B2 US 8309991 B2 US8309991 B2 US 8309991B2 US 63121809 A US63121809 A US 63121809A US 8309991 B2 US8309991 B2 US 8309991B2
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nanowire
gate
gate conductor
strain
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Sarunya Bangsaruntip
Guy Cohen
Conal E. Murray
Jeffrey W. Sleight
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GlobalFoundries US Inc
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Definitions

  • aspects of the present invention are directed to a nanowire field effect transistor (FET) and, more particularly, to a nanowire FET with a metal gate that is surrounded with silicide around the metal gate for inducing radial and, in some cases, longitudinal strain in the nanowire channel.
  • FET nanowire field effect transistor
  • a device in accordance with an aspect of the invention, includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire.
  • SOI silicon-on-insulator
  • a device in accordance with an aspect of the invention, includes first and second pads, a nanowire, formed in a silicon-on-insulator (SOI) layer disposed over a buried oxide (BOX) layer, connecting the first and second pads and a gate surrounding the nanowire and including a dielectric adjacent the nanowire, a gate conductor adjacent the dielectric and a fully silicided material surrounding the gate conductor to radially strain the nanowire.
  • SOI silicon-on-insulator
  • BOX buried oxide
  • a method to induce radial strain in a field effect transistor (FET) nanowire includes surrounding the nanowire with a gate conductor and surrounding the gate conductor with poly-Si, depositing a silicide forming metal onto the poly-Si and reacting the poly-Si with the silicide forming metal to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
  • FET field effect transistor
  • a method for testing induced strain includes measuring device characteristics with a strain neutral doped poly-Si gate, re-measuring the device characteristics following conversion of the strain neutral doped poly-Si gate to a FUSI gate and correlating a change in the device characteristics with a strain intensity.
  • FIG. 1 is a perspective view of a nanowire under strain
  • FIGS. 2A and 2B are views of a nanowire extending across a recessed oxide
  • FIGS. 3A and 3B are views of a reshaped nanowire extending across the recessed oxide
  • FIGS. 4A and 4B are views of a nanowire and a poly-Si coated with a gate dielectric and partially coated with TaN;
  • FIGS. 4C and 4D are views of the nanowire and the poly-Si fully coated with the gate dielectric and the TaN;
  • FIG. 5 is a side sectional view of a poly-Si gate with epitaxy, silicide and oxide coatings.
  • FIG. 6 is a side sectional view of a FUSI stressor with the structures of FIG. 5 .
  • GAA gate-all-around
  • FET nanowire field effect transistor
  • the present methods are described using silicon (Si) nanowires and Si processing.
  • the present techniques can also be practiced with other semiconductor materials such as, for example, germanium (Ge) or III-V semiconductors.
  • the processing steps of the present teachings are basically the same except that growth temperature and dopant species applied are adapted to the specific semiconductor used.
  • Use of Si-containing semiconductor materials such as Si, silicon germanium (SiGe), Si/SiGe, silicon carbide (SiC) or silicon germanium carbide (SiGeC) are exemplary. It is noted that a portion of the nanowires is used herein as the device channel or body.
  • ⁇ r/r radial strain
  • ⁇ L/L longitudinal strain
  • r and L being the nanowire's radius and length, respectively
  • ⁇ r and ⁇ L being the change in radius and the change in length, respectively, as a result of stress.
  • P residual stress
  • a method to induce radial strain and, in some cases, longitudinal strain in a nanowire channel, without the need to change the gate conductor or the process that is used to define the gate is provided and makes use of a thin metal all-around-gate (e.g., about 2-4 nm and, in some cases, about 3 nm thick tantalum nitride (TaN)) while the “filler” material that connects all the nanowires' metal gates and forms a solid gate line is initially poly-Si that is later converted into fully silicided material (FUSI).
  • a thin metal all-around-gate e.g., about 2-4 nm and, in some cases, about 3 nm thick tantalum nitride (TaN)
  • the “filler” material that connects all the nanowires' metal gates and forms a solid gate line is initially poly-Si that is later converted into fully silicided material (FUSI).
  • the FUSI surrounding the metal gate effectively induces strain in the nanowire channel, but does not impact other device properties (such as the work function) since the latter is set by the metal gate.
  • the gate definition process therefore, remains substantially constant even if various silicides are used for the FUSI.
  • the device structure and process operations are summarized and relate to embodiments in which the FUSI gate is formed last.
  • a wafer is provided and includes a Si substrate 101 , a buried oxide (BOX) layer 102 and a silicon-on-insulator (SOI) layer 103 .
  • the wafer can be fabricated using methods such as Separation by IMplanted OXygen (SIMOX) or wafer bonding (for example, SmartCutTM). These wafer fabrication techniques are known to those of skill in the art and thus are not described further herein. Also, the substitution of other SOI substrates known in the art for the SOI on BOX configuration described herein may be made and would be within the scope of the present teachings.
  • Nanowires 104 connected to SOI pads 103 A are patterned in SOI layer 103 to form a ladder-like structure.
  • SOI layer 103 is made to have a typical thickness of about 20-30 nanometers (nm).
  • the as-patterned nanowires 104 have a height that is about 20-30 nm.
  • a width of the nanowires 104 can be in the range of about 10-30 nm.
  • the patterning of the nanowires 104 and SOI pads 103 A may be achieved by lithography (e.g., optical or e-beam) followed by reactive ion etching (RIE) or by a sidewall transfer technique. These patterning techniques are known to those of skill in the art and thus are not described further herein.
  • the nanowires 104 can be suspended or released from the BOX layer 102 by etching and a recessing of the BOX layer 102 under the nanowires 104 .
  • the nanowires 104 thus form a suspended bridge between the SOI pads 103 A over recessed oxide 105 .
  • the recessing of the BOX layer 102 can be achieved with a diluted hydrofluoric (DHF) etch.
  • DHF diluted hydrofluoric
  • the lateral component of this etching undercuts the BOX layer 102 under the nanowires 104 .
  • the suspension of the nanowires 104 may be obtained during an annealing process to re-shape the nanowires 104 .
  • While SOI substrates provide an easy path to define and suspend nanowires 104 , it is possible to obtain suspended nanowires 104 with other substrates.
  • a SiGe/Si stack epitaxially grown on bulk Si wafers can also be patterned to form the nanowires 104 .
  • the SiGe layer can be used as a sacrificial layer (analogous to the BOX layer 102 ) which is undercut to suspend the nanowires 104 .
  • the nanowires 104 are then reshaped to form reshaped nanowires 108 , as shown in FIGS. 3A and 3B .
  • the reshaping refers to a smoothing of the respective surfaces of the nanowires 104 to thereby change their respective cross-sections to be more cylindrical, and to a thinning of the respective nanowire 104 bodies by moving silicon from the nanowire 104 bodies to the SOI pads 103 A.
  • the reshaped nanowires 108 may be formed by way of an annealing process during which the SOI wafer contacts an inert gas at a temperature, pressure and for a duration sufficient to cause Si to migrate from the nanowires 104 to the SOI pads 103 A.
  • the term “inert gas” refers to a gas that does not react with Si and may include hydrogen (H 2 ), xenon (Xe), helium (He) and potentially others.
  • the wafer may be annealed in an exemplary H 2 gas.
  • native oxide is etched off from the surfaces of the nanowires 104 and the SOI pads 103 A.
  • the annealing in H 2 smoothes the nanowire sidewalls, realigns the sidewalls and the SOI pads 103 A and re-shapes the nanowire 104 cross-section from a rectangular cross-section to a more cylindrical cross-section.
  • the H 2 anneal may also thin the nanowire 104 body by re-distributing Si to the SOI pads 103 A.
  • the inert gas anneal may be performed with a gas pressure of from about 30 torr to about 1000 torr, at a temperature of from about 600 degrees Celsius (° C.) to about 1100° C. and for a duration of about 1-120 minutes.
  • a gas pressure of from about 30 torr to about 1000 torr, at a temperature of from about 600 degrees Celsius (° C.) to about 1100° C. and for a duration of about 1-120 minutes.
  • the rate of Si re-distribution increases with temperature and decrease with an increase in pressure.
  • a conformal gate dielectric 112 is deposited over the structure.
  • the gate dielectric 112 may include silicon dioxide (SiO 2 ), silicon oxynitride (SiON), hafnium oxide (HfO 2 ) or any other suitable hi-K dielectric(s) and may be deposited over SOI pads 103 A and around the reshaped nanowires 108 using chemical vapor deposition (CVD), atomic layer deposition (ALD) or an oxidation furnace in the case of SiO 2 and SiON.
  • CVD chemical vapor deposition
  • ALD atomic layer deposition
  • a mask 115 is employed to facilitate the etching of a gate line by reactive ion etching (RIE).
  • RIE reactive ion etching
  • the thin gate conductor 117 may be removed by RIE as shown in FIGS. 4A and 4B .
  • the removal of the thin gate conductor 117 from surfaces outside gate line 118 A may require an additional wet etch step as shown in FIGS. 4C and 4D .
  • a poly-Si 113 is blanket deposited.
  • RIE e.g., hydrogen bromide (HBr)-based chemistry
  • the poly-Si 113 is selectively etched except where the etching is blocked by mask 115 to define a cleared region 119 .
  • the RIE process includes a first phase, during which etching is directional to obtain a substantially straight profile for the gate line 118 A, and a second phase, during which the gate line 118 A is trimmed sideways by an amount sufficient to clear the gate material under the reshaped nanowires 108 in the regions outside the gate stack 118 .
  • the gate etching can include the etching of the thin gate conductor 117 , as shown in FIGS. 4A and 4B , or it can be limited to an etching of the poly-Si 113 while leaving the thin gate conductor 117 relatively intact, as illustrated in FIGS. 4C and 4D .
  • gate sidewall spacers 121 are formed and epitaxy 122 may be selectively used to thicken the reshaped nanowire 108 portions that are not encapsulated by the gate stack 118 and sidewall spaces.
  • the SOI pads 103 A may also be thickened as necessary by epitaxy 122 .
  • Epitaxy 122 can include in-situ doping to incorporate dopants into the source/drain regions. Alternatively, ion-implantation can be used to dope the source and drain region. A self-aligned silicide may be applied to form silicide 124 over the source and drain regions.
  • the FUSI surrounding the thin gate conductor 117 is formed in a last set of processes referred to as “FUSI last,” since the FET source and drain junctions including silicide 124 over the source and drain regions are fabricated before the FUSI surrounding the gate stack 118 is formed.
  • the FUSI formation temperature is, therefore, limited to about 550° C. but is compatible with standard fabrication techniques and requires relatively little process development.
  • an oxide layer 126 is deposited and chemical mechanical polishing (CMP) is employed to polish back the oxide layer 126 and planarize its surface.
  • CMP chemical mechanical polishing
  • the polishing exposes the top portion of the gate line 118 A.
  • the silicide 125 can then be used as a stop-CMP film.
  • a standard M 1 planarization process can be used, where the oxide film is substituted with a nitride/oxide film stack.
  • the CMP process then polishes the oxide layer 126 and uses the nitride as a polish-stop film.
  • the nitride film is etched to expose the top portion of the gate line 118 A.
  • a silicide forming metal such as nickel (Ni) and/or platinum (Pt) is then blanket deposited.
  • the thickness of the silicide forming metal is chosen such that, when it is reacted with the poly-Si 113 all or a substantial portion of the poly-Si will be converted into a metal-silicide.
  • the metal is chosen such that it is the main diffuser in the silicide reaction. Examples of metals that can form silicide at temperatures below about 550° C. and are the primary diffusing species are nickel (Ni) and platinum (Pt) as well as other similar metals.
  • annealing or some other reaction initiating operation is performed to cause the metal to react with the poly-Si 113 and form silicide 127 all-around the metal gate 117 .
  • the unreacted metal over the oxide 126 is selectively etched.
  • the final structure has a FUSI 127 surrounding the thin gate conductor 117 , which is exposed through the oxide 126 . Due to thermal mismatch at the temperature of silicide formation and due to volume change, the FUSI 127 induces radial strain in the reshaped nanowire 108 .
  • Poly-germanium or another suitable composition can be used as a substitute to poly-Si 113 and, in this case, in similar fashion to the process described for forming FUSI 127 , the poly-germanium can be reacted with a germanide forming metal such as nickel. Additionally, any poly-SiGe alloy can also be used to substitute poly-Si 113 . Still further, poly-Si 113 can be deposited in a poly-crystalline form or deposited in an amorphous form which is later transformed into poly-Si when exposed to high temperature.
  • the methods disclosed herein can be applied to an omega-shaped gate nanowire FET, where the nanowire 104 or reshaped nanowire 108 is attached to the buried oxide 102 such that it is not suspended.
  • the strain profile may not have perfect radial symmetry. Volume expansion plays a smaller role in producing stress in the silicided films, and it is assumed that thermal mismatch between the silicide and the nanowire is the main contributor to stress. As such, an intensity of the induced strain can be controlled and tuned by changes in the silicide formation temperature. In general, the higher the formation temperature, the higher the induced strain due to thermal mismatch.
  • the above embodiments describe a method and structure to induce radial strain in a nanowire FET channel.
  • the radial strain can be decoupled from the longitudinal strain.
  • the choice of stressor (FUSI) does not change the gate stack properties (work function).
  • a method for testing induced strain on, e.g., a nanowire 104 includes measuring device characteristics of the nanowire 104 with a strain neutral doped poly-Si gate. The device characteristics are then re-measured following conversion of the strain neutral doped poly-Si gate to a FUSI gate in a manner similar to the operations described above. Finally, a change in the device characteristics is correlated with a strain intensity.

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Abstract

A device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire.

Description

CROSS REFERENCE TO RELATED APPLICATIONS
This application is related to co-pending application 12/631,203, the entire contents of which are incorporated herein by reference.
BACKGROUND
Aspects of the present invention are directed to a nanowire field effect transistor (FET) and, more particularly, to a nanowire FET with a metal gate that is surrounded with silicide around the metal gate for inducing radial and, in some cases, longitudinal strain in the nanowire channel.
In a field effect transistor (FET) with nanowire channels, it is possible to induce longitudinal strain in the nanowires since the relatively small diameters of the nanowires leads to efficient strain coupling from a stressor. While longitudinal strain was studied in detail in planar devices and more recently longitudinal tensile strain was demonstrated with nanowire FETs, the effect of radial strain on the carrier transport in nanowires is unknown.
One of the main challenges with studying the impact of radial strain in a nanowire FET is that the gate material needs to be varied to change the strain level. Altering the gate conductor changes the induced strain but also other properties of the device such as the work function. Additionally, the use of different gate materials requires substantial processing development.
SUMMARY
In accordance with an aspect of the invention, a device is provided and includes a nanowire connecting first and second silicon-on-insulator (SOI) pads and a gate including a gate conductor surrounding the nanowire and a fully silicided material surrounding the gate conductor to radially strain the nanowire.
In accordance with an aspect of the invention, a device is provided and includes first and second pads, a nanowire, formed in a silicon-on-insulator (SOI) layer disposed over a buried oxide (BOX) layer, connecting the first and second pads and a gate surrounding the nanowire and including a dielectric adjacent the nanowire, a gate conductor adjacent the dielectric and a fully silicided material surrounding the gate conductor to radially strain the nanowire.
In accordance with an aspect of the invention, a method to induce radial strain in a field effect transistor (FET) nanowire is provided and includes surrounding the nanowire with a gate conductor and surrounding the gate conductor with poly-Si, depositing a silicide forming metal onto the poly-Si and reacting the poly-Si with the silicide forming metal to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
In accordance with another aspect of the invention, a method for testing induced strain is provided and includes measuring device characteristics with a strain neutral doped poly-Si gate, re-measuring the device characteristics following conversion of the strain neutral doped poly-Si gate to a FUSI gate and correlating a change in the device characteristics with a strain intensity.
BRIEF DESCRIPTIONS OF THE SEVERAL VIEWS OF THE DRAWINGS
The subject matter regarded as the invention is particularly pointed out and distinctly claimed in the claims at the conclusion of the specification. The foregoing and other aspects, features, and advantages of the invention are apparent from the following detailed description taken in conjunction with the accompanying drawings in which:
FIG. 1 is a perspective view of a nanowire under strain;
FIGS. 2A and 2B are views of a nanowire extending across a recessed oxide;
FIGS. 3A and 3B are views of a reshaped nanowire extending across the recessed oxide;
FIGS. 4A and 4B are views of a nanowire and a poly-Si coated with a gate dielectric and partially coated with TaN;
FIGS. 4C and 4D are views of the nanowire and the poly-Si fully coated with the gate dielectric and the TaN;
FIG. 5 is a side sectional view of a poly-Si gate with epitaxy, silicide and oxide coatings; and
FIG. 6 is a side sectional view of a FUSI stressor with the structures of FIG. 5.
 DETAILED DESCRIPTION
The present techniques provide a gate-all-around (GAA) nanowire field effect transistor (FET) as well as methods for fabricating the same. In this discussion, reference will be made to various drawings that illustrate embodiments of the present teachings. Since the drawings of the embodiments of the present teachings are provided for illustrative purposes, the structures contained therein are not drawn to scale.
The present methods are described using silicon (Si) nanowires and Si processing. However, the present techniques can also be practiced with other semiconductor materials such as, for example, germanium (Ge) or III-V semiconductors. When non-Si-containing semiconductors are used, the processing steps of the present teachings are basically the same except that growth temperature and dopant species applied are adapted to the specific semiconductor used. Use of Si-containing semiconductor materials such as Si, silicon germanium (SiGe), Si/SiGe, silicon carbide (SiC) or silicon germanium carbide (SiGeC) are exemplary. It is noted that a portion of the nanowires is used herein as the device channel or body.
With reference to FIG. 1, in an FET with a nanowire channel 10, it is possible to relatively efficiently induce radial strain (Δr/r) as well as longitudinal strain (ΔL/L), with r and L being the nanowire's radius and length, respectively, and Δr and ΔL being the change in radius and the change in length, respectively, as a result of stress. The small diameter of the nanowire 11 leads to efficient strain coupling from a stressor with a residual stress, P, such as the material that would normally surround the nanowire 11 that generates a residual stress, C, in the nanowire. While longitudinal strain has been studied in detail in planar devices and, more recently, longitudinal tensile strain was demonstrated with nanowire FETs, the effect of radial strain on the carrier transport in nanowires is currently unknown due to the fact that, in studying the impact of radial strain in a nanowire FET, it has been necessary to vary the gate conductor material to change the strain level. While altering the gate conductor material changes the induced strain, the alteration requires substantial processing development and the varied gate conductor material changes other properties of the relevant device, such as the work function and threshold voltage.
In accordance with aspects of the present invention, a method to induce radial strain and, in some cases, longitudinal strain in a nanowire channel, without the need to change the gate conductor or the process that is used to define the gate is provided and makes use of a thin metal all-around-gate (e.g., about 2-4 nm and, in some cases, about 3 nm thick tantalum nitride (TaN)) while the “filler” material that connects all the nanowires' metal gates and forms a solid gate line is initially poly-Si that is later converted into fully silicided material (FUSI). The FUSI surrounding the metal gate effectively induces strain in the nanowire channel, but does not impact other device properties (such as the work function) since the latter is set by the metal gate. The gate definition process, therefore, remains substantially constant even if various silicides are used for the FUSI. Once built, the device can be tested with a strain neutral doped poly-Si gate, and then retested with a FUSI gate to study the impact of strain.
With reference to FIGS. 2-6, the device structure and process operations are summarized and relate to embodiments in which the FUSI gate is formed last.
With reference to FIGS. 2A and 2B, a wafer is provided and includes a Si substrate 101, a buried oxide (BOX) layer 102 and a silicon-on-insulator (SOI) layer 103. The wafer can be fabricated using methods such as Separation by IMplanted OXygen (SIMOX) or wafer bonding (for example, SmartCut™). These wafer fabrication techniques are known to those of skill in the art and thus are not described further herein. Also, the substitution of other SOI substrates known in the art for the SOI on BOX configuration described herein may be made and would be within the scope of the present teachings.
Nanowires 104 connected to SOI pads 103A are patterned in SOI layer 103 to form a ladder-like structure. SOI layer 103 is made to have a typical thickness of about 20-30 nanometers (nm). As a result the as-patterned nanowires 104 have a height that is about 20-30 nm. A width of the nanowires 104 can be in the range of about 10-30 nm. The patterning of the nanowires 104 and SOI pads 103A may be achieved by lithography (e.g., optical or e-beam) followed by reactive ion etching (RIE) or by a sidewall transfer technique. These patterning techniques are known to those of skill in the art and thus are not described further herein.
The nanowires 104 can be suspended or released from the BOX layer 102 by etching and a recessing of the BOX layer 102 under the nanowires 104. The nanowires 104 thus form a suspended bridge between the SOI pads 103A over recessed oxide 105. The recessing of the BOX layer 102 can be achieved with a diluted hydrofluoric (DHF) etch. The lateral component of this etching undercuts the BOX layer 102 under the nanowires 104. Alternatively, the suspension of the nanowires 104 may be obtained during an annealing process to re-shape the nanowires 104.
While SOI substrates provide an easy path to define and suspend nanowires 104, it is possible to obtain suspended nanowires 104 with other substrates. For example, a SiGe/Si stack epitaxially grown on bulk Si wafers can also be patterned to form the nanowires 104. The SiGe layer can be used as a sacrificial layer (analogous to the BOX layer 102) which is undercut to suspend the nanowires 104.
The nanowires 104 are then reshaped to form reshaped nanowires 108, as shown in FIGS. 3A and 3B. Here, the reshaping refers to a smoothing of the respective surfaces of the nanowires 104 to thereby change their respective cross-sections to be more cylindrical, and to a thinning of the respective nanowire 104 bodies by moving silicon from the nanowire 104 bodies to the SOI pads 103A. As an example, the reshaped nanowires 108 may be formed by way of an annealing process during which the SOI wafer contacts an inert gas at a temperature, pressure and for a duration sufficient to cause Si to migrate from the nanowires 104 to the SOI pads 103A. Here, the term “inert gas” refers to a gas that does not react with Si and may include hydrogen (H2), xenon (Xe), helium (He) and potentially others.
With reference to FIGS. 3A and 3B, it is seen that the wafer may be annealed in an exemplary H2 gas. Shortly before H2 annealing, native oxide is etched off from the surfaces of the nanowires 104 and the SOI pads 103A. The annealing in H2 smoothes the nanowire sidewalls, realigns the sidewalls and the SOI pads 103A and re-shapes the nanowire 104 cross-section from a rectangular cross-section to a more cylindrical cross-section. The H2 anneal may also thin the nanowire 104 body by re-distributing Si to the SOI pads 103A.
According to an exemplary embodiment, the inert gas anneal may be performed with a gas pressure of from about 30 torr to about 1000 torr, at a temperature of from about 600 degrees Celsius (° C.) to about 1100° C. and for a duration of about 1-120 minutes. In general, the rate of Si re-distribution increases with temperature and decrease with an increase in pressure.
With reference to FIGS. 4A-4D, a conformal gate dielectric 112 is deposited over the structure. The gate dielectric 112 may include silicon dioxide (SiO2), silicon oxynitride (SiON), hafnium oxide (HfO2) or any other suitable hi-K dielectric(s) and may be deposited over SOI pads 103A and around the reshaped nanowires 108 using chemical vapor deposition (CVD), atomic layer deposition (ALD) or an oxidation furnace in the case of SiO2 and SiON. A conformal deposition of a thin gate conductor 117 of, e.g., TaN or TiN, is then formed and is followed by a deposition of poly-Si 113 to form a gate stack 118 perimetrically surrounding the reshaped nanowire 108. A mask 115 is employed to facilitate the etching of a gate line by reactive ion etching (RIE). The thin gate conductor 117 may be removed by RIE as shown in FIGS. 4A and 4B. Alternatively, the removal of the thin gate conductor 117 from surfaces outside gate line 118A may require an additional wet etch step as shown in FIGS. 4C and 4D.
As an example, to fabricate a poly-Si gate, a poly-Si 113 is blanket deposited. Using lithography and selective RIE (e.g., hydrogen bromide (HBr)-based chemistry) the poly-Si 113 is selectively etched except where the etching is blocked by mask 115 to define a cleared region 119. The RIE process includes a first phase, during which etching is directional to obtain a substantially straight profile for the gate line 118A, and a second phase, during which the gate line 118A is trimmed sideways by an amount sufficient to clear the gate material under the reshaped nanowires 108 in the regions outside the gate stack 118. The gate etching can include the etching of the thin gate conductor 117, as shown in FIGS. 4A and 4B, or it can be limited to an etching of the poly-Si 113 while leaving the thin gate conductor 117 relatively intact, as illustrated in FIGS. 4C and 4D.
With reference now to FIGS. 5 and 6, gate sidewall spacers 121 are formed and epitaxy 122 may be selectively used to thicken the reshaped nanowire 108 portions that are not encapsulated by the gate stack 118 and sidewall spaces. The SOI pads 103A may also be thickened as necessary by epitaxy 122. Epitaxy 122 can include in-situ doping to incorporate dopants into the source/drain regions. Alternatively, ion-implantation can be used to dope the source and drain region. A self-aligned silicide may be applied to form silicide 124 over the source and drain regions.
In accordance with embodiments of the invention, the FUSI surrounding the thin gate conductor 117 is formed in a last set of processes referred to as “FUSI last,” since the FET source and drain junctions including silicide 124 over the source and drain regions are fabricated before the FUSI surrounding the gate stack 118 is formed. The FUSI formation temperature is, therefore, limited to about 550° C. but is compatible with standard fabrication techniques and requires relatively little process development.
As shown in FIG. 5, an oxide layer 126 is deposited and chemical mechanical polishing (CMP) is employed to polish back the oxide layer 126 and planarize its surface. The polishing exposes the top portion of the gate line 118A. The silicide 125 can then be used as a stop-CMP film. Alternatively, a standard M1 planarization process can be used, where the oxide film is substituted with a nitride/oxide film stack. The CMP process then polishes the oxide layer 126 and uses the nitride as a polish-stop film. The nitride film is etched to expose the top portion of the gate line 118A.
A silicide forming metal, such as nickel (Ni) and/or platinum (Pt), is then blanket deposited. The thickness of the silicide forming metal is chosen such that, when it is reacted with the poly-Si 113 all or a substantial portion of the poly-Si will be converted into a metal-silicide. To circumvent the formation of voids, the metal is chosen such that it is the main diffuser in the silicide reaction. Examples of metals that can form silicide at temperatures below about 550° C. and are the primary diffusing species are nickel (Ni) and platinum (Pt) as well as other similar metals. Following this metal deposition, annealing or some other reaction initiating operation is performed to cause the metal to react with the poly-Si 113 and form silicide 127 all-around the metal gate 117.
With reference to FIG. 6, the unreacted metal over the oxide 126 is selectively etched. The final structure has a FUSI 127 surrounding the thin gate conductor 117, which is exposed through the oxide 126. Due to thermal mismatch at the temperature of silicide formation and due to volume change, the FUSI 127 induces radial strain in the reshaped nanowire 108.
Poly-germanium or another suitable composition can be used as a substitute to poly-Si 113 and, in this case, in similar fashion to the process described for forming FUSI 127, the poly-germanium can be reacted with a germanide forming metal such as nickel. Additionally, any poly-SiGe alloy can also be used to substitute poly-Si 113. Still further, poly-Si 113 can be deposited in a poly-crystalline form or deposited in an amorphous form which is later transformed into poly-Si when exposed to high temperature.
In accordance with further embodiments, the methods disclosed herein can be applied to an omega-shaped gate nanowire FET, where the nanowire 104 or reshaped nanowire 108 is attached to the buried oxide 102 such that it is not suspended. In this non-suspended case, however, the strain profile may not have perfect radial symmetry. Volume expansion plays a smaller role in producing stress in the silicided films, and it is assumed that thermal mismatch between the silicide and the nanowire is the main contributor to stress. As such, an intensity of the induced strain can be controlled and tuned by changes in the silicide formation temperature. In general, the higher the formation temperature, the higher the induced strain due to thermal mismatch.
The above embodiments describe a method and structure to induce radial strain in a nanowire FET channel. The radial strain can be decoupled from the longitudinal strain. The choice of stressor (FUSI) does not change the gate stack properties (work function).
In accordance with further aspects, a method for testing induced strain on, e.g., a nanowire 104 is provided and includes measuring device characteristics of the nanowire 104 with a strain neutral doped poly-Si gate. The device characteristics are then re-measured following conversion of the strain neutral doped poly-Si gate to a FUSI gate in a manner similar to the operations described above. Finally, a change in the device characteristics is correlated with a strain intensity.
While the disclosure has been described with reference to exemplary embodiments, it will be understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the scope of the disclosure. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the disclosure without departing from the essential scope thereof. Therefore, it is intended that the disclosure not be limited to the particular exemplary embodiment disclosed as the best mode contemplated for carrying out this disclosure, but that the disclosure will include all embodiments falling within the scope of the appended claims.

Claims (22)

1. A device, comprising:
a nanowire connecting first and second silicon-on-insulator (SOI) pads; and
a gate including a gate conductor surrounding an entire surface of the nanowire along a length thereof and a fully silicided material surrounding the gate conductor to radially strain the nanowire,
the entire surface of the nanowire along the length of the nanowire being defined as all upper, lower and side surface of the nanowire along the length of the nanowire.
2. The device according to claim 1, wherein a material of the gate conductor is selected from the group comprising tantalum nitride (TaN) and titanium nitride (TiN).
3. The device according to claim 1, wherein the gate conductor comprises a film having a thickness of about 2-4 nm.
4. The device according to claim 1, wherein the fully silicided material comprises a silicide that forms at or below about 550° C.
5. The device according to claim 1, wherein the fully silicided material comprises at least one of nickel (Ni) and platinum (Pt).
6. The device according to claim 1, wherein a material of the gate conductor is determinative of a work function of the gate conductor independent of the fully silicided material.
7. A device, comprising:
first and second pads;
a nanowire, formed in a silicon-on-insulator (SOI) layer disposed over a buried oxide (BOX) layer, connecting the first and second pads; and
a gate surrounding the nanowire and including a dielectric adjacent the nanowire, a gate including a dielectric adjacent the nanowire, a gate conductor adjacent the dielectric and a fully silicided material surrounding the gate conductor to radially strain the nanowire,
the entire surface of the nanowire along the length of the nanowire being defined as all upper, lower and side surface of the nanowire along the length of the nanowire.
8. The device according to claim 7, wherein the nanowire is substantially cylindrical.
9. The device according to claim 7, wherein the gate perimetrically surrounds the nanowire.
10. The device according to claim 7, wherein a material of the dielectric is selected from the group comprising silicon dioxide (SiO2), silicon oxynitride (SiON) and hafnium oxide (HfO2).
11. The device according to claim 7, wherein a material of the gate conductor is selected from the group comprising tantalum nitride (TaN) and titanium nitride (TiN).
12. The device according to claim 7, wherein the gate conductor comprises a film having a thickness of about 2-4 nm.
13. The device according to claim 7, wherein the fully silicided material comprises a silicide that forms at or below about 550° C.
14. The device according to claim 7, wherein the fully silicided material comprises at least one of nickel (Ni) and platinum (Pt).
15. The device according to claim 7, wherein a material of the gate conductor is determinative of a work function of the gate conductor independent of the fully silicided material.
16. The device according to claim 7, further comprising:
spacers disposed on opposite sides of the gate conductor and the fully silicided material;
an epitaxy to thicken nanowire portions not surrounded by the gate;
a self-aligned silicide adjacent to the epitaxy; and
an oxide adjacent to the epitaxy.
17. A method to induce radial strain in a field effect transistor (FET) nanowire, the method comprising:
surrounding an entire surface of the nanowire along a length thereof with a gate conductor and surrounding the gate conductor with poly-Si; the entire surface of the nanowire along the length of the nanowire being defined as all upper, lower and side surface of the nanowire along the length of the nanowire;
depositing a silicide forming metal onto the poly-Si; and
reacting the poly-Si with the silicide forming metal to form a fully silicided (FUSI) material to induce radial strain in the nanowire.
18. The method according to claim 17, further comprising fabricating source and drain regions relative to the nanowire prior to the depositing and reacting.
19. The method according to claim 17, wherein the forming of the FUSI comprises:
depositing an oxide layer; and
exposing a portion of the poly-Si through the oxide layer onto which the silicide forming metal is deposited.
20. The method according to claim 17, wherein the depositing comprises depositing an amount of the silicide forming metal sufficient to fully convert the poly-Si into silicide.
21. The method according to claim 17, wherein an intensity of the induced strain is tuned by a change of a silicide formation temperature.
22. A method for testing induced strain, comprising:
measuring device characteristics with a strain neutral doped poly-Si gate;
re-measuring the device characteristics following conversion of the strain neutral doped poly-Si gate to a FUSI gate; and
correlating a change in the device characteristics with a strain intensity.
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