US8261025B2 - Software pipelining on a network on chip - Google Patents

Software pipelining on a network on chip Download PDF

Info

Publication number
US8261025B2
US8261025B2 US11938376 US93837607A US8261025B2 US 8261025 B2 US8261025 B2 US 8261025B2 US 11938376 US11938376 US 11938376 US 93837607 A US93837607 A US 93837607A US 8261025 B2 US8261025 B2 US 8261025B2
Authority
US
Grant status
Grant
Patent type
Prior art keywords
memory
stage
communications
data
ip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related, expires
Application number
US11938376
Other versions
US20090125574A1 (en )
Inventor
Eric O. Mejdrich
Paul E. Schardt
Robert A. Shearer
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/15Interconnection of switching modules
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/10Switching fabric construction
    • H04L49/109Switching fabric construction integrated on microchip, e.g. switch-on-chip
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/90Queuing arrangements
    • H04L49/901Storage descriptor, e.g. read or write pointers
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/25Routing or path finding through a switch fabric
    • H04L49/252Store and forward routing
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L49/00Packet switching elements
    • H04L49/30Peripheral units, e.g. input or output ports
    • H04L49/3036Shared queuing

Abstract

Memory sharing in a software pipeline on a network on chip (‘NOC’), the NOC including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution; allocating memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The field of the invention is data processing, or, more specifically apparatus and methods for data processing with a network on chip (‘NOC’).

2. Description of Related Art

There are two widely used paradigms of data processing; multiple instructions, multiple data (‘MIMD’) and single instruction, multiple data (‘SIMD’). In MIMD processing, a computer program is typically characterized as one or more threads of execution operating more or less independently, each requiring fast random access to large quantities of shared memory. MIMD is a data processing paradigm optimized for the particular classes of programs that fit it, including, for example, word processors, spreadsheets, database managers, many forms of telecommunications such as browsers, for example, and so on.

SIMD is characterized by a single program running simultaneously in parallel on many processors, each instance of the program operating in the same way but on separate items of data. SIMD is a data processing paradigm that is optimized for the particular classes of applications that fit it, including, for example, many forms of digital signal processing, vector processing, and so on.

There is another class of applications, however, including many real-world simulation programs, for example, for which neither pure SIMD nor pure MIMD data processing is optimized. That class of applications includes applications that benefit from parallel processing and also require fast random access to shared memory. For that class of programs, a pure MIMD system will not provide a high degree of parallelism and a pure SIMD system will not provide fast random access to main memory stores.

SUMMARY OF THE INVENTION

Methods, apparatus, and computer program products for a network on chip (‘NOC’) that shares memory in a software pipeline and includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, including segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage executing in a thread of execution on an IP block; allocating, by at least one of the stages, memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated; determining, by at least one stage in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and deallocating the shared memory.

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts of exemplary embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 sets forth a block diagram of automated computing machinery comprising an exemplary computer useful in data processing with a NOC according to embodiments of the present invention.

FIG. 2 sets forth a functional block diagram of an example NOC according to embodiments of the present invention.

FIG. 3 sets forth a functional block diagram of a further example NOC according to embodiments of the present invention.

FIG. 4 sets forth a flow chart illustrating an exemplary method for data processing with a NOC according to embodiments of the present invention.

FIG. 5 sets forth a data flow diagram an example software pipeline on a NOC according to embodiments of the present invention, where the NOC is capable of sharing memory in a software pipeline.

FIG. 6 sets forth a flow chart illustrating an exemplary method of software pipelining on a NOC according to embodiments of the present invention.

FIG. 7 sets forth a flow chart illustrating an exemplary method of sharing memory in a software pipeline according to embodiments of the present invention.

DETAILED DESCRIPTION OF EXEMPLARY EMBODIMENTS

Exemplary apparatus and methods for data processing with a NOC in accordance with the present invention are described with reference to the accompanying drawings, beginning with FIG. 1. FIG. 1 sets forth a block diagram of automated computing machinery comprising an exemplary computer (152) useful in data processing with a NOC according to embodiments of the present invention. The computer (152) of FIG. 1 includes at least one computer processor (156) or ‘CPU’ as well as random access memory (168) (‘RAM’) which is connected through a high speed memory bus (166) and bus adapter (158) to processor (156) and to other components of the computer (152).

Stored in RAM (168) is an application program (184), a module of user-level computer program instructions for carrying out particular data processing tasks such as, for example, word processing, spreadsheets, database operations, video gaming, stock market simulations, atomic quantum process simulations, or other user-level applications. Also stored in RAM (168) is an operating system (154). Operating systems useful data processing with a NOC according to embodiments of the present invention include UNIX™, Linux™, Microsoft XP™, AIX™, IBM's i5/OS™, and others as will occur to those of skill in the art. The operating system (154) and the application (184) in the example of FIG. 1 are shown in RAM (168), but many components of such software typically are stored in non-volatile memory also, such as, for example, on a disk drive (170).

The example computer (152) includes two example NOCs according to embodiments of the present invention: a video adapter (209) and a coprocessor (157). The video adapter (209) is an example of an I/O adapter specially designed for graphic output to a display device (180) such as a display screen or computer monitor. Video adapter (209) is connected to processor (156) through a high speed video bus (164), bus adapter (158), and the front side bus (162), which is also a high speed bus.

The example NOC coprocessor (157) is connected to processor (156) through bus adapter (158), and front side buses (162 and 163), which is also a high speed bus. The NOC coprocessor of FIG. 1 is optimized to accelerate particular data processing tasks at the behest of the main processor (156).

The example NOC video adapter (209) and NOC coprocessor (157) of FIG. 1 each include a NOC according to embodiments of the present invention, including integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers. The NOC video adapter and the NOC coprocessor are optimized for programs that use parallel processing and also require fast random access to shared memory. The details of the NOC structure and operation are discussed below with reference to FIGS. 2-4.

The computer (152) of FIG. 1 includes disk drive adapter (172) coupled through expansion bus (160) and bus adapter (158) to processor (156) and other components of the computer (152). Disk drive adapter (172) connects non-volatile data storage to the computer (152) in the form of disk drive (170). Disk drive adapters useful in computers for data processing with a NOC according to embodiments of the present invention include Integrated Drive Electronics (‘IDE’) adapters, Small Computer System Interface (‘SCSI’) adapters, and others as will occur to those of skill in the art. Non-volatile computer memory also may be implemented for as an optical disk drive, electrically erasable programmable read-only memory (so-called ‘EEPROM’ or ‘Flash’ memory), RAM drives, and so on, as will occur to those of skill in the art.

The example computer (152) of FIG. 1 includes one or more input/output (‘I/O’) adapters (178). I/O adapters implement user-oriented input/output through, for example, software drivers and computer hardware for controlling output to display devices such as computer display screens, as well as user input from user input devices (181) such as keyboards and mice.

The exemplary computer (152) of FIG. 1 includes a communications adapter (167) for data communications with other computers (182) and for data communications with a data communications network (100). Such data communications may be carried out serially through RS-232 connections, through external buses such as a Universal Serial Bus (‘USB’), through data communications data communications networks such as IP data communications networks, and in other ways as will occur to those of skill in the art. Communications adapters implement the hardware level of data communications through which one computer sends data communications to another computer, directly or through a data communications network. Examples of communications adapters useful for data processing with a NOC according to embodiments of the present invention include modems for wired dial-up communications, Ethernet (IEEE 802.3) adapters for wired data communications network communications, and 802.11 adapters for wireless data communications network communications.

For further explanation, FIG. 2 sets forth a functional block diagram of an example NOC (102) according to embodiments of the present invention. The NOC in the example of FIG. 1 is implemented on a ‘chip’ (100), that is, on an integrated circuit. The NOC (102) of FIG. 2 includes integrated processor (‘IP’) blocks (104), routers (110), memory communications controllers (106), and network interface controllers (108). Each IP block (104) is adapted to a router (110) through a memory communications controller (106) and a network interface controller (108). Each memory communications controller controls communications between an IP block and memory, and each network interface controller (108) controls inter-IP block communications through routers (110).

In the NOC (102) of FIG. 2, each IP block represents a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC. The term ‘IP block’ is sometimes expanded as ‘intellectual property block,’ effectively designating an IP block as a design that is owned by a party, that is the intellectual property of a party, to be licensed to other users or designers of semiconductor circuits. In the scope of the present invention, however, there is no requirement that IP blocks be subject to any particular ownership, so the term is always expanded in this specification as ‘integrated processor block.’ IP blocks, as specified here, are reusable units of logic, cell, or chip layout design that may or may not be the subject of intellectual property. IP blocks are logic cores that can be formed as ASIC chip designs or FPGA logic designs.

One way to describe IP blocks by analogy is that IP blocks are for NOC design what a library is for computer programming or a discrete integrated circuit component is for printed circuit board design. In NOCs according to embodiments of the present invention, IP blocks may be implemented as generic gate netlists, as complete special purpose or general purpose microprocessors, or in other ways as may occur to those of skill in the art. A netlist is a Boolean-algebra representation (gates, standard cells) of an IP block's logical-function, analogous to an assembly-code listing for a high-level program application. NOCs also may be implemented, for example, in synthesizable form, described in a hardware description language such as Verilog or VHDL. In addition to netlist and synthesizable implementation, NOCs also may be delivered in lower-level, physical descriptions. Analog IP block elements such as SERDES, PLL, DAC, ADC, and so on, may be distributed in a transistor-layout format such as GDSII. Digital elements of IP blocks are sometimes offered in layout format as well.

Each IP block (104) in the example of FIG. 2 is adapted to a router (110) through a memory communications controller (106). Each memory communication controller is an aggregation of synchronous and asynchronous logic circuitry adapted to provide data communications between an IP block and memory. Examples of such communications between IP blocks and memory include memory load instructions and memory store instructions. The memory communications controllers (106) are described in more detail below with reference to FIG. 3.

Each IP block (104) in the example of FIG. 2 is also adapted to a router (110) through a network interface controller (108). Each network interface controller (108) controls communications through routers (110) between IP blocks (104). Examples of communications between IP blocks include messages carrying data and instructions for processing the data among IP blocks in parallel applications and in pipelined applications. The network interface controllers (108) are described in more detail below with reference to FIG. 3.

Each IP block (104) in the example of FIG. 2 is adapted to a router (110). The routers (110) and links (120) among the routers implement the network operations of the NOC. The links (120) are packets structures implemented on physical, parallel wire buses connecting all the routers. That is, each link is implemented on a wire bus wide enough to accommodate simultaneously an entire data switching packet, including all header information and payload data. If a packet structure includes 64 bytes, for example, including an eight byte header and 56 bytes of payload data, then the wire bus subtending each link is 64 bytes wise, 512 wires. In addition, each link is bi-directional, so that if the link packet structure includes 64 bytes, the wire bus actually contains 1024 wires between each router and each of its neighbors in the network. A message can includes more than one packet, but each packet fits precisely onto the width of the wire bus. If the connection between the router and each section of wire bus is referred to as a port, then each router includes five ports, one for each of four directions of data transmission on the network and a fifth port for adapting the router to a particular IP block through a memory communications controller and a network interface controller.

Each memory communications controller (106) in the example of FIG. 2 controls communications between an IP block and memory. Memory can include off-chip main RAM (112), memory (115) connected directly to an IP block through a memory communications controller (106), on-chip memory enabled as an IP block (114), and on-chip caches. In the NOC of FIG. 2, either of the on-chip memories (114, 115), for example, may be implemented as on-chip cache memory. All these forms of memory can be disposed in the same address space, physical addresses or virtual addresses, true even for the memory attached directly to an IP block. Memory-addressed messages therefore can be entirely bidirectional with respect to IP blocks, because such memory can be addressed directly from any IP block anywhere on the network. Memory (114) on an IP block can be addressed from that IP block or from any other IP block in the NOC. Memory (115) attached directly to a memory communication controller can be addressed by the IP block that is adapted to the network by that memory communication controller—and can also be addressed from any other IP block anywhere in the NOC.

The example NOC includes two memory management units (‘MMUs’) (107, 109), illustrating two alternative memory architectures for NOCs according to embodiments of the present invention. MMU (107) is implemented with an IP block, allowing a processor within the IP block to operate in virtual memory while allowing the entire remaining architecture of the NOC to operate in a physical memory address space. The MMU (109) is implemented off-chip, connected to the NOC through a data communications port (116). The port (116) includes the pins and other interconnections required to conduct signals between the NOC and the MMU, as well as sufficient intelligence to convert message packets from the NOC packet format to the bus format required by the external MMU (109). The external location of the MMU means that all processors in all IP blocks of the NOC can operate in virtual memory address space, with all conversions to physical addresses of the off-chip memory handled by the off-chip MMU (109).

In addition to the two memory architectures illustrated by use of the MMUs (107, 109), data communications port (118) illustrates a third memory architecture useful in NOCs according to embodiments of the present invention. Port (118) provides a direct connection between an IP block (104) of the NOC (102) and off-chip memory (112). With no MMU in the processing path, this architecture provides utilization of a physical address space by all the IP blocks of the NOC. In sharing the address space bi-directionally, all the IP blocks of the NOC can access memory in the address space by memory-addressed messages, including loads and stores, directed through the IP block connected directly to the port (118). The port (118) includes the pins and other interconnections required to conduct signals between the NOC and the off-chip memory (112), as well as sufficient intelligence to convert message packets from the NOC packet format to the bus format required by the off-chip memory (112).

In the example of FIG. 2, one of the IP blocks is designated a host interface processor (105). A host interface processor (105) provides an interface between the NOC and a host computer (152) in which the NOC may be installed and also provides data processing services to the other IP blocks on the NOC, including, for example, receiving and dispatching among the IP blocks of the NOC data processing requests from the host computer. A NOC may, for example, implement a video graphics adapter (209) or a coprocessor (157) on a larger computer (152) as described above with reference to FIG. 1. In the example of FIG. 2, the host interface processor (105) is connected to the larger host computer through a data communications port (115). The port (115) includes the pins and other interconnections required to conduct signals between the NOC and the host computer, as well as sufficient intelligence to convert message packets from the NOC to the bus format required by the host computer (152). In the example of the NOC coprocessor in the computer of FIG. 1, such a port would provide data communications format translation between the link structure of the NOC coprocessor (157) and the protocol required for the front side bus (163) between the NOC coprocessor (157) and the bus adapter (158).

For further explanation, FIG. 3 sets forth a functional block diagram of a further example NOC according to embodiments of the present invention. The example NOC of FIG. 3 is similar to the example NOC of FIG. 2 in that the example NOC of FIG. 3 is implemented on a chip (100 on FIG. 2), and the NOC (102) of FIG. 3 includes integrated processor (‘IP’) blocks (104), routers (110), memory communications controllers (106), and network interface controllers (108). Each IP block (104) is adapted to a router (110) through a memory communications controller (106) and a network interface controller (108). Each memory communications controller controls communications between an IP block and memory, and each network interface controller (108) controls inter-IP block communications through routers (110). In the example of FIG. 3, one set (122) of an IP block (104) adapted to a router (110) through a memory communications controller (106) and network interface controller (108) is expanded to aid a more detailed explanation of their structure and operations. All the IP blocks, memory communications controllers, network interface controllers, and routers in the example of FIG. 3 are configured in the same manner as the expanded set (122).

In the example of FIG. 3, each IP block (104) includes a computer processor (126) and I/O functionality (124). In this example, computer memory is represented by a segment of random access memory (‘RAM’) (128) in each IP block (104). The memory, as described above with reference to the example of FIG. 2, can occupy segments of a physical address space whose contents on each IP block are addressable and accessible from any IP block in the NOC. The processors (126), I/O capabilities (124), and memory (128) on each IP block effectively implement the IP blocks as generally programmable microcomputers. As explained above, however, in the scope of the present invention, IP blocks generally represent reusable units of synchronous or asynchronous logic used as building blocks for data processing within a NOC. Implementing IP blocks as generally programmable microcomputers, therefore, although a common embodiment useful for purposes of explanation, is not a limitation of the present invention.

In the NOC (102) of FIG. 3, each memory communications controller (106) includes a plurality of memory communications execution engines (140). Each memory communications execution engine (140) is enabled to execute memory communications instructions from an IP block (104), including bidirectional memory communications instruction flow (142, 144, 145) between the network and the IP block (104). The memory communications instructions executed by the memory communications controller may originate, not only from the IP block adapted to a router through a particular memory communications controller, but also from any IP block (104) anywhere in the NOC (102). That is, any IP block in the NOC can generate a memory communications instruction and transmit that memory communications instruction through the routers of the NOC to another memory communications controller associated with another IP block for execution of that memory communications instruction. Such memory communications instructions can include, for example, translation lookaside buffer control instructions, cache control instructions, barrier instructions, and memory load and store instructions.

Each memory communications execution engine (140) is enabled to execute a complete memory communications instruction separately and in parallel with other memory communications execution engines. The memory communications execution engines implement a scalable memory transaction processor optimized for concurrent throughput of memory communications instructions. The memory communications controller (106) supports multiple memory communications execution engines (140) all of which run concurrently for simultaneous execution of multiple memory communications instructions. A new memory communications instruction is allocated by the memory communications controller (106) to a memory communications engine (140) and the memory communications execution engines (140) can accept multiple response events simultaneously. In this example, all of the memory communications execution engines (140) are identical. Scaling the number of memory communications instructions that can be handled simultaneously by a memory communications controller (106), therefore, is implemented by scaling the number of memory communications execution engines (140).

In the NOC (102) of FIG. 3, each network interface controller (108) is enabled to convert communications instructions from command format to network packet format for transmission among the IP blocks (104) through routers (110). The communications instructions are formulated in command format by the IP block (104) or by the memory communications controller (106) and provided to the network interface controller (108) in command format. The command format is a native format that conforms to architectural register files of the IP block (104) and the memory communications controller (106). The network packet format is the format required for transmission through routers (110) of the network. Each such message is composed of one or more network packets. Examples of such communications instructions that are converted from command format to packet format in the network interface controller include memory load instructions and memory store instructions between IP blocks and memory. Such communications instructions may also include communications instructions that send messages among IP blocks carrying data and instructions for processing the data among IP blocks in parallel applications and in pipelined applications.

In the NOC (102) of FIG. 3, each IP block is enabled to send memory-address-based communications to and from memory through the IP block's memory communications controller and then also through its network interface controller to the network. A memory-address-based communications is a memory access instruction, such as a load instruction or a store instruction, that is executed by a memory communication execution engine of a memory communications controller of an IP block. Such memory-address-based communications typically originate in an IP block, formulated in command format, and handed off to a memory communications controller for execution.

Many memory-address-based communications are executed with message traffic, because any memory to be accessed may be located anywhere in the physical memory address space, on-chip or off-chip, directly attached to any memory communications controller in the NOC, or ultimately accessed through any IP block of the NOC—regardless of which IP block originated any particular memory-address-based communication. All memory-address-based communication that are executed with message traffic are passed from the memory communications controller to an associated network interface controller for conversion (136) from command format to packet format and transmission through the network in a message. In converting to packet format, the network interface controller also identifies a network address for the packet in dependence upon the memory address or addresses to be accessed by a memory-address-based communication. Memory address based messages are addressed with memory addresses. Each memory address is mapped by the network interface controllers to a network address, typically the network location of a memory communications controller responsible for some range of physical memory addresses. The network location of a memory communication controller (106) is naturally also the network location of that memory communication controller's associated router (110), network interface controller (108), and IP block (104). The instruction conversion logic (136) within each network interface controller is capable of converting memory addresses to network addresses for purposes of transmitting memory-address-based communications through routers of a NOC.

Upon receiving message traffic from routers (110) of the network, each network interface controller (108) inspects each packet for memory instructions. Each packet containing a memory instruction is handed to the memory communications controller (106) associated with the receiving network interface controller, which executes the memory instruction before sending the remaining payload of the packet to the IP block for further processing. In this way, memory contents are always prepared to support data processing by an IP block before the IP block begins execution of instructions from a message that depend upon particular memory content.

In the NOC (102) of FIG. 3, each IP block (104) is enabled to bypass its memory communications controller (106) and send inter-IP block, network-addressed communications (146) directly to the network through the IP block's network interface controller (108). Network-addressed communications are messages directed by a network address to another IP block. Such messages transmit working data in pipelined applications, multiple data for single program processing among IP blocks in a SIMD application, and so on, as will occur to those of skill in the art. Such messages are distinct from memory-address-based communications in that they are network addressed from the start, by the originating IP block which knows the network address to which the message is to be directed through routers of the NOC. Such network-addressed communications are passed by the IP block through it I/O functions (124) directly to the IP block's network interface controller in command format, then converted to packet format by the network interface controller and transmitted through routers of the NOC to another IP block. Such network-addressed communications (146) are bi-directional, potentially proceeding to and from each IP block of the NOC, depending on their use in any particular application. Each network interface controller, however, is enabled to both send and receive (142) such communications to and from an associated router, and each network interface controller is enabled to both send and receive (146) such communications directly to and from an associated IP block, bypassing an associated memory communications controller (106).

Each network interface controller (108) in the example of FIG. 3 is also enabled to implement virtual channels on the network, characterizing network packets by type. Each network interface controller (108) includes virtual channel implementation logic (138) that classifies each communication instruction by type and records the type of instruction in a field of the network packet format before handing off the instruction in packet form to a router (110) for transmission on the NOC. Examples of communication instruction types include inter-IP block network-address-based messages, request messages, responses to request messages, invalidate messages directed to caches; memory load and store messages; and responses to memory load messages, and so on.

Each router (110) in the example of FIG. 3 includes routing logic (130), virtual channel control logic (132), and virtual channel buffers (134). The routing logic typically is implemented as a network of synchronous and asynchronous logic that implements a data communications protocol stack for data communication in the network formed by the routers (110), links (120), and bus wires among the routers. The routing logic (130) includes the functionality that readers of skill in the art might associate in off-chip networks with routing tables, routing tables in at least some embodiments being considered too slow and cumbersome for use in a NOC. Routing logic implemented as a network of synchronous and asynchronous logic can be configured to make routing decisions as fast as a single clock cycle. The routing logic in this example routes packets by selecting a port for forwarding each packet received in a router. Each packet contains a network address to which the packet is to be routed. Each router in this example includes five ports, four ports (121) connected through bus wires (120-A, 120-B, 120-C, 120-D) to other routers and a fifth port (123) connecting each router to its associated IP block (104) through a network interface controller (108) and a memory communications controller (106).

In describing memory-address-based communications above, each memory address was described as mapped by network interface controllers to a network address, a network location of a memory communications controller. The network location of a memory communication controller (106) is naturally also the network location of that memory communication controller's associated router (110), network interface controller (108), and IP block (104). In inter-IP block, or network-address-based communications, therefore, it is also typical for application-level data processing to view network addresses as location of IP block within the network formed by the routers, links, and bus wires of the NOC. FIG. 2 illustrates that one organization of such a network is a mesh of rows and columns in which each network address can be implemented, for example, as either a unique identifier for each set of associated router, IP block, memory communications controller, and network interface controller of the mesh or x,y coordinates of each such set in the mesh.

In the NOC (102) of FIG. 3, each router (110) implements two or more virtual communications channels, where each virtual communications channel is characterized by a communication type. Communication instruction types, and therefore virtual channel types, include those mentioned above: inter-IP block network-address-based messages, request messages, responses to request messages, invalidate messages directed to caches; memory load and store messages; and responses to memory load messages, and so on. In support of virtual channels, each router (110) in the example of FIG. 3 also includes virtual channel control logic (132) and virtual channel buffers (134). The virtual channel control logic (132) examines each received packet for its assigned communications type and places each packet in an outgoing virtual channel buffer for that communications type for transmission through a port to a neighboring router on the NOC.

Each virtual channel buffer (134) has finite storage space. When many packets are received in a short period of time, a virtual channel buffer can fill up—so that no more packets can be put in the buffer. In other protocols, packets arriving on a virtual channel whose buffer is full would be dropped. Each virtual channel buffer (134) in this example, however, is enabled with control signals of the bus wires to advise surrounding routers through the virtual channel control logic to suspend transmission in a virtual channel, that is, suspend transmission of packets of a particular communications type. When one virtual channel is so suspended, all other virtual channels are unaffected—and can continue to operate at full capacity. The control signals are wired all the way back through each router to each router's associated network interface controller (108). Each network interface controller is configured to, upon receipt of such a signal, refuse to accept, from its associated memory communications controller (106) or from its associated IP block (104), communications instructions for the suspended virtual channel. In this way, suspension of a virtual channel affects all the hardware that implements the virtual channel, all the way back up to the originating IP blocks.

One effect of suspending packet transmissions in a virtual channel is that no packets are ever dropped in the architecture of FIG. 3. When a router encounters a situation in which a packet might be dropped in some unreliable protocol such as, for example, the Internet Protocol, the routers in the example of FIG. 3 suspend by their virtual channel buffers (134) and their virtual channel control logic (132) all transmissions of packets in a virtual channel until buffer space is again available, eliminating any need to drop packets. The NOC of FIG. 3, therefore, implements highly reliable network communications protocols with an extremely thin layer of hardware.

For further explanation, FIG. 4 sets forth a flow chart illustrating an exemplary method for data processing with a NOC according to embodiments of the present invention. The method of FIG. 4 is implemented on a NOC similar to the ones described above in this specification, a NOC (102 on FIG. 3) that is implemented on a chip (100 on FIG. 3) with IP blocks (104 on FIG. 3), routers (110 on FIG. 3), memory communications controllers (106 on FIG. 3), and network interface controllers (108 on FIG. 3). Each IP block (104 on FIG. 3) is adapted to a router (110 on FIG. 3) through a memory communications controller (106 on FIG. 3) and a network interface controller (108 on FIG. 3). In the method of FIG. 4, each IP block may be implemented as a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC.

The method of FIG. 4 includes controlling (402) by a memory communications controller (106 on FIG. 3) communications between an IP block and memory. In the method of FIG. 4, the memory communications controller includes a plurality of memory communications execution engines (140 on FIG. 3). Also in the method of FIG. 4, controlling (402) communications between an IP block and memory is carried out by executing (404) by each memory communications execution engine a complete memory communications instruction separately and in parallel with other memory communications execution engines and executing (406) a bidirectional flow of memory communications instructions between the network and the IP block. In the method of FIG. 4, memory communications instructions may include translation lookaside buffer control instructions, cache control instructions, barrier instructions, memory load instructions, and memory store instructions. In the method of FIG. 4, memory may include off-chip main RAM, memory connected directly to an IP block through a memory communications controller, on-chip memory enabled as an IP block, and on-chip caches.

The method of FIG. 4 also includes controlling (408) by a network interface controller (108 on FIG. 3) inter-IP block communications through routers. In the method of FIG. 4, controlling (408) inter-IP block communications also includes converting (410) by each network interface controller communications instructions from command format to network packet format and implementing (412) by each network interface controller virtual channels on the network, including characterizing network packets by type.

The method of FIG. 4 also includes transmitting (414) messages by each router (110 on FIG. 3) through two or more virtual communications channels, where each virtual communications channel is characterized by a communication type. Communication instruction types, and therefore virtual channel types, include, for example: inter-IP block network-address-based messages, request messages, responses to request messages, invalidate messages directed to caches; memory load and store messages; and responses to memory load messages, and so on. In support of virtual channels, each router also includes virtual channel control logic (132 on FIG. 3) and virtual channel buffers (134 on FIG. 3). The virtual channel control logic examines each received packet for its assigned communications type and places each packet in an outgoing virtual channel buffer for that communications type for transmission through a port to a neighboring router on the NOC.

On a NOC according to embodiments of the present invention, computer software applications may be implemented as software pipelines. For further explanation, FIG. 5 sets forth a data flow diagram illustrating operation of an example pipeline (600). The example pipeline (600) of FIG. 5 includes three stages (602, 604, 606) of execution. A software pipeline is a computer software application that is segmented into a set of modules or ‘stages’ of computer program instructions that cooperate with one another to carry out a series of data processing tasks in sequence. Each stage in a pipeline is composed of a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block on a NOC (102). The stages are ‘flexibly configurable’ in that each stage may support multiple instances of the stage, so that a pipeline may be scaled by instantiating additional instances of a stage as needed depending on workload.

Because each stage (602, 604, 606) is implemented by computer program instructions executing on an IP block (104 on FIG. 2) of a NOC (102 on FIG. 2), each stage (602, 604, 606) is capable of accessing addressed memory through a memory communications controller (106 on FIG. 2) of an IP block—with memory-addressed messages as described above. At least one stage, moreover, sends network-address based communications among other stages, where the network-address based communications maintain packet order. In the example of FIG. 5, both stage 1 and stage 2 send network-address based communications among stages, stage 1 sending network address based communications (622-626) from stage 1 to stage 2, stage 2 sending network addressed communications (628-632) to stage 3.

The network-address based communications (622-632) in the example of FIG. 5 maintain packet order. Network-address based communications among stages of a pipeline are all communications of a same type which therefore flow through the same virtual channel as described above. Each packet in such communications is routed by a router (110 on FIG. 3) according to embodiments of the present invention, entering and leaving a virtual channel buffer (134 on FIG. 3) in sequence, in FIFO order, first-in, first-out, thereby maintaining strict packet order. Maintaining packet order in network address based communications according to the present invention provides message integrity because the packets are received in the same order in which they are—eliminating the need for tracking packet sequence in a higher layer of the data communication protocol stack. Contrast the example of TCP/IP where the network protocol, that is, the Internet Protocol, not only makes no undertaking regarding packet sequence, but in fact normally does deliver packets out of order, leaving it up to the Transmission Control Protocol in a higher layer of the data communication protocol stack to put the packets in correct order and deliver a complete message to the application layer of the protocol stack.

Each stage implements a producer/consumer relationship with a next stage. Stage 1 receives work instructions and work piece data (620) through a host interface processor (105) from an application (184) running on a host computer (152). Stage 1 carries out its designated data processing tasks on the work piece, produces output data, and sends the produced output data (622, 624, 626) to stage 2, which consumes the produced output data from stage 1 by carrying out its designated data processing tasks on the produced output data from stage 1, thereby producing output data from stage 2, and sends its produced output data (628, 630, 632) to stage 3, which in turn consumes the produced output data from stage 2 by carrying out its designated data processing tasks on the produced output data from stage 2, thereby producing output data from stage 3, which then stores its produced output data (634, 636) in an output data structure (638) for eventual return through the host interface processor (105) to the originating application program (184) on the host computer (152).

The return to the originating application program is said to be ‘eventual’ because quite a lot of return data may need to be calculated before the output data structure (638) is ready to return. The pipeline (600) in this example is represented with only six instances (622-632) in three stages (602-606). Many pipelines according to embodiments of the present invention, however, may includes many stages and many instances of stages. In an atomic process modeling application, for example, the output data structure (638) may represent the state at a particular nanosecond of an atomic process containing the exact quantum state of billions of sub-atomic particles, each of which requires thousands of calculations in various stages of a pipeline. Or in a video processing application, for a further example, the output data structure (638) may represent a video frame composed of the current display state of thousands of pixels, each of which requires many calculations in various stages of a pipeline.

Each instance (622-632) of each stage (602-606) of the pipeline (600) is implemented as an application-level module of computer program instructions executed on a separate IP block (104 on FIG. 2) on a NOC (102 on FIG. 2). Each stage is assigned to a thread of execution on an IP block of a NOC. Each stage is assigned a stage ID, and each instance of a stage is assigned an identifier. The pipeline (600) is implemented in this example with one instance (608) of stage 1, three instances (610, 612, 614) of stage 2, and two instances (616, 618) of stage 3. Stage 1 (602, 608) is configured at start-up by the host interface processor (105) with the number of instances of stage 2 and the network location of each instance of stage 2. Stage 1 (602, 608) may distribute its resultant workload (622, 624, 626) by, for example, distributing it equally among the instances (610-614) of stage 2. Each instance (610-614) of stage 2 is configured at start up with the network location of each instance of stage 3 to which an instance of stage 2 is authorized to send its resultant workload. In this example, instances (610, 612) are both configured to send their resultant workloads (628, 630) to instance (616) of stage 3, whereas only one instance (614) of stage 2 sends work (632) to instance (618) of stage 3. If instance (616) becomes a bottleneck trying to do twice the workload of instance (618), an additional instance of stage 3 may be instantiated, even in real time at run time if needed.

In the example of FIG. 5, where a computer software application (500) is segmented into stages (602-606), each stage may be configured with a stage ID for each instance of a next stage. That a stage may be configured with a stage ID means that a stage is provided with an identifier for each instance of a next stage, with the identifier stored in memory available to the stage. Configuring with identifiers of instances of next stage can include configuring with the number of instances of a next states as well as the network location of each instance of a next stage, as mentioned above. The single instance (608) of stage 1, in the current example, may be configured with a stage identifier or ‘ID’ for each instance (610-614) of a next stage, where the ‘next stage’ for stage 1, of course, is stage 2. The three instances (610-614) of stage 2 each may be configured with a stage ID for each instance (616, 618) of a next stage, where the next stage for stage 2 naturally is stage 3. And so on, with stage 3 in this example representing the trivial case of a stage having no next stage, so that configuring such a stage with nothing represents configuring that stage with the stage ID of a next stage.

Configuring a stage with IDs for instances of a next stage as described here provides the stage with the information needed to carry out load balancing across stages. In the pipeline of FIG. 5, for example, where a computer software application (500) is segmented into stages, the stages are load balanced with a number of instances of each stage in dependence upon the performance of the stages. Such load balancing can be carried out, for example, by monitoring the performance of the stages and instantiating a number of instances of each stage in dependence upon the performance of one or more of the stages. Monitoring the performance of the stages can be carried out by configuring each stage to report performance statistics to a monitoring application (502) that in turn is installed and running on another thread of execution on an IP block or host interface processor. Performance statistics can include, for example, time required to complete a data processing task, a number of data processing tasks completed within a particular time period, and so on, as will occur to those of skill in the art.

Instantiating a number of instances of each stage in dependence upon the performance of one or more of the stages can be carried out by instantiating, by a host interface processor (105), a new instance of a stage when monitored performance indicates a need for a new instance. As mentioned, instances (610, 612) in this example are both configured to send their resultant workloads (628, 630) to instance (616) of stage 3, whereas only one instance (614) of stage 2 sends work (632) to instance (618) of stage 3. If instance (616) becomes a bottleneck trying to do twice the workload of instance (618), an additional instance of stage 3 may be instantiated, even in real time at run time if needed.

The NOC of FIG. 5 is capable of sharing memory in a software pipeline, that is, sharing memory among stages of a software pipeline. The example NOC (102) of FIG. 5 includes memory (702) allocated by at least one of the stages (602-606) to be shared among at least two stages. In this example, an instance of stage 1 (608) allocated the shared memory, and the shared memory is shared between stages 1 and 2 (602, 604).

The example NOC also includes a smart pointer (704), which in turn includes data elements (728, 730) for determining when the shared memory (702) can be deallocated. The smart pointer (704) is a ‘pointer’ in the sense that it is implemented as a structure that contains a pointer (722) to a segment of memory (702) that is shared among stages in a software pipeline. The memory pointer (722) may be implemented, for example, as an address of the beginning of the shared memory segment, the beginning address plus an extent or size of the shared memory segment, both a beginning address and an ending address, and so on, as will occur to those of skill in the art. The smart pointer (704) is ‘smart’ in that it is implemented as an instance of an object-oriented class that includes accessor functions (724, 726) for setting the values of the data elements (728, 730) for determining when the shared memory (702) can be deallocated. The accessor functions are named respectively SetInUse( ) (724) and SetNoLongerRequired( ) (726). Each accessor function takes a call parameter, “instanceID,” an identifier of an instance of a stage in a software pipeline. Each accessor function sets a value in a corresponding data element. SetInUse( ) (724) sets a value in an InUse (728) data element, and SetNoLongerRequired( ) (726) sets a value in a NoLongerRequired (730) data element. In many embodiments, more than one instance of a stage will have access to the same shared memory segment, so that a smart pointer will administer multiple sets of InUse and NoLongerRequired data elements for determining when the shared memory can be deallocated. Such embodiments can store multiple sets of InUse and NoLongerRequired data elements for determining when the shared memory can be deallocated in a table, for example. In such embodiments, the “instanceID” parameter may be used to specify which rows of the table contain InUse and NoLongerRequired data elements whose values are to be set by any particular call to an accessor function.

Just as a stage, or an instance of a stage, can allocate memory to be shared among stages, so also, in the example of FIG. 5, a stage can determine in dependence upon the data elements for determining when the shared memory can be deallocated that the shared memory can be deallocated, and such a stage, upon making the determination that shared memory can be deallocated, can deallocate the shared memory. In the example NOC of FIG. 5, the computer software application (500) segmented into stages (602-606) of a software pipeline (600) can include two or more stages authorized to change values of the data elements for determining when the shared memory can be deallocated. In this example, stages 1 and 2 are so authorized, because only instances of stages 1 and 2 are sharing the shared memory segment (702).

In the example NOC of FIG. 5, the computer software application (500) segmented into stages (602-606) of a software pipeline (600) can include a stage authorized to determine that the memory (702) can be deallocated. In this example, it is assumed that stage 1 (602) allocated the shared memory segment (702) and that stage 1 is authorized to determine that the shared memory can be deallocated.

A software pipeline typically includes one or more paths of execution. In the example of FIG. 5, the software pipeline includes three paths of execution among the stages of the pipeline. Represented as sequences of instances of the stage, the paths of execution in the software pipeline in the example of FIG. 5 are:

    • 608-610-616
    • 608-612-616
    • 608-614-618

For ease of explanation, the example pipeline (600) here is represented with only three paths of execution among its stages. Readers will recognize, however, that many NOCs that share memory in a software pipeline according to embodiments of the present invention will implement many more stages, many instances of stages, and many paths of execution among the stages.

The data elements (728, 730) for determining when the shared memory can be deallocated can be implemented as a table that includes at least one row for each path of execution in the pipeline. Such a table can include, as data elements for determining when the shared memory can be deallocated, a column indicating that a segment of the shared memory is in use by a stage in a path of the pipeline and another column indicating that the segment of shared memory is no longer required for use by the stage in a path of execution in the pipeline. An example of such a table is set forth here as Table 1, and subsequent examples of the same table are set forth below as Tables 1a and 1b:

TABLE 1
Data Elements For Determining When
A Particular Segment Of Shared
Memory Can Be Deallocated
No Longer
In Use Required
Path Instance (728) (730)
608-610-616 608 0 0
608-610-616 610 0 0
608-610-616 616 0 0
608-612-616 608 0 0
608-612-616 612 0 0
608-612-616 616 0 0
608-614-618 608 0 0
608-614-618 614 0 0
608-614-618 618 0 0

Table 1 includes three rows for each path of execution in the software pipeline of FIG. 5, one row for each instance of a stage in each path of execution. Table 1 includes a column entitled “In Use” (728) capable of indicating that a segment of the shared memory is in use by a stage in a path of the pipeline and another column entitled “No Longer Required” (730) capable of indicating that the segment of shared memory is no longer required for use by the stage in a path of execution in the pipeline. So providing separate In Use and No Longer Required fields for each instance of a stage that shares a memory segment means that each call to an accessor function from an instance of a stage of a software pipeline affects only a single, separate data element, thereby eliminating race conditions and either reducing or eliminating completely any need for mutual exclusion, memory locks, semaphores, and the like, to control access to data elements used for determining that shared memory can be deallocated.

In a NOC according to embodiments of the present invention, one of the stages of pipeline typically is designated as responsible for determining, in dependence upon data values in the columns of the table, that the memory can be deallocated. In the example NOC of FIG. 5, stage 1 (602), instance (608), in the software pipeline (600) is considered to be designated as responsible for determining that the shared memory segment can be deallocated. A preferred method of making such a determination is for the accessor functions (724, 726) to set the same value in both columns of the table representing data elements (728, 730) for determining when the shared memory can be deallocated. In this way, a stage that is designated responsible for determining that the memory can be deallocated can make that determination when the data values in the data elements for determining when the shared memory can be deallocated in each row of the table are equal.

It would make no difference whether the data values are numerical or Boolean as long as the operations on each column are symmetric. The values being equal in each row will demonstrate that the shared memory can be deallocated. Consider for further explanation, an example in which the accessor functions use the numeric values 0 and 1 to indicate whether a stage or an instance of a stage is using or no longer requires use of a shared memory segment. In such an example, the In Use and the No Longer Required columns can be initialized entirely to 0 when a smart pointer for a particular segment of shared memory is first instantiated. Table 1 shows an example of an initial state of values in data elements (728, 730) of a smart pointer for the memory (702) shared among stages of the software pipeline in the example of FIG. 5. That values of In Use (728) and No Longer Required (730) are the same in all rows of Table 1, indicating to a responsible or authorized stage that the shared memory segment administered by these data elements can be deallocated. If the segment were deallocated now, before any of the stages authorized to share it indicated usage, such a deallocation can be indicated in a member variable established for that purpose and named, for example, “Allocated” (723). Then the accessor function SetInUse( ) can be programmed to check the value of the Allocated (723) variable and, if the value of Allocated indicates deallocation, return an error code to any calling instance of a stage attempting to register an indication of usage.

Instances of stages indicate their current use of the shared memory by calling SetInUse(instanceID), thereby setting the value 1 in a row of the table corresponding to the calling instance. Table 1a show the state of such a table after a number of calls to the SetInUse(instanceID) accessor function.

TABLE 1a
Data Elements For Determining When
A Particular Segment Of Shared
Memory Can Be Deallocated
No Longer
In Use Required
Path Instance (728) (730)
608-610-616 608 1 0
608-610-616 610 0 0
608-610-616 616 0 0
608-612-616 608 1 0
608-612-616 612 0 0
608-612-616 616 0 0
608-614-618 608 1 0
608-614-618 614 1 0
608-614-618 618 0 0

In Table 1a, the values of In Use (728) have been set to 1 for instances (608) and (614), indicating that the shared memory segment is in use by instances of stages 1 and 2 in the pipeline of FIG. 5. Now the values of In Use (728) and No Longer Required (730) in four rows of the table are no longer equal. The values of In Use (728) are 1 for instances (608) and (614) and the corresponding values of No Longer Required (730) in the same rows are still set to 0. That the values of In Use (728) and No Longer Required (730) are not the same in all rows of Table 1a indicates to a responsible or authorized stage that the shared memory segment administered by these data elements can not be deallocated at this time—because the shared memory segment (702) administered by use of the data elements in Table 1a is in use and continues to be required by one or more instances (608, 614) of stages (602, 604) in at least one path of execution (608-614-618) in the software pipeline (600) of FIG. 5.

Instances of stages may indicate that use of a segment of shared memory is no long required by calling SetNoLongerRequired (instanceID), thereby setting the value 1 in a row of the table corresponding to the calling instance. Table 1b show the state of such a table after a number of calls to the SetNoLongerRequired (instanceID) accessor function.

TABLE 1b
Data Elements For Determining When
A Particular Segment Of Shared
Memory Can Be Deallocated
No Longer
In Use Required
Path Instance (728) (730)
608-610-616 608 1 1
608-610-616 610 0 0
608-610-616 616 0 0
608-612-616 608 1 1
608-612-616 612 0 0
608-612-616 616 0 0
608-614-618 608 1 1
608-614-618 614 1 1
608-614-618 618 0 0

In Table 1a, the values of No Longer Required (730) have been set to 1 for instances (608) and (614), indicating that the shared memory segment administered by use of data elements in Table 1b is no longer required by instances of stages 1 and 2 in the software pipeline of FIG. 5. Now the values of In Use (728) and No Longer Required (730) in four rows of the table, previously unequal in Table 1a, are now equal. The values of In Use (728) are 1 for instances (608) and (614) and the corresponding values of No Longer Required (730) in the same rows are also now set to 1. Now all values of In Use (728) and No Longer Required (730) are the same in all rows of Table 1a, indicating to a responsible or authorized stage that the shared memory segment administered by the data elements of Table 1b can be deallocated at this time—because the shared memory segment (702) administered by use of the data elements in Table 1a is either not in use or, to the extent that it was in use, no longer required by any instance of stages in any path of execution in the software pipeline (600) of FIG. 5.

For further explanation, FIG. 6 sets forth a flow chart illustrating an exemplary method of software pipelining on a NOC according to embodiments of the present invention. The method of FIG. 6 is implemented on a NOC similar to the ones described above in this specification, a NOC (102 on FIG. 2) that is implemented on a chip (100 on FIG. 2) with IP blocks (104 on FIG. 2), routers (110 on FIG. 2), memory communications controllers (106 on FIG. 2), and network interface controllers (108 on FIG. 2). Each IP block (104 on FIG. 2) is adapted to a router (110 on FIG. 2) through a memory communications controller (106 on FIG. 2) and a network interface controller (108 on FIG. 2). In the method of FIG. 6, each IP block is implemented as a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC.

The method of FIG. 6 includes segmenting (702) a computer software application into stages, where each stage is implemented as a flexibly configurable module of computer program instructions identified by a stage ID. In the method of FIG. 6, segmenting (702) a computer software application into stages may be carried out by configuring (706) each stage with a stage ID for each instance of a next stage. The method of FIG. 6 also includes executing (704) each stage on a thread of execution on an IP block.

In the method of FIG. 6, segmenting (702) a computer software application into stages also may include assigning (708) each stage to a thread of execution on an IP block, assigning each stage a stage ID. In such an embodiment, executing (704) each stage on a thread of execution on an IP block may include: executing (710) a first stage, producing output data; sending (712) by the first stage the produced output data to a second stage; and consuming (714) the produced output data by the second stage.

In the method of FIG. 6, segmenting (702) a computer software application into stages also may include load balancing (716) the stages, carried out by monitoring (718) the performance of the stages and instantiating (720) a number of instances of each stage in dependence upon the performance of one or more of the stages.

For further explanation, FIG. 7 sets forth a flow chart illustrating an exemplary method of sharing memory in a software pipeline according to embodiments of the present invention. The method of FIG. 7 is implemented on a NOC similar to the ones described above in this specification, a NOC (102 on FIG. 2) that is implemented on a chip (100 on FIG. 2) with IP blocks (104 on FIG. 2), routers (110 on FIG. 2), memory communications controllers (106 on FIG. 2), and network interface controllers (108 on FIG. 2). Each IP block (104 on FIG. 2) is adapted to a router (110 on FIG. 2) through a memory communications controller (106 on FIG. 2) and a network interface controller (108 on FIG. 2). In the method of FIG. 7, each IP block is implemented as a reusable unit of synchronous or asynchronous logic design used as a building block for data processing within the NOC.

The method of FIG. 7 includes segmenting (802) a computer software application into stages (602-606) of a software pipeline (600). As mentioned above, a software pipeline is a computer software application that is segmented into a set of modules or ‘stages’ of computer program instructions that cooperate with one another to carry out a series of data processing tasks in sequence. Each stage in a pipeline is composed of a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block on a NOC (102). The stages are ‘flexibly configurable’ in that each stage may support multiple instances of the stage, so that a pipeline may be scaled by instantiating additional instances of a stage as needed depending on workload. Such a software pipeline typically includes one or more paths of execution among instances of the stages, and each stage is implemented as a flexibly configurable module of computer program instructions identified by a stage ID. Each stage executes in a thread of execution on an IP block of the NOC.

The method of FIG. 7 also includes allocating (804), by at least one of the stages, memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated. In the method of FIG. 7, data elements for determining when the shared memory can be deallocated can be implemented in a table that includes at least one row for each path of execution in the pipeline—such as, for example, the tables described above as Tables 1, 1a, and 1b. The table can include a column indicating that a segment of the shared memory is in use by a stage in a path of execution in the pipeline and a column indicating that a segment of the shared memory is no longer required for use by a stage in the path of execution in the pipeline. Taking as an example the smart pointer (704) of FIG. 5, a stage that is designated as responsible or authorized to do so can allocate memory to be shared among stages by instantiating a smart pointer object of a smart pointer class having a structure similar to the one illustrated at reference (704) on FIG. 5. Such an authorized or designated stage can then configure the smart pointer object with a memory pointer (722) identifying a segment of memory to be shared among stages and provide to each stage, or instance of a stage, that is to share the memory segment a reference to the smart pointer object.

The method of FIG. 7 also includes determining (806), by at least one stage in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated. In the method of FIG. 7, segmenting (802) a computer software application into stages of a software pipeline may include authorizing (810) two or more stages to change values of data elements for determining when shared memory can be deallocated. Continuing to use the smart pointer (704) of FIG. 5 as an example: stages of a software pipeline can change values of data elements (728, 730) for determining when shared memory can be deallocated by calling accessor functions (724, 726) that set the values of data elements (728, 730) for determining when shared memory can be deallocated in a smart pointer (704) implemented as an object-oriented instance of a smart pointer class.

In the method of FIG. 7, segmenting (802) a computer software application into stages of a software pipeline may include authorizing (812) at least one stage to determine that the shared memory can be deallocated, and determining (804) that the shared memory can be deallocated may include determining (814), by the at least one authorized stage, that the shared memory can be deallocated. Also in the method of FIG. 7, determining (806), by at least one stage in dependence upon the data elements, that the shared memory can be deallocated may include determining (816), by a designated stage in dependence upon data values in the columns of the table, that the shared memory can be deallocated. In the method of FIG. 7, determining (806), by at least one stage in dependence upon the data elements, that the shared memory can be deallocated alternatively may include determining (818), by a designated stage, that the data values in the data elements for determining when the shared memory can be deallocated in each row of the table are equal.

As described above with reference to Tables 1, 1a, and 1b, in an embodiment that uses the same initial data values and the same values to indicate ‘in use’ and ‘no longer required,’ the fact that each row contains the same value in both its ‘in use’ and ‘no longer required’ fields can be taken to mean that a shared memory segment is eligible for deallocation. The requirement in such an embodiment is that the corresponding values in each row are the same. In such an embodiment, however, there is no requirement that all values in all such fields across rows be the same. Table 1b illustrates this fact. Looking down the In Use (728) and the No Longer Required (730) columns, the values of the fields vary across rows. Both the In Use and the No Longer Required values within any single row, however, are all equal in Table 1b. All four sets of In Use and No Longer Required values for instances (608, 614) are set to 1. All remaining two-sets of In Use and No Longer Required are set to 0. Table 1b therefore depicts data elements for determining when shared memory can be deallocated indicating that the share memory controlled by these data elements is in a condition to be deallocated.

The method of FIG. 7 also includes deallocating (808) the shared memory. Continuing with the smart pointer (704) of FIG. 5 as an example: stages of a software pipeline can deallocate shared memory by resetting a member variable established for that purpose in the smart pointer (704) and named, for example, “Allocated” (723). In an embodiments where allocating shared memory is carried out by providing to each sharing stage, or to each sharing instance of a stage, a reference to a smart pointer object, so resetting a Boolean Allocate variable to FALSE, for example, effectively and immediately deallocates the share memory across all sharing instances of stages. Any stage or instance of a stage still in possession of such a reference to a smart pointer object attempting to register shared memory as In Use (728) by calling an accessor function such as SetInUse( ) (724) would find the SetInUse( ) programmed to check the value of the Allocated (723) variable and, if the value of Allocated indicates deallocation, return an error code or throw an exception.

Exemplary embodiments of the present invention are described largely in the context of a fully functional computer system for software pipelining on a NOC. Readers of skill in the art will recognize, however, that the present invention also may be embodied in a computer program product disposed on computer readable media for use with any suitable data processing system. Such computer readable media may be transmission media or recordable media for machine-readable information, including magnetic media, optical media, or other suitable media. Examples of recordable media include magnetic disks in hard drives or diskettes, compact disks for optical drives, magnetic tape, and others as will occur to those of skill in the art. Examples of transmission media include telephone networks for voice communications and digital data communications networks such as, for example, Ethernets™ and networks that communicate with the Internet Protocol and the World Wide Web as well as wireless transmission media such as, for example, networks implemented according to the IEEE 802.11 family of specifications. Persons skilled in the art will immediately recognize that any computer system having suitable programming means will be capable of executing the steps of the method of the invention as embodied in a program product. Persons skilled in the art will recognize immediately that, although some of the exemplary embodiments described in this specification are oriented to software installed and executing on computer hardware, nevertheless, alternative embodiments implemented as firmware or as hardware are well within the scope of the present invention.

It will be understood from the foregoing description that modifications and changes may be made in various embodiments of the present invention without departing from its true spirit. The descriptions in this specification are for purposes of illustration only and are not to be construed in a limiting sense. The scope of the present invention is limited only by the language of the following claims.

Claims (15)

1. A method of sharing memory in a software pipeline, the method implemented on a network on chip (‘NOC’), the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block operatively coupled to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the method comprising:
segmenting a computer software application into stages of a software pipeline, the software pipeline comprising one or more paths of execution, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID, each stage executing in a thread of execution on an IP block; and
allocating, by at least one of the stages, memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated, wherein data elements for determining when the shared memory can be deallocated further comprise a table comprising at least one row for each path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is in use by a stage in a path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is no longer required for use by a stage in the path of execution in the pipeline;
determining, by at least one stage in dependence upon the data elements for determining when the shared memory can be deallocated, that the shared memory can be deallocated; and
deallocating the shared memory.
2. The method of claim 1 wherein segmenting a computer software application into stages of a software pipeline further comprises authorizing two or more stages to change values of the data elements for determining when the shared memory can be deallocated.
3. The method of claim 1 wherein:
segmenting a computer software application into stages of a software pipeline further comprises authorizing at least one stage to determine that the shared memory can be deallocated; and
determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by the at least one authorized stage, that the shared memory can be deallocated.
4. The method of claim 1 wherein determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by a designated stage in dependence upon data values in the columns of the table, that the shared memory can be deallocated.
5. The method of claim 1 wherein determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by a designated stage, that data values in the data elements for determining when the shared memory can be deallocated in each row of the table are equal.
6. A network on chip (‘NOC’) for sharing memory in a software pipeline, the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block operatively coupled to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the NOC further comprising:
a computer software application segmented into stages as the software pipeline, the software pipeline comprising one or more paths of execution, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID and executing on a thread of execution on an IP block; and
memory allocated by at least one of the stages to be shared among at least two stages, including a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated, wherein data elements for determining when the shared memory can be deallocated further comprise a table comprising at least one row for each path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is in use by a stage in a path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is no longer required for use by a stage in the path of execution in the pipeline.
7. The NOC of claim 6 wherein the computer software application segmented into stages of a software pipeline further comprises two or more stages authorized to change values of the data elements for determining when the shared memory can be deallocated.
8. The NOC of claim 6 wherein:
the computer software application segmented into stages of a software pipeline further comprises at least one stage authorized to determine that the shared memory can be deallocated.
9. The NOC of claim 6 wherein one of the stages is designated responsible for determining, in dependence upon data values in the columns of the table, that the shared memory can be deallocated.
10. The NOC of claim 6 wherein one of the stages is designated responsible for determining, when data values in the data elements for determining when the shared memory can be deallocated in each row of the table are equal, that the shared memory can be deallocated.
11. A computer program product for sharing memory in a software pipeline on a network on chip (‘NOC’), the NOC comprising integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, each IP block operatively coupled to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, the computer program product including computer program instructions disposed in a recordable computer readable medium, the computer program instructions capable of:
segmenting a computer software application into stages of a software pipeline, the pipeline comprising one or more paths of execution, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID; and
allocating, by at least one of the stages, memory to be shared among at least two stages including creating a smart pointer, the smart pointer including data elements for determining when the shared memory can be deallocated, wherein the data elements for determining when the shared memory can be deallocated further comprise a table comprising at least one row for each path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is in use by a stage in a path of execution in the pipeline, the table further comprising a column indicating that a segment of the shared memory is no longer required for use by a stage in the path of execution in the pipeline;
executing each stage on a thread of execution on an IP block;
determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated; and
deallocating the shared memory.
12. The computer program product of claim 11 wherein segmenting a computer software application into stages of a software pipeline further comprises authorizing two or more stages to change values of the data elements for determining when the shared memory can be deallocated.
13. The computer program product of claim 11 wherein:
segmenting a computer software application into stages of a software pipeline further comprises authorizing at least one stage to determine that the shared memory can be deallocated; and
determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by the at least one authorized stage, that the shared memory can be deallocated.
14. The computer program product of claim 11 wherein determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by a designated stage in dependence upon data values in the columns of the table, that the shared memory can be deallocated.
15. The computer program product of claim 11 wherein determining, by at least one stage in dependence upon the data elements, that the shared memory can be deallocated further comprises determining, by a designated stage, that data values in the data elements for determining when the shared memory can be deallocated in each row of the table are equal.
US11938376 2007-11-12 2007-11-12 Software pipelining on a network on chip Expired - Fee Related US8261025B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US11938376 US8261025B2 (en) 2007-11-12 2007-11-12 Software pipelining on a network on chip

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11938376 US8261025B2 (en) 2007-11-12 2007-11-12 Software pipelining on a network on chip
US13453380 US8898396B2 (en) 2007-11-12 2012-04-23 Software pipelining on a network on chip

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US13453380 Continuation US8898396B2 (en) 2007-11-12 2012-04-23 Software pipelining on a network on chip

Publications (2)

Publication Number Publication Date
US20090125574A1 true US20090125574A1 (en) 2009-05-14
US8261025B2 true US8261025B2 (en) 2012-09-04

Family

ID=40624768

Family Applications (2)

Application Number Title Priority Date Filing Date
US11938376 Expired - Fee Related US8261025B2 (en) 2007-11-12 2007-11-12 Software pipelining on a network on chip
US13453380 Active 2027-12-27 US8898396B2 (en) 2007-11-12 2012-04-23 Software pipelining on a network on chip

Family Applications After (1)

Application Number Title Priority Date Filing Date
US13453380 Active 2027-12-27 US8898396B2 (en) 2007-11-12 2012-04-23 Software pipelining on a network on chip

Country Status (1)

Country Link
US (2) US8261025B2 (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20150178435A1 (en) * 2013-12-19 2015-06-25 Netspeed Systems Automatic pipelining of noc channels to meet timing and/or performance
US9444702B1 (en) 2015-02-06 2016-09-13 Netspeed Systems System and method for visualization of NoC performance based on simulation output
US9568970B1 (en) 2015-02-12 2017-02-14 Netspeed Systems, Inc. Hardware and software enabled implementation of power profile management instructions in system on chip
US9590813B1 (en) 2013-08-07 2017-03-07 Netspeed Systems Supporting multicast in NoC interconnect
US9742630B2 (en) 2014-09-22 2017-08-22 Netspeed Systems Configurable router for a network on chip (NoC)
US9769077B2 (en) 2014-02-20 2017-09-19 Netspeed Systems QoS in a system with end-to-end flow control and QoS aware buffer allocation
US9825809B2 (en) 2015-05-29 2017-11-21 Netspeed Systems Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
US9825887B2 (en) 2015-02-03 2017-11-21 Netspeed Systems Automatic buffer sizing for optimal network-on-chip design
US9864728B2 (en) 2015-05-29 2018-01-09 Netspeed Systems, Inc. Automatic generation of physically aware aggregation/distribution networks
US9928204B2 (en) 2015-02-12 2018-03-27 Netspeed Systems, Inc. Transaction expansion for NoC simulation and NoC design

Families Citing this family (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090109996A1 (en) * 2007-10-29 2009-04-30 Hoover Russell D Network on Chip
EP2217701B9 (en) 2007-10-30 2015-02-18 Indiana University Research and Technology Corporation Glucagon antagonists
US20090125706A1 (en) * 2007-11-08 2009-05-14 Hoover Russell D Software Pipelining on a Network on Chip
US20090125703A1 (en) * 2007-11-09 2009-05-14 Mejdrich Eric O Context Switching on a Network On Chip
US8261025B2 (en) 2007-11-12 2012-09-04 International Business Machines Corporation Software pipelining on a network on chip
US8526422B2 (en) * 2007-11-27 2013-09-03 International Business Machines Corporation Network on chip with partitions
US7873701B2 (en) * 2007-11-27 2011-01-18 International Business Machines Corporation Network on chip with partitions
US8473667B2 (en) * 2008-01-11 2013-06-25 International Business Machines Corporation Network on chip that maintains cache coherency with invalidation messages
US8490110B2 (en) * 2008-02-15 2013-07-16 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US20090260013A1 (en) * 2008-04-14 2009-10-15 International Business Machines Corporation Computer Processors With Plural, Pipelined Hardware Threads Of Execution
US8423715B2 (en) * 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
US8020168B2 (en) * 2008-05-09 2011-09-13 International Business Machines Corporation Dynamic virtual software pipelining on a network on chip
US8494833B2 (en) * 2008-05-09 2013-07-23 International Business Machines Corporation Emulating a computer run time environment
US8392664B2 (en) * 2008-05-09 2013-03-05 International Business Machines Corporation Network on chip
US8214845B2 (en) * 2008-05-09 2012-07-03 International Business Machines Corporation Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data
US20090282419A1 (en) * 2008-05-09 2009-11-12 International Business Machines Corporation Ordered And Unordered Network-Addressed Message Control With Embedded DMA Commands For A Network On Chip
US20090282211A1 (en) * 2008-05-09 2009-11-12 International Business Machines Network On Chip With Partitions
US8230179B2 (en) * 2008-05-15 2012-07-24 International Business Machines Corporation Administering non-cacheable memory load instructions
US8438578B2 (en) * 2008-06-09 2013-05-07 International Business Machines Corporation Network on chip with an I/O accelerator
US8195884B2 (en) 2008-09-18 2012-06-05 International Business Machines Corporation Network on chip with caching restrictions for pages of computer memory
US8661455B2 (en) * 2009-04-21 2014-02-25 International Business Machines Corporation Performance event triggering through direct interthread communication on a network on chip
US8495643B2 (en) * 2009-06-30 2013-07-23 International Business Machines Corporation Message selection based on time stamp and priority in a multithreaded processor
US20110289485A1 (en) * 2010-05-21 2011-11-24 International Business Machines Corporation Software Trace Collection and Analysis Utilizing Direct Interthread Communication On A Network On Chip
US8629867B2 (en) 2010-06-04 2014-01-14 International Business Machines Corporation Performing vector multiplication
US8692825B2 (en) 2010-06-24 2014-04-08 International Business Machines Corporation Parallelized streaming accelerated data structure generation
US9253248B2 (en) * 2010-11-15 2016-02-02 Interactic Holdings, Llc Parallel information system utilizing flow control and virtual channels
US20120191896A1 (en) * 2011-01-25 2012-07-26 Zhen Fang Circuitry to select, at least in part, at least one memory
CN102158403B (en) * 2011-03-24 2014-03-05 山东大学 Efficient data stream transmission communication structure suitable for on chip network and operating method thereof
CN102523169A (en) * 2011-12-31 2012-06-27 南京大学 Parallelization method based on 2D-Mesh multi-core network architecture
KR101697038B1 (en) * 2013-05-30 2017-01-16 인텔 코포레이션 Dynamic optimization of software pipelining
US9781043B2 (en) * 2013-07-15 2017-10-03 Netspeed Systems Identification of internal dependencies within system components for evaluating potential protocol level deadlocks
US9348602B1 (en) 2013-09-03 2016-05-24 Amazon Technologies, Inc. Resource allocation for staged execution pipelining
CN103593485B (en) * 2013-12-04 2017-06-16 网易传媒科技(北京)有限公司 To achieve real-time database operation method and apparatus

Citations (130)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4813037A (en) 1986-01-24 1989-03-14 Alcatel Nv Switching system
US4951195A (en) 1988-02-01 1990-08-21 International Business Machines Corporation Condition code graph analysis for simulating a CPU processor
US5167023A (en) 1988-02-01 1992-11-24 International Business Machines Translating a dynamic transfer control instruction address in a simulated CPU processor
US5301302A (en) 1988-02-01 1994-04-05 International Business Machines Corporation Memory mapping and special write detection in a system and method for simulating a CPU processor
US5442797A (en) 1991-12-04 1995-08-15 Casavant; Thomas L. Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
US5590308A (en) 1993-09-01 1996-12-31 International Business Machines Corporation Method and apparatus for reducing false invalidations in distributed systems
US5761516A (en) 1996-05-03 1998-06-02 Lsi Logic Corporation Single chip multiprocessor architecture with internal task switching synchronization bus
US5784706A (en) 1993-12-13 1998-07-21 Cray Research, Inc. Virtual to logical to physical address translation for distributed memory massively parallel processing systems
US5870479A (en) 1993-10-25 1999-02-09 Koninklijke Ptt Nederland N.V. Device for processing data packets
US5872963A (en) 1997-02-18 1999-02-16 Silicon Graphics, Inc. Resumption of preempted non-privileged threads with no kernel intervention
US5884060A (en) 1991-05-15 1999-03-16 Ross Technology, Inc. Processor which performs dynamic instruction scheduling at time of execution within a single clock cycle
US5887166A (en) 1996-12-16 1999-03-23 International Business Machines Corporation Method and system for constructing a program including a navigation instruction
US5974487A (en) 1997-07-14 1999-10-26 Advanced Micro Devices, Inc. Data transfer network on a chip utilizing a mesh of rings topology
US6021470A (en) 1997-03-17 2000-02-01 Oracle Corporation Method and apparatus for selective data caching implemented with noncacheable and cacheable data for improved cache performance in a computer networking system
US6044478A (en) 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
US6047122A (en) 1992-05-07 2000-04-04 Tm Patents, L.P. System for method for performing a context switch operation in a massively parallel computer system
US6049866A (en) 1996-09-06 2000-04-11 Silicon Graphics, Inc. Method and system for an efficient user mode cache manipulation using a simulated instruction
US6085296A (en) * 1997-11-12 2000-07-04 Digital Equipment Corporation Sharing memory pages and page tables among computer processes
US6085315A (en) 1997-09-12 2000-07-04 Siemens Aktiengesellschaft Data processing device with loop pipeline
US6101599A (en) 1998-06-29 2000-08-08 Cisco Technology, Inc. System for context switching between processing elements in a pipeline of processing elements
US6105119A (en) * 1997-04-04 2000-08-15 Texas Instruments Incorporated Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems
US6119215A (en) 1998-06-29 2000-09-12 Cisco Technology, Inc. Synchronization and control system for an arrayed processing engine
US6145072A (en) 1993-08-12 2000-11-07 Hughes Electronics Corporation Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same
US6151668A (en) 1997-11-07 2000-11-21 Billions Of Operations Per Second, Inc. Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication
US6164841A (en) 1998-05-04 2000-12-26 Hewlett-Packard Company Method, apparatus, and product for dynamic software code translation system
US6272598B1 (en) 1999-03-22 2001-08-07 Hewlett-Packard Company Web cache performance by applying different replacement policies to the web cache
US6292888B1 (en) 1999-01-27 2001-09-18 Clearwater Networks, Inc. Register transfer unit for electronic processor
US6370622B1 (en) 1998-11-20 2002-04-09 Massachusetts Institute Of Technology Method and apparatus for curious and column caching
US20020099833A1 (en) 2001-01-24 2002-07-25 Steely Simon C. Cache coherency mechanism using arbitration masks
US6434669B1 (en) 1999-09-07 2002-08-13 International Business Machines Corporation Method of cache management to dynamically update information-type dependent cache policies
US6446171B1 (en) 2000-03-02 2002-09-03 Mips Technologies, Inc. Method and apparatus for tracking and update of LRU algorithm using vectors
US20020178337A1 (en) 2001-05-23 2002-11-28 Wilson Kenneth Mark Method and system for creating secure address space using hardware memory router
US6493817B1 (en) 1999-05-21 2002-12-10 Hewlett-Packard Company Floating-point unit which utilizes standard MAC units for performing SIMD operations
US6519605B1 (en) 1999-04-27 2003-02-11 International Business Machines Corporation Run-time translation of legacy emulator high level language application programming interface (EHLLAPI) calls to object-based calls
US20030065890A1 (en) 1999-12-17 2003-04-03 Lyon Terry L. Method and apparatus for updating and invalidating store data
US6567895B2 (en) 2000-05-31 2003-05-20 Texas Instruments Incorporated Loop cache memory and cache controller for pipelined microprocessors
US6591347B2 (en) 1998-10-09 2003-07-08 National Semiconductor Corporation Dynamic replacement technique in a shared cache
US6625662B1 (en) 1995-10-04 2003-09-23 Kawasaki Microelectronics, Inc. Inter-network connecting device
US6668307B1 (en) 2000-09-29 2003-12-23 Sun Microsystems, Inc. System and method for a software controlled cache
US6668308B2 (en) 2000-06-10 2003-12-23 Hewlett-Packard Development Company, L.P. Scalable architecture based on single-chip multiprocessing
US6675284B1 (en) 1998-08-21 2004-01-06 Stmicroelectronics Limited Integrated circuit with multiple processing cores
US6697932B1 (en) 1999-12-30 2004-02-24 Intel Corporation System and method for early resolution of low confidence branches and safe data cache accesses
US20040037313A1 (en) 2002-05-15 2004-02-26 Manu Gulati Packet data service over hyper transport link(s)
US6725317B1 (en) 2000-04-29 2004-04-20 Hewlett-Packard Development Company, L.P. System and method for managing a computer system having a plurality of partitions
US20040083341A1 (en) 2002-10-24 2004-04-29 Robinson John T. Weighted cache line replacement
US20040151197A1 (en) 2002-10-21 2004-08-05 Hui Ronald Chi-Chun Priority queue architecture for supporting per flow queuing and multiple ports
US20040153579A1 (en) 2003-01-30 2004-08-05 Ching-Chih Shih Virtual disc drive control device
US20040216105A1 (en) 2003-04-24 2004-10-28 International Business Machines Corporation Method for resource balancing using dispatch flush in a simultaneous multithread processor
US6823429B1 (en) 1997-07-10 2004-11-23 International Business Machines Corporation Memory controller for controlling memory accesses across networks in distributed shared memory processing systems
US20040250046A1 (en) 2003-03-31 2004-12-09 Gonzalez Ricardo E. Systems and methods for software extensible multi-processing
US6832184B1 (en) 2000-03-02 2004-12-14 International Business Machines Corporation Intelligent work station simulation—generalized LAN frame generation simulation structure
US20040260906A1 (en) 2003-04-04 2004-12-23 Sun Microsystems, Inc. Performing virtual to global address translation in processing subsystem
US20050044319A1 (en) 2003-08-19 2005-02-24 Sun Microsystems, Inc. Multi-core multi-thread processor
CN1599471A (en) 2003-09-17 2005-03-23 华为技术有限公司 Realization method and device for controlling load balance in communication system
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
US20050086435A1 (en) 2003-09-09 2005-04-21 Seiko Epson Corporation Cache memory controlling apparatus, information processing apparatus and method for control of cache memory
US20050097184A1 (en) 2003-10-31 2005-05-05 Brown David A. Internal memory controller providing configurable access of processor clients to memory instances
US6891828B2 (en) 2001-03-12 2005-05-10 Network Excellence For Enterprises Corp. Dual-loop bus-based network switch using distance-value or bit-mask
US6898791B1 (en) 1998-04-21 2005-05-24 California Institute Of Technology Infospheres distributed object system
US20050149689A1 (en) 2003-12-30 2005-07-07 Intel Corporation Method and apparatus for rescheduling operations in a processor
US20050160209A1 (en) 2004-01-20 2005-07-21 Van Doren Stephen R. System and method for resolving transactions in a cache coherency protocol
US20050166205A1 (en) 2004-01-22 2005-07-28 University Of Washington Wavescalar architecture having a wave order memory
US6938253B2 (en) 2001-05-02 2005-08-30 Portalplayer, Inc. Multiprocessor communication system and method
US20050198442A1 (en) 2004-03-02 2005-09-08 Mandler Alberto R. Conditionally accessible cache memory
US20050203988A1 (en) 2003-06-02 2005-09-15 Vincent Nollet Heterogeneous multiprocessor network on chip devices, methods and operating systems for control thereof
US6950438B1 (en) 1999-09-17 2005-09-27 Advanced Micro Devices, Inc. System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system
US20050238035A1 (en) 2004-04-27 2005-10-27 Hewlett-Packard System and method for remote direct memory access over a network switch fabric
US6973032B1 (en) 2000-12-04 2005-12-06 Cisco Technology, Inc. Selective backpressure control for multistage switches
US6988149B2 (en) 2002-02-26 2006-01-17 Lsi Logic Corporation Integrated target masking
US7010580B1 (en) 1999-10-08 2006-03-07 Agile Software Corp. Method and apparatus for exchanging data in a platform independent manner
US7015909B1 (en) 2002-03-19 2006-03-21 Aechelon Technology, Inc. Efficient use of user-defined shaders to implement graphics operations
US20060095920A1 (en) 2002-10-08 2006-05-04 Koninklijke Philips Electronics N.V. Integrated circuit and method for establishing transactions
US20060101249A1 (en) 2004-10-05 2006-05-11 Ibm Corporation Arrangements for adaptive response to latencies
US7072996B2 (en) 2001-06-13 2006-07-04 Corrent Corporation System and method of transferring data between a processing engine and a plurality of bus types using an arbiter
US20060203825A1 (en) 2005-03-08 2006-09-14 Edith Beigne Communication node architecture in a globally asynchronous network on chip system
US20060209846A1 (en) 2005-03-08 2006-09-21 Commissariat A L'energie Atomique Globally asynchronous communication architecture for system on chip
US20060242393A1 (en) 2005-04-20 2006-10-26 International Business Machines Corporation Branch target prediction for multi-target branches
US7162560B2 (en) 2003-12-31 2007-01-09 Intel Corporation Partitionable multiprocessor system having programmable interrupt controllers
US20070055961A1 (en) 2005-08-23 2007-03-08 Callister James R Systems and methods for re-ordering instructions
US20070055826A1 (en) 2002-11-04 2007-03-08 Newisys, Inc., A Delaware Corporation Reducing probe traffic in multiprocessor systems
US20070074191A1 (en) 2005-08-30 2007-03-29 Geisinger Nile J Software executables having virtual hardware, operating systems, and networks
US20070076739A1 (en) 2005-09-30 2007-04-05 Arati Manjeshwar Method and system for providing acknowledged broadcast and multicast communication
US20070180310A1 (en) 2006-02-02 2007-08-02 Texas Instruments, Inc. Multi-core architecture with hardware messaging
US20070271557A1 (en) 2005-08-30 2007-11-22 Geisinger Nile J Computing platform having transparent access to resources of a host platform
US20070283324A1 (en) 2005-08-30 2007-12-06 Geisinger Nile J System and method for creating programs that comprise several execution layers
US7376789B2 (en) 2005-06-29 2008-05-20 Intel Corporation Wide-port context cache apparatus, systems, and methods
US20080134191A1 (en) 2006-11-30 2008-06-05 Ulhas Warrier Methods and apparatuses for core allocations
US20080133885A1 (en) 2005-08-29 2008-06-05 Centaurus Data Llc Hierarchical multi-threading processor
US7394288B1 (en) 2004-12-13 2008-07-01 Massachusetts Institute Of Technology Transferring data in a parallel processing environment
US7398374B2 (en) 2002-02-27 2008-07-08 Hewlett-Packard Development Company, L.P. Multi-cluster processor for processing instructions of one or more instruction threads
US20080181115A1 (en) 2007-01-29 2008-07-31 Stmicroelectronics Sa System for transmitting data within a network between nodes of the network and flow control process for transmitting the data
US20080186998A1 (en) 2005-04-06 2008-08-07 Koninklijke Philips Electronics, N.V. Network-On-Chip Environment and Method for Reduction of Latency
US20080205432A1 (en) 2005-04-07 2008-08-28 Koninklijke Philips Electronics, N.V. Network-On-Chip Environment and Method For Reduction of Latency
US20080216073A1 (en) 1999-01-28 2008-09-04 Ati International Srl Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US7464197B2 (en) 2000-09-08 2008-12-09 Intel Corporation Distributed direct memory access for systems on chip
US20080307422A1 (en) 2007-06-08 2008-12-11 Kurland Aaron S Shared memory for multi-core processors
US20080320235A1 (en) 2007-06-22 2008-12-25 Microsoft Corporation Processor cache management with software input via an intermediary
US7478225B1 (en) 2004-06-30 2009-01-13 Sun Microsystems, Inc. Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor
US20090019190A1 (en) 2007-07-12 2009-01-15 Blocksome Michael A Low Latency, High Bandwidth Data Communications Between Compute Nodes in a Parallel Computer
US7493474B1 (en) 2004-11-10 2009-02-17 Altera Corporation Methods and apparatus for transforming, loading, and executing super-set instructions
US7500060B1 (en) 2007-03-16 2009-03-03 Xilinx, Inc. Hardware stack structure using programmable logic
US7502378B2 (en) 2006-11-29 2009-03-10 Nec Laboratories America, Inc. Flexible wrapper architecture for tiled networks on a chip
US20090083263A1 (en) 2007-09-24 2009-03-26 Cognitive Electronics, Inc. Parallel processing computer systems with reduced power consumption and methods for providing the same
US7521961B1 (en) 2007-01-23 2009-04-21 Xilinx, Inc. Method and system for partially reconfigurable switch
US7533154B1 (en) 2004-02-04 2009-05-12 Advanced Micro Devices, Inc. Descriptor management systems and methods for transferring data of multiple priorities between a host and a network
US20090125703A1 (en) 2007-11-09 2009-05-14 Mejdrich Eric O Context Switching on a Network On Chip
US20090125706A1 (en) 2007-11-08 2009-05-14 Hoover Russell D Software Pipelining on a Network on Chip
US20090125574A1 (en) 2007-11-12 2009-05-14 Mejdrich Eric O Software Pipelining On a Network On Chip
US7539124B2 (en) 2004-02-06 2009-05-26 Samsung Electronics Co., Ltd. Apparatus and method for setting routing path between routers in chip
US20090135739A1 (en) 2007-11-27 2009-05-28 Hoover Russell D Network On Chip With Partitions
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
US7568064B2 (en) 2006-02-21 2009-07-28 M2000 Packet-oriented communication in reconfigurable circuit(s)
US7590774B2 (en) 2005-12-01 2009-09-15 Kabushiki Kaisha Toshiba Method and system for efficient context swapping
US20090231349A1 (en) 2008-03-12 2009-09-17 Eric Oliver Mejdrich Rolling Context Data Structure for Maintaining State Data in a Multithreaded Image Processing Pipeline
US20090260013A1 (en) 2008-04-14 2009-10-15 International Business Machines Corporation Computer Processors With Plural, Pipelined Hardware Threads Of Execution
US7613882B1 (en) 2007-01-29 2009-11-03 3 Leaf Systems Fast invalidation for cache coherency in distributed shared memory system
US20090282222A1 (en) 2008-05-09 2009-11-12 International Business Machines Corporation Dynamic Virtual Software Pipelining On A Network On Chip
US7664108B2 (en) 2006-10-10 2010-02-16 Abdullah Ali Bahattab Route once and cross-connect many
US7689738B1 (en) 2003-10-01 2010-03-30 Advanced Micro Devices, Inc. Peripheral devices and methods for transferring incoming data status entries from a peripheral to a host
US7701252B1 (en) 2007-11-06 2010-04-20 Altera Corporation Stacked die network-on-chip for FPGA
US7861065B2 (en) 2008-05-09 2010-12-28 International Business Machines Corporation Preferential dispatching of computer program instructions
US7882307B1 (en) 2006-04-14 2011-02-01 Tilera Corporation Managing cache memory in a parallel processing environment
US7886084B2 (en) 2007-06-26 2011-02-08 International Business Machines Corporation Optimized collectives using a DMA on a parallel computer
US7913010B2 (en) 2008-02-15 2011-03-22 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US7917703B2 (en) 2007-12-13 2011-03-29 International Business Machines Corporation Network on chip that maintains cache coherency with invalidate commands
US7958340B2 (en) 2008-05-09 2011-06-07 International Business Machines Corporation Monitoring software pipeline performance on a network on chip
US7991978B2 (en) 2008-05-09 2011-08-02 International Business Machines Corporation Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor
US8010750B2 (en) 2008-01-17 2011-08-30 International Business Machines Corporation Network on chip that maintains cache coherency with invalidate commands
US8018466B2 (en) 2008-02-12 2011-09-13 International Business Machines Corporation Graphics rendering on a network on chip
US8040799B2 (en) 2008-05-15 2011-10-18 International Business Machines Corporation Network on chip with minimum guaranteed bandwidth for virtual communications channels

Family Cites Families (53)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2638065B2 (en) 1988-05-11 1997-08-06 富士通株式会社 Computer system
CA2067576C (en) 1991-07-10 1998-04-14 Jimmie D. Edrington Dynamic load balancing for a multiprocessor pipeline
JP3322754B2 (en) 1994-05-17 2002-09-09 富士通株式会社 Parallel computer
US5974498A (en) * 1996-09-24 1999-10-26 Texas Instruments Incorporated Loading page register with page value in branch instruction for as fast access to memory extension as in-page access
US5802386A (en) 1996-11-19 1998-09-01 International Business Machines Corporation Latency-based scheduling of instructions in a superscalar processor
JPH10232788A (en) 1996-12-17 1998-09-02 Fujitsu Ltd Signal processor and software
JP3849951B2 (en) 1997-02-27 2006-11-22 株式会社日立製作所 Shared memory multiprocessor
US6298370B1 (en) * 1997-04-04 2001-10-02 Texas Instruments Incorporated Computer operating process allocating tasks between first and second processors at run time based upon current processor load
US6179489B1 (en) * 1997-04-04 2001-01-30 Texas Instruments Incorporated Devices, methods, systems and software products for coordination of computer main microprocessor and second microprocessor coupled thereto
US6092159A (en) 1998-05-05 2000-07-18 Lsi Logic Corporation Implementation of configurable on-chip fast memory using the data cache RAM
WO2000002164A3 (en) * 1998-07-01 2000-04-06 Koninkl Philips Electronics Nv Computer graphics animation method and device
GB2385174B (en) 1999-01-19 2003-11-26 Advanced Risc Mach Ltd Memory control within data processing systems
US6567084B1 (en) 2000-07-27 2003-05-20 Ati International Srl Lighting effect computation circuit and method therefore
US6748492B1 (en) 2000-08-07 2004-06-08 Broadcom Corporation Deterministic setting of replacement policy in a cache through way selection
US20020087844A1 (en) 2000-12-29 2002-07-04 Udo Walterscheidt Apparatus and method for concealing switch latency
JP4790971B2 (en) * 2001-01-29 2011-10-12 ジョセフ エイ マッギル Adjustable dampers for air flow system
US7418068B2 (en) 2001-02-24 2008-08-26 International Business Machines Corporation Data capture technique for high speed signaling
EP1459180A2 (en) 2001-12-14 2004-09-22 Philips Electronics N.V. Data processing system
CN1311348C (en) 2001-12-14 2007-04-18 皇家飞利浦电子股份有限公司 Data processing system
KR100960413B1 (en) 2001-12-14 2010-05-28 엔엑스피 비 브이 Data processing system having multiple processors and a communication means in a data processing system having multiple processors
WO2003052597A3 (en) 2001-12-14 2004-05-13 Koninkl Philips Electronics Nv Data processing system having multiple processors and task scheduler and corresponding method therefore
US20040111594A1 (en) 2002-12-05 2004-06-10 International Business Machines Corporation Multithreading recycle and dispatch mechanism
US7254578B2 (en) 2002-12-10 2007-08-07 International Business Machines Corporation Concurrency classes for shared file systems
JP3892829B2 (en) 2003-06-27 2007-03-14 株式会社東芝 An information processing system and a memory management method
DE602005007014D1 (en) 2004-05-18 2008-07-03 Koninkl Philips Electronics Nv Integrated circuit and method for buffering to optimize the burst length in networks on chips
US7152155B2 (en) 2005-02-18 2006-12-19 Qualcomm Incorporated System and method of correcting a branch misprediction
EP1856860B1 (en) 2005-02-28 2010-11-17 Nxp B.V. Input buffered switch
JP4791530B2 (en) 2005-04-13 2011-10-12 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Electronic devices and flow control method
DE102005021340A1 (en) * 2005-05-04 2006-11-09 Carl Zeiss Smt Ag Optical unit for e.g. projection lens of microlithographic projection exposure system, has layer made of material with non-cubical crystal structure and formed on substrate, where sign of time delays in substrate and/or layer is opposite
EP1911218A2 (en) 2005-07-19 2008-04-16 Philips Electronics N.V. Electronic device and method of communication resource allocation
US8429661B1 (en) 2005-12-14 2013-04-23 Nvidia Corporation Managing multi-threaded FIFO memory by determining whether issued credit count for dedicated class of threads is less than limit
US8213461B2 (en) 2006-03-29 2012-07-03 Arm Limited Method of designating slots in a transmission frame for controlling transmission of data over an interconnect coupling a plurality of master units with a plurality of slave units
US8345053B2 (en) 2006-09-21 2013-01-01 Qualcomm Incorporated Graphics processors with parallel scheduling and execution of threads
US20080198166A1 (en) 2007-02-16 2008-08-21 Via Technologies, Inc. Multi-threads vertex shader, graphics processing unit, and flow control method
GB2447907B (en) 2007-03-26 2009-02-18 Imagination Tech Ltd Processing long-latency instructions in a pipelined processor
US20090109996A1 (en) 2007-10-29 2009-04-30 Hoover Russell D Network on Chip
US8245232B2 (en) 2007-11-27 2012-08-14 Microsoft Corporation Software-configurable and stall-time fair memory access scheduling mechanism for shared memory systems
US7873701B2 (en) 2007-11-27 2011-01-18 International Business Machines Corporation Network on chip with partitions
US8473667B2 (en) 2008-01-11 2013-06-25 International Business Machines Corporation Network on chip that maintains cache coherency with invalidation messages
US8490110B2 (en) 2008-02-15 2013-07-16 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US20090245257A1 (en) 2008-04-01 2009-10-01 International Business Machines Corporation Network On Chip
US8078850B2 (en) 2008-04-24 2011-12-13 International Business Machines Corporation Branch prediction technique using instruction for resetting result table pointer
US20090271172A1 (en) 2008-04-24 2009-10-29 International Business Machines Corporation Emulating A Computer Run Time Environment
US8423715B2 (en) 2008-05-01 2013-04-16 International Business Machines Corporation Memory management among levels of cache in a memory hierarchy
CA2664969C (en) * 2008-05-02 2011-09-20 Francis V. Smith High tonnage trailer combination, trailer components, and method of use
US8392664B2 (en) 2008-05-09 2013-03-05 International Business Machines Corporation Network on chip
US8494833B2 (en) 2008-05-09 2013-07-23 International Business Machines Corporation Emulating a computer run time environment
US20090282419A1 (en) 2008-05-09 2009-11-12 International Business Machines Corporation Ordered And Unordered Network-Addressed Message Control With Embedded DMA Commands For A Network On Chip
US8214845B2 (en) 2008-05-09 2012-07-03 International Business Machines Corporation Context switching in a network on chip by thread saving and restoring pointers to memory arrays containing valid message data
US20090282211A1 (en) 2008-05-09 2009-11-12 International Business Machines Network On Chip With Partitions
US8230179B2 (en) 2008-05-15 2012-07-24 International Business Machines Corporation Administering non-cacheable memory load instructions
US8438578B2 (en) 2008-06-09 2013-05-07 International Business Machines Corporation Network on chip with an I/O accelerator
US8195884B2 (en) 2008-09-18 2012-06-05 International Business Machines Corporation Network on chip with caching restrictions for pages of computer memory

Patent Citations (134)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4813037A (en) 1986-01-24 1989-03-14 Alcatel Nv Switching system
US4951195A (en) 1988-02-01 1990-08-21 International Business Machines Corporation Condition code graph analysis for simulating a CPU processor
US5167023A (en) 1988-02-01 1992-11-24 International Business Machines Translating a dynamic transfer control instruction address in a simulated CPU processor
US5301302A (en) 1988-02-01 1994-04-05 International Business Machines Corporation Memory mapping and special write detection in a system and method for simulating a CPU processor
US5884060A (en) 1991-05-15 1999-03-16 Ross Technology, Inc. Processor which performs dynamic instruction scheduling at time of execution within a single clock cycle
US5442797A (en) 1991-12-04 1995-08-15 Casavant; Thomas L. Latency tolerant risc-based multiple processor with event driven locality managers resulting from variable tagging
US6047122A (en) 1992-05-07 2000-04-04 Tm Patents, L.P. System for method for performing a context switch operation in a massively parallel computer system
US6145072A (en) 1993-08-12 2000-11-07 Hughes Electronics Corporation Independently non-homogeneously dynamically reconfigurable two dimensional interprocessor communication topology for SIMD multi-processors and apparatus for implementing same
US5590308A (en) 1993-09-01 1996-12-31 International Business Machines Corporation Method and apparatus for reducing false invalidations in distributed systems
US5870479A (en) 1993-10-25 1999-02-09 Koninklijke Ptt Nederland N.V. Device for processing data packets
US5784706A (en) 1993-12-13 1998-07-21 Cray Research, Inc. Virtual to logical to physical address translation for distributed memory massively parallel processing systems
US6625662B1 (en) 1995-10-04 2003-09-23 Kawasaki Microelectronics, Inc. Inter-network connecting device
US5761516A (en) 1996-05-03 1998-06-02 Lsi Logic Corporation Single chip multiprocessor architecture with internal task switching synchronization bus
US6049866A (en) 1996-09-06 2000-04-11 Silicon Graphics, Inc. Method and system for an efficient user mode cache manipulation using a simulated instruction
US5887166A (en) 1996-12-16 1999-03-23 International Business Machines Corporation Method and system for constructing a program including a navigation instruction
US5872963A (en) 1997-02-18 1999-02-16 Silicon Graphics, Inc. Resumption of preempted non-privileged threads with no kernel intervention
US6021470A (en) 1997-03-17 2000-02-01 Oracle Corporation Method and apparatus for selective data caching implemented with noncacheable and cacheable data for improved cache performance in a computer networking system
US6105119A (en) * 1997-04-04 2000-08-15 Texas Instruments Incorporated Data transfer circuitry, DSP wrapper circuitry and improved processor devices, methods and systems
US6044478A (en) 1997-05-30 2000-03-28 National Semiconductor Corporation Cache with finely granular locked-down regions
US6823429B1 (en) 1997-07-10 2004-11-23 International Business Machines Corporation Memory controller for controlling memory accesses across networks in distributed shared memory processing systems
US5974487A (en) 1997-07-14 1999-10-26 Advanced Micro Devices, Inc. Data transfer network on a chip utilizing a mesh of rings topology
US6085315A (en) 1997-09-12 2000-07-04 Siemens Aktiengesellschaft Data processing device with loop pipeline
US6151668A (en) 1997-11-07 2000-11-21 Billions Of Operations Per Second, Inc. Methods and apparatus for efficient synchronous MIMD operations with iVLIW PE-to-PE communication
US6085296A (en) * 1997-11-12 2000-07-04 Digital Equipment Corporation Sharing memory pages and page tables among computer processes
US6898791B1 (en) 1998-04-21 2005-05-24 California Institute Of Technology Infospheres distributed object system
US6164841A (en) 1998-05-04 2000-12-26 Hewlett-Packard Company Method, apparatus, and product for dynamic software code translation system
US6101599A (en) 1998-06-29 2000-08-08 Cisco Technology, Inc. System for context switching between processing elements in a pipeline of processing elements
US6119215A (en) 1998-06-29 2000-09-12 Cisco Technology, Inc. Synchronization and control system for an arrayed processing engine
US6675284B1 (en) 1998-08-21 2004-01-06 Stmicroelectronics Limited Integrated circuit with multiple processing cores
US6591347B2 (en) 1998-10-09 2003-07-08 National Semiconductor Corporation Dynamic replacement technique in a shared cache
US6370622B1 (en) 1998-11-20 2002-04-09 Massachusetts Institute Of Technology Method and apparatus for curious and column caching
US6292888B1 (en) 1999-01-27 2001-09-18 Clearwater Networks, Inc. Register transfer unit for electronic processor
US20080216073A1 (en) 1999-01-28 2008-09-04 Ati International Srl Apparatus for executing programs for a first computer architechture on a computer of a second architechture
US6272598B1 (en) 1999-03-22 2001-08-07 Hewlett-Packard Company Web cache performance by applying different replacement policies to the web cache
US6519605B1 (en) 1999-04-27 2003-02-11 International Business Machines Corporation Run-time translation of legacy emulator high level language application programming interface (EHLLAPI) calls to object-based calls
US6493817B1 (en) 1999-05-21 2002-12-10 Hewlett-Packard Company Floating-point unit which utilizes standard MAC units for performing SIMD operations
US7546444B1 (en) 1999-09-01 2009-06-09 Intel Corporation Register set used in multithreaded parallel processor architecture
US6434669B1 (en) 1999-09-07 2002-08-13 International Business Machines Corporation Method of cache management to dynamically update information-type dependent cache policies
US6950438B1 (en) 1999-09-17 2005-09-27 Advanced Micro Devices, Inc. System and method for implementing a separate virtual channel for posted requests in a multiprocessor computer system
US7010580B1 (en) 1999-10-08 2006-03-07 Agile Software Corp. Method and apparatus for exchanging data in a platform independent manner
US20030065890A1 (en) 1999-12-17 2003-04-03 Lyon Terry L. Method and apparatus for updating and invalidating store data
US6697932B1 (en) 1999-12-30 2004-02-24 Intel Corporation System and method for early resolution of low confidence branches and safe data cache accesses
US6446171B1 (en) 2000-03-02 2002-09-03 Mips Technologies, Inc. Method and apparatus for tracking and update of LRU algorithm using vectors
US6832184B1 (en) 2000-03-02 2004-12-14 International Business Machines Corporation Intelligent work station simulation—generalized LAN frame generation simulation structure
US6725317B1 (en) 2000-04-29 2004-04-20 Hewlett-Packard Development Company, L.P. System and method for managing a computer system having a plurality of partitions
US6567895B2 (en) 2000-05-31 2003-05-20 Texas Instruments Incorporated Loop cache memory and cache controller for pipelined microprocessors
US20040088487A1 (en) 2000-06-10 2004-05-06 Barroso Luiz Andre Scalable architecture based on single-chip multiprocessing
US6668308B2 (en) 2000-06-10 2003-12-23 Hewlett-Packard Development Company, L.P. Scalable architecture based on single-chip multiprocessing
US7464197B2 (en) 2000-09-08 2008-12-09 Intel Corporation Distributed direct memory access for systems on chip
US6668307B1 (en) 2000-09-29 2003-12-23 Sun Microsystems, Inc. System and method for a software controlled cache
US6877086B1 (en) 2000-11-02 2005-04-05 Intel Corporation Method and apparatus for rescheduling multiple micro-operations in a processor using a replay queue and a counter
US6973032B1 (en) 2000-12-04 2005-12-06 Cisco Technology, Inc. Selective backpressure control for multistage switches
US20020099833A1 (en) 2001-01-24 2002-07-25 Steely Simon C. Cache coherency mechanism using arbitration masks
US6891828B2 (en) 2001-03-12 2005-05-10 Network Excellence For Enterprises Corp. Dual-loop bus-based network switch using distance-value or bit-mask
US6938253B2 (en) 2001-05-02 2005-08-30 Portalplayer, Inc. Multiprocessor communication system and method
US6915402B2 (en) 2001-05-23 2005-07-05 Hewlett-Packard Development Company, L.P. Method and system for creating secure address space using hardware memory router
US20020178337A1 (en) 2001-05-23 2002-11-28 Wilson Kenneth Mark Method and system for creating secure address space using hardware memory router
US7072996B2 (en) 2001-06-13 2006-07-04 Corrent Corporation System and method of transferring data between a processing engine and a plurality of bus types using an arbiter
US6988149B2 (en) 2002-02-26 2006-01-17 Lsi Logic Corporation Integrated target masking
US7398374B2 (en) 2002-02-27 2008-07-08 Hewlett-Packard Development Company, L.P. Multi-cluster processor for processing instructions of one or more instruction threads
US7015909B1 (en) 2002-03-19 2006-03-21 Aechelon Technology, Inc. Efficient use of user-defined shaders to implement graphics operations
US20040037313A1 (en) 2002-05-15 2004-02-26 Manu Gulati Packet data service over hyper transport link(s)
US20060095920A1 (en) 2002-10-08 2006-05-04 Koninklijke Philips Electronics N.V. Integrated circuit and method for establishing transactions
US20040151197A1 (en) 2002-10-21 2004-08-05 Hui Ronald Chi-Chun Priority queue architecture for supporting per flow queuing and multiple ports
US20040083341A1 (en) 2002-10-24 2004-04-29 Robinson John T. Weighted cache line replacement
US20070055826A1 (en) 2002-11-04 2007-03-08 Newisys, Inc., A Delaware Corporation Reducing probe traffic in multiprocessor systems
US20040153579A1 (en) 2003-01-30 2004-08-05 Ching-Chih Shih Virtual disc drive control device
US20040250046A1 (en) 2003-03-31 2004-12-09 Gonzalez Ricardo E. Systems and methods for software extensible multi-processing
US20040260906A1 (en) 2003-04-04 2004-12-23 Sun Microsystems, Inc. Performing virtual to global address translation in processing subsystem
US20040216105A1 (en) 2003-04-24 2004-10-28 International Business Machines Corporation Method for resource balancing using dispatch flush in a simultaneous multithread processor
US20050203988A1 (en) 2003-06-02 2005-09-15 Vincent Nollet Heterogeneous multiprocessor network on chip devices, methods and operating systems for control thereof
US20050044319A1 (en) 2003-08-19 2005-02-24 Sun Microsystems, Inc. Multi-core multi-thread processor
US20050086435A1 (en) 2003-09-09 2005-04-21 Seiko Epson Corporation Cache memory controlling apparatus, information processing apparatus and method for control of cache memory
CN1599471A (en) 2003-09-17 2005-03-23 华为技术有限公司 Realization method and device for controlling load balance in communication system
US7689738B1 (en) 2003-10-01 2010-03-30 Advanced Micro Devices, Inc. Peripheral devices and methods for transferring incoming data status entries from a peripheral to a host
US20050097184A1 (en) 2003-10-31 2005-05-05 Brown David A. Internal memory controller providing configurable access of processor clients to memory instances
US20050149689A1 (en) 2003-12-30 2005-07-07 Intel Corporation Method and apparatus for rescheduling operations in a processor
US7162560B2 (en) 2003-12-31 2007-01-09 Intel Corporation Partitionable multiprocessor system having programmable interrupt controllers
US20050160209A1 (en) 2004-01-20 2005-07-21 Van Doren Stephen R. System and method for resolving transactions in a cache coherency protocol
US20050166205A1 (en) 2004-01-22 2005-07-28 University Of Washington Wavescalar architecture having a wave order memory
US7533154B1 (en) 2004-02-04 2009-05-12 Advanced Micro Devices, Inc. Descriptor management systems and methods for transferring data of multiple priorities between a host and a network
US7539124B2 (en) 2004-02-06 2009-05-26 Samsung Electronics Co., Ltd. Apparatus and method for setting routing path between routers in chip
US20050198442A1 (en) 2004-03-02 2005-09-08 Mandler Alberto R. Conditionally accessible cache memory
US20050238035A1 (en) 2004-04-27 2005-10-27 Hewlett-Packard System and method for remote direct memory access over a network switch fabric
US7478225B1 (en) 2004-06-30 2009-01-13 Sun Microsystems, Inc. Apparatus and method to support pipelining of differing-latency instructions in a multithreaded processor
US20060101249A1 (en) 2004-10-05 2006-05-11 Ibm Corporation Arrangements for adaptive response to latencies
US7493474B1 (en) 2004-11-10 2009-02-17 Altera Corporation Methods and apparatus for transforming, loading, and executing super-set instructions
US7394288B1 (en) 2004-12-13 2008-07-01 Massachusetts Institute Of Technology Transferring data in a parallel processing environment
US20060209846A1 (en) 2005-03-08 2006-09-21 Commissariat A L'energie Atomique Globally asynchronous communication architecture for system on chip
US20060203825A1 (en) 2005-03-08 2006-09-14 Edith Beigne Communication node architecture in a globally asynchronous network on chip system
US20080186998A1 (en) 2005-04-06 2008-08-07 Koninklijke Philips Electronics, N.V. Network-On-Chip Environment and Method for Reduction of Latency
US20080205432A1 (en) 2005-04-07 2008-08-28 Koninklijke Philips Electronics, N.V. Network-On-Chip Environment and Method For Reduction of Latency
US20060242393A1 (en) 2005-04-20 2006-10-26 International Business Machines Corporation Branch target prediction for multi-target branches
US7376789B2 (en) 2005-06-29 2008-05-20 Intel Corporation Wide-port context cache apparatus, systems, and methods
US20070055961A1 (en) 2005-08-23 2007-03-08 Callister James R Systems and methods for re-ordering instructions
US20080133885A1 (en) 2005-08-29 2008-06-05 Centaurus Data Llc Hierarchical multi-threading processor
US20070074191A1 (en) 2005-08-30 2007-03-29 Geisinger Nile J Software executables having virtual hardware, operating systems, and networks
US20080028401A1 (en) 2005-08-30 2008-01-31 Geisinger Nile J Software executables having virtual hardware, operating systems, and networks
US20070283324A1 (en) 2005-08-30 2007-12-06 Geisinger Nile J System and method for creating programs that comprise several execution layers
US20070271557A1 (en) 2005-08-30 2007-11-22 Geisinger Nile J Computing platform having transparent access to resources of a host platform
US20070076739A1 (en) 2005-09-30 2007-04-05 Arati Manjeshwar Method and system for providing acknowledged broadcast and multicast communication
US7590774B2 (en) 2005-12-01 2009-09-15 Kabushiki Kaisha Toshiba Method and system for efficient context swapping
US20070180310A1 (en) 2006-02-02 2007-08-02 Texas Instruments, Inc. Multi-core architecture with hardware messaging
US7568064B2 (en) 2006-02-21 2009-07-28 M2000 Packet-oriented communication in reconfigurable circuit(s)
US7882307B1 (en) 2006-04-14 2011-02-01 Tilera Corporation Managing cache memory in a parallel processing environment
US7664108B2 (en) 2006-10-10 2010-02-16 Abdullah Ali Bahattab Route once and cross-connect many
US7502378B2 (en) 2006-11-29 2009-03-10 Nec Laboratories America, Inc. Flexible wrapper architecture for tiled networks on a chip
US20080134191A1 (en) 2006-11-30 2008-06-05 Ulhas Warrier Methods and apparatuses for core allocations
US7521961B1 (en) 2007-01-23 2009-04-21 Xilinx, Inc. Method and system for partially reconfigurable switch
US20080181115A1 (en) 2007-01-29 2008-07-31 Stmicroelectronics Sa System for transmitting data within a network between nodes of the network and flow control process for transmitting the data
US7613882B1 (en) 2007-01-29 2009-11-03 3 Leaf Systems Fast invalidation for cache coherency in distributed shared memory system
US7500060B1 (en) 2007-03-16 2009-03-03 Xilinx, Inc. Hardware stack structure using programmable logic
US20080307422A1 (en) 2007-06-08 2008-12-11 Kurland Aaron S Shared memory for multi-core processors
US20080320235A1 (en) 2007-06-22 2008-12-25 Microsoft Corporation Processor cache management with software input via an intermediary
US7886084B2 (en) 2007-06-26 2011-02-08 International Business Machines Corporation Optimized collectives using a DMA on a parallel computer
US20090019190A1 (en) 2007-07-12 2009-01-15 Blocksome Michael A Low Latency, High Bandwidth Data Communications Between Compute Nodes in a Parallel Computer
US20090083263A1 (en) 2007-09-24 2009-03-26 Cognitive Electronics, Inc. Parallel processing computer systems with reduced power consumption and methods for providing the same
US7701252B1 (en) 2007-11-06 2010-04-20 Altera Corporation Stacked die network-on-chip for FPGA
US20090125706A1 (en) 2007-11-08 2009-05-14 Hoover Russell D Software Pipelining on a Network on Chip
US20090125703A1 (en) 2007-11-09 2009-05-14 Mejdrich Eric O Context Switching on a Network On Chip
US20090125574A1 (en) 2007-11-12 2009-05-14 Mejdrich Eric O Software Pipelining On a Network On Chip
US20090135739A1 (en) 2007-11-27 2009-05-28 Hoover Russell D Network On Chip With Partitions
US7917703B2 (en) 2007-12-13 2011-03-29 International Business Machines Corporation Network on chip that maintains cache coherency with invalidate commands
US8010750B2 (en) 2008-01-17 2011-08-30 International Business Machines Corporation Network on chip that maintains cache coherency with invalidate commands
US8018466B2 (en) 2008-02-12 2011-09-13 International Business Machines Corporation Graphics rendering on a network on chip
US7913010B2 (en) 2008-02-15 2011-03-22 International Business Machines Corporation Network on chip with a low latency, high bandwidth application messaging interconnect
US20090231349A1 (en) 2008-03-12 2009-09-17 Eric Oliver Mejdrich Rolling Context Data Structure for Maintaining State Data in a Multithreaded Image Processing Pipeline
US20090260013A1 (en) 2008-04-14 2009-10-15 International Business Machines Corporation Computer Processors With Plural, Pipelined Hardware Threads Of Execution
US7861065B2 (en) 2008-05-09 2010-12-28 International Business Machines Corporation Preferential dispatching of computer program instructions
US7991978B2 (en) 2008-05-09 2011-08-02 International Business Machines Corporation Network on chip with low latency, high bandwidth application messaging interconnects that abstract hardware inter-thread data communications into an architected state of a processor
US8020168B2 (en) 2008-05-09 2011-09-13 International Business Machines Corporation Dynamic virtual software pipelining on a network on chip
US20090282222A1 (en) 2008-05-09 2009-11-12 International Business Machines Corporation Dynamic Virtual Software Pipelining On A Network On Chip
US7958340B2 (en) 2008-05-09 2011-06-07 International Business Machines Corporation Monitoring software pipeline performance on a network on chip
US8040799B2 (en) 2008-05-15 2011-10-18 International Business Machines Corporation Network on chip with minimum guaranteed bandwidth for virtual communications channels

Non-Patent Citations (132)

* Cited by examiner, † Cited by third party
Title
1994-2010 China Academic Journal Electronic Publishing House, pp. 0-30 and pp. 31-66 (includes English abstract).
Advisory Action U.S. Appl. No. 11/926,212, Nov. 2, 2010.
Advisory Action, U.S. Appl. No. 11/945,396, Mar. 21, 2012.
Advisory Action, U.S. Appl. No. 12/118,315, Mar. 27, 2012.
Al-Hashimi; ("System-on-Chip-Net Generation Electronics", "Asynchronous on-chip networks"2006); Chapter 18 p. l-32.
Bolotin, et al. "The Power of Priority: NoC based Distributed Cache Coherency". Published May 21, 2007, pp. 117-126, ISBN 0-7695-2773-06/07 by IEEE.
Bolotin, et al., The Power of Priority:NoC based Distributed Cache Coherency, May 21, 2007, IEEE, pp. 117-126.
Cifuentes et al. "Walkabout-A Retargetable Dynamic Binary Translation Framework", Sun Microsystems Laboratories, Jan. 2002, 13 pages.
Cifuentes et al. "Walkabout—A Retargetable Dynamic Binary Translation Framework", Sun Microsystems Laboratories, Jan. 2002, 13 pages.
David Taylor, et al. "System on Chip Packet Processor for an Experimental Network Service Platform". 2003.
Final Office Action Dated Jan. 15, 2010 in U.S. Appl. No. 12/031,733.
Final Office Action Dated May 19, 2010 in U.S. Appl. No. 11/945,396.
Final Office Action U.S. Appl. No. 11/926,212, Aug. 23, 2010.
Final Office Action U.S. Appl. No. 11/926,212, May 17, 2011.
Final Office Action U.S. Appl. No. 11/936,873, Dec. 30, 2011.
Final Office Action U.S. Appl. No. 11/937,579, Feb. 23, 2011.
Final Office Action U.S. Appl. No. 11/945,396, Sep. 1, 2011.
Final Office Action U.S. Appl. No. 11/955,553, Sep. 13, 2010.
Final Office Action U.S. Appl. No. 11/972,753, Feb. 18, 2011.
Final Office Action U.S. Appl. No. 11/972,753, Sep. 7, 2011.
Final Office Action U.S. Appl. No. 12,031,733, Aug. 19, 2010.
Final Office Action U.S. Appl. No. 12,118,059, Feb. 17, 2011.
Final Office Action U.S. Appl. No. 12/015,975, Jan. 7, 2011.
Final Office Action U.S. Appl. No. 12/031,738, Dec. 22, 2011.
Final Office Action U.S. Appl. No. 12/060,559, Jul. 8, 2011.
Final Office Action U.S. Appl. No. 12/108,770, Sep. 30, 2011.
Final Office Action U.S. Appl. No. 12/108,846, Feb. 17, 2011.
Final Office Action U.S. Appl. No. 12/113,286, Feb. 18, 2011.
Final Office Action U.S. Appl. No. 12/117,875, Nov. 10, 2010.
Final Office Action U.S. Appl. No. 12/117,906, Mar. 28, 2011.
Final Office Action U.S. Appl. No. 12/118,017, Mar. 28, 2011.
Final Office Action, U.S. Appl. No. 11/937,579, Jan. 19, 2012.
Final Office Action, U.S. Appl. No. 12/135,364, Jan. 26, 2012.
Huneycutt et al. "Software Caching using Dynamic Binary Rewriting for Embedded Devices", 2001, Proceedings of the International Conference on Parallel Processing, 10 pages.
Intel, E8870 Chipset, Intel, Jun. 2002, pp. 1-10.
Issenin et al.; (Date Reuse Driven Memory and network-on-Chip Co-Synthesis); NSF; pp. 1-7.
Kavaldijev et al. ("Providing QOS Guaranteed in a NOC by Virtual Channel Reservation"); 2006; pp. 1-12.
Kumar et al.; "A Network on Chip Architecture and Design Methodology";2002; IEEE.
Kumar, et al. "A Network on Chip Architecture and Design Methodology". Published 2002, pp. 1-8, ISBN 0-7695-1486-03/02 by IEEE.
Kuskin, et al.; The Stanford Flash Multiprocessor; Jun. 6, 1996; Stanford University.
Master Dissertation, University of Electronic Science and Technology of China, pp. 0-35 and pp. 36-81 (includes English abstract).
Mereu, "Conception, Analysis, Design and Realization of a Multi-socket Network-on-Chip Architecture and of the Binary Translation support for VLIW core targeted to Systems-on-Chip", Mar. 2007, 145 pages, accessible at http://www.diee.unica.it/driei/tesi/19—mereu.pdf.
Mereu, Gianni. "Conception, Analysis, Design and Realization of a Multi-socket Network-on-Chip Architecture and of the Binary Translation support for VLIW core targeted to Systems-on-Chip", Mar. 2007, 145 pages, accessible at http://www.diee.unica.it/driei/tesi/19-mereu.pdf.
Mereu, Gianni. "Conception, Analysis, Design and Realization of a Multi-socket Network-on-Chip Architecture and of the Binary Translation support for VLIW core targeted to Systems-on-Chip", Mar. 2007, 145 pages, accessible at http://www.diee.unica.it/driei/tesi/19—mereu.pdf.
Monchiero ("Exploration of Distributed Shared Memory Architecture of NOC-Based Microprocessors", 2007) pp. 1-8.
Nikolay Kvaldjiev et al., A Virtual Channel Network-on-chip for GT and BE traffic, Apr. 2006, IEEE Emerging VLSI Technologies and Architectures.
Nollet, V., et al., "Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles" [online]. 2005 [retrieved Jul. 15, 2011], Retrieved from Internet: http://portal.acm.org/ft-gateway.cfm?id=1049106&type=pdf&CFID=32720390&CFTOKEN=986277114, pp. 1-6.
Nollet, V., et al., "Centralized Run-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles" [online]. 2005 [retrieved Jul. 15, 2011], Retrieved from Internet: http://portal.acm.org/ft—gateway.cfm?id=1049106&type=pdf&CFID=32720390&CFTOKEN=986277114, pp. 1-6.
Notice of Allowance U.S. Appl. No. 11/955,553, Nov. 22, 2010.
Notice of Allowance U.S. Appl. No. 12/015,975, Apr. 15, 2011.
Notice of Allowance U.S. Appl. No. 12/029,647, Feb. 25, 2011.
Notice of Allowance U.S. Appl. No. 12/031,733, Nov. 16, 2010.
Notice of Allowance U.S. Appl. No. 12/108,846, May 13, 2011.
Notice of Allowance U.S. Appl. No. 12/117,875, Jan. 27, 2011.
Notice of Allowance U.S. Appl. No. 12/117,897, May 4, 2011.
Notice of Allowance U.S. Appl. No. 12/118,272, Mar. 22, 2011.
Notice of Allowance U.S. Appl. No. 12/118,298, Aug. 18, 2010.
Notice of Allowance U.S. Appl. No. 12/121,168, Mar. 22, 2011.
Notice of Allowance U.S. Appl. No. 12/121,168, Sep. 9, 2011.
Notice of Allowance, U.S. Appl. No. 12/118,039, Feb. 23, 2012.
Notice of Allowance, U.S. Appl. No. 12/121,222, Feb. 3, 2012.
Notice of Allowance, U.S. Appl. No. 12/233,180, Feb. 3, 2012.
Office Action Dated Apr. 2, 2010 in U.S. Appl. No. 11/955,553.
Office Action Dated Jan. 29, 2010 in U.S. Appl. No. 11/945,396.
Office Action Dated Jul. 20, 2009 in U.S. Appl. No. 12/031,733.
Office Action Dated Jun. 8, 2010 in U.S. Appl. No. 12/118,298.
Office Action Dated Mar. 24, 2010 in U.S. Appl. No. 12/031,733.
Office Action Dated Mar. 30, 2010 in U.S. Appl. No. 11/926,212.
Office Action Dated May 26, 2010 in U.S. Appl. No. 12/117,875.
Office Action U.S. Appl. No. 11/926,212, Dec. 7, 2010.
Office Action U.S. Appl. No. 11/936,873, Jul. 21, 2011.
Office Action U.S. Appl. No. 11/937,579, Aug. 15, 2011.
Office Action U.S. Appl. No. 11/937,579, Sep. 16, 2010.
Office Action U.S. Appl. No. 11/945,396, Dec. 9, 2010.
Office Action U.S. Appl. No. 11/945,396, Mar. 3, 2011.
Office Action U.S. Appl. No. 11/972,753, Oct. 4, 2010.
Office Action U.S. Appl. No. 12,031,738, Jul. 11, 2011.
Office Action U.S. Appl. No. 12/015,975, Jul. 22, 2010.
Office Action U.S. Appl. No. 12/060,559, Apr. 1, 2011.
Office Action U.S. Appl. No. 12/060,559, Nov. 3, 2010.
Office Action U.S. Appl. No. 12/102,033, Oct. 7, 2011.
Office Action U.S. Appl. No. 12/108,770, Apr. 12, 2011.
Office Action U.S. Appl. No. 12/108,846, Dec. 2, 2010.
Office Action U.S. Appl. No. 12/113,286, Oct. 14, 2010.
Office Action U.S. Appl. No. 12/117,906, May 9, 2008.
Office Action U.S. Appl. No. 12/118,017, Dec. 8, 2010.
Office Action U.S. Appl. No. 12/118,059, Sep. 1, 2010.
Office Action U.S. Appl. No. 12/118,272, Dec. 2, 2010.
Office Action U.S. Appl. No. 12/118,315, Jul. 26, 2011.
Office Action U.S. Appl. No. 12/121,168, Oct. 5, 2010.
Office Action U.S. Appl. No. 12/121,222, Sep. 20, 2011.
Office Action U.S. Appl. No. 12/135,364, Aug. 5, 2011.
Office Action U.S. Appl. No. 12/233,180, Oct. 6, 2011.
Office Action, U.S. Appl. No. 11/972,753, Jan. 19, 2012.
Office Action, U.S. Appl. No. 12/113,286, Feb. 17, 2012.
Pande et al., "Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures", IEEE Transactions on Computers, vol. 54, No. 8, Aug. 2005, pp. 1025-1040, IEEE Computer Society, USA.
Radulescu et al. (An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration, Mar. 2004, pp. 1-6). *
RCE, U.S. Appl. No. 11/936,873, Mar. 16, 2012.
Samman et al., "Networks-On-Chip Based on Dynamic Wormhole Packet Identity Mapping Management", VLSI Design, Aug. 7, 2008, 15 pp., vol. 2009, Article ID 941701, Hindawi Publishing Corporation, USA.
Steve Furber, Future Trends in SOC Interconnect, Aug. 2000.
U.S. Appl. No. 11/926,212, filed Oct. 29, 2007, Hoover, et al.
U.S. Appl. No. 11/936,873, filed Nov. 8, 2007, Hoover, et al.
U.S. Appl. No. 11/937,579, filed Nov. 9, 2007, Mejdrich, et al.
U.S. Appl. No. 11/938,376, filed Nov. 12, 2007, Mejdrich, et al.
U.S. Appl. No. 11/945,396, filed Nov. 27, 2007, Hoover, et al.
U.S. Appl. No. 11/955,553, filed Dec. 13, 2007, Comparan, et al.
U.S. Appl. No. 11/972,753, filed Jan. 11, 2008, Mejdrich, et al.
U.S. Appl. No. 12/015,975, filed Jan. 17, 2008, Comparan, et al.
U.S. Appl. No. 12/029,647, filed Feb. 12, 2008, Hoover, et al.
U.S. Appl. No. 12/031,733, filed Feb. 15, 2008, Hoover, et al.
U.S. Appl. No. 12/031,738, filed Feb. 15, 2008, Hoover, et al.
U.S. Appl. No. 12/060,559, filed Apr. 1, 2008, Comparan, et al.
U.S. Appl. No. 12/102,033, filed Apr. 14, 2008, Heil, et al.
U.S. Appl. No. 12/108,770, filed Apr. 24, 2008, Mejdrich, et al.
U.S. Appl. No. 12/108,846, filed Apr. 24, 2008, Kuesel, et al.
U.S. Appl. No. 12/113,286, filed May 1, 2008, Heil, et al.
U.S. Appl. No. 12/117,875, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/117,897, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/117,906, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/118,017, filed May 9, 2008, Comparan, et al.
U.S. Appl. No. 12/118,039, filed May 9, 2008, Hoover, et al.
U.S. Appl. No. 12/118,059, filed May 9, 2008, Mejdrich, et al.
U.S. Appl. No. 12/118,272, filed May 9, 2008, Kuesel, et al.
U.S. Appl. No. 12/118,298, May 9, 2008, Heil, et al.
U.S. Appl. No. 12/118,315, filed May 9, 2008, Mejdrich, et al.
U.S. Appl. No. 12/121,168, filed May 15, 2008, Hoover, et al.
U.S. Appl. No. 12/121,222, filed May 15, 2008, Kriegel, et al.
U.S. Appl. No. 12/135,364, filed Jun. 9, 2008, Hoover, et al.
U.S. Appl. No. 12/233,180, filed Sep. 18, 2008, Hoover, et al.
Virtanen, et al. "NoC Interface for a Protocol Processor". University of Turku.
Walter, et al., "BENoC: A Bus-Enhanced Network on-Chip". Dec. 2007, Technion, Israel Institute of Technology, Haifa, Israel.
Wikipedia, "Parallel Computing", Wikipedia [online], URL: http://en.wikipedia.org/wiki/Parallel—computing, Jan. 19, 2007, pp. 1-6, USA.

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9590813B1 (en) 2013-08-07 2017-03-07 Netspeed Systems Supporting multicast in NoC interconnect
US9158882B2 (en) * 2013-12-19 2015-10-13 Netspeed Systems Automatic pipelining of NoC channels to meet timing and/or performance
US20150178435A1 (en) * 2013-12-19 2015-06-25 Netspeed Systems Automatic pipelining of noc channels to meet timing and/or performance
US9769077B2 (en) 2014-02-20 2017-09-19 Netspeed Systems QoS in a system with end-to-end flow control and QoS aware buffer allocation
US9742630B2 (en) 2014-09-22 2017-08-22 Netspeed Systems Configurable router for a network on chip (NoC)
US9860197B2 (en) 2015-02-03 2018-01-02 Netspeed Systems, Inc. Automatic buffer sizing for optimal network-on-chip design
US9825887B2 (en) 2015-02-03 2017-11-21 Netspeed Systems Automatic buffer sizing for optimal network-on-chip design
US9444702B1 (en) 2015-02-06 2016-09-13 Netspeed Systems System and method for visualization of NoC performance based on simulation output
US9829962B2 (en) 2015-02-12 2017-11-28 Netspeed Systems, Inc. Hardware and software enabled implementation of power profile management instructions in system on chip
US9568970B1 (en) 2015-02-12 2017-02-14 Netspeed Systems, Inc. Hardware and software enabled implementation of power profile management instructions in system on chip
US9928204B2 (en) 2015-02-12 2018-03-27 Netspeed Systems, Inc. Transaction expansion for NoC simulation and NoC design
US9825809B2 (en) 2015-05-29 2017-11-21 Netspeed Systems Dynamically configuring store-and-forward channels and cut-through channels in a network-on-chip
US9864728B2 (en) 2015-05-29 2018-01-09 Netspeed Systems, Inc. Automatic generation of physically aware aggregation/distribution networks

Also Published As

Publication number Publication date Type
US20120209944A1 (en) 2012-08-16 application
US8898396B2 (en) 2014-11-25 grant
US20090125574A1 (en) 2009-05-14 application

Similar Documents

Publication Publication Date Title
Enslow Jr Multiprocessor organization—A survey
US7502876B1 (en) Background memory manager that determines if data structures fits in memory with memory state transactions map
US8392661B1 (en) Managing cache coherence
US6961761B2 (en) System and method for partitioning a computer system into domains
US8250164B2 (en) Query performance data on parallel computer system having compute nodes
US20030110166A1 (en) Queue management
US7516456B2 (en) Asymmetric heterogeneous multi-threaded operating system
US20020174316A1 (en) Dynamic resource management and allocation in a distributed processing device
US20050071828A1 (en) System and method for compiling source code for multi-processor environments
US20060041715A1 (en) Multiprocessor chip having bidirectional ring interconnect
US4872125A (en) Multiple processor accelerator for logic simulation
US20070136458A1 (en) Creation and management of ATPT in switches of multi-host PCI topologies
US20060253682A1 (en) Managing computer memory in a computing environment with dynamic logical partitioning
US20100023631A1 (en) Processing Data Access Requests Among A Plurality Of Compute Nodes
US20070192518A1 (en) Apparatus for performing I/O sharing & virtualization
US20100165874A1 (en) Differentiating Blade Destination and Traffic Types in a Multi-Root PCIe Environment
US20090150647A1 (en) Processing Unit Incorporating Vectorizable Execution Unit
US20050060705A1 (en) Optimizing critical section microblocks by controlling thread execution
US7552312B2 (en) Identifying messaging completion in a parallel computer by checking for change in message received and transmitted count at each node
US20030088608A1 (en) Method and apparatus for dispatching tasks in a non-uniform memory access (NUMA) computer system
US20050027900A1 (en) Method and apparatus for a shared I/O serial ATA controller
US4916647A (en) Hardwired pipeline processor for logic simulation
US20060230208A1 (en) System and method for presenting interrupts
US20090138892A1 (en) Dispatching Packets on a Global Combining Network of a Parallel Computer
US20080141264A1 (en) Methods and systems for load balancing of virtual machines in clustered processors using storage related load information

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MEJDRICH, ERIC O.;SCHARDT, PAUL E.;SHEARER, ROBERT A.;REEL/FRAME:020095/0553;SIGNING DATES FROM 20071026 TO 20071108

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:MEJDRICH, ERIC O.;SCHARDT, PAUL E.;SHEARER, ROBERT A.;SIGNING DATES FROM 20071026 TO 20071108;REEL/FRAME:020095/0553

REMI Maintenance fee reminder mailed
LAPS Lapse for failure to pay maintenance fees
FP Expired due to failure to pay maintenance fee

Effective date: 20160904