US8078771B2 - Sending large command descriptor block (CDB) structures in serial attached SCSI (SAS) controller - Google Patents
Sending large command descriptor block (CDB) structures in serial attached SCSI (SAS) controller Download PDFInfo
- Publication number
- US8078771B2 US8078771B2 US12/315,704 US31570408A US8078771B2 US 8078771 B2 US8078771 B2 US 8078771B2 US 31570408 A US31570408 A US 31570408A US 8078771 B2 US8078771 B2 US 8078771B2
- Authority
- US
- United States
- Prior art keywords
- cdb
- message frame
- transmit
- sas
- bytes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related, expires
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
Definitions
- the CDB Transmit Block 102 may receive one or more Message Frames 101 .
- the CDB Transmit Block 102 may be responsible for reading 10 (input/output) command information from a Message Frame 101 , translating that information into a SAS Command Frame, and/or initializing the Context Memory 104 for that IO for subsequent utilization of that IO by other design modules.
- a Message Frame 101 may comprise the main programming interface to the CDB Transmit Block 102 .
- the CDB Transmit Block 102 may contain a required amount of storage elements to process CDB sizes up to approximately 32 bytes, or small CDBs. When a CDB is approximately 32 bytes or less, the CDB may be contained within the Message Frame 101 .
- the DMA Queue 105 may comprise a FIFO (first-in-first-out) structure and contain one or more entries of information to be processed by the Transmit DMA Engine 106 .
- the DMA Queue 105 may be utilized to store work that is required in the normal processing of SAS IOs.
- the Transmit DMA Engine 106 may be utilized to transfer the actual user data for a given command, received as entries from the DMA Queue 105 . These entries may be utilized to supply an address pointer to the data that needs to be transferred. These transfers typically are in terms of sectors or blocks of data, typically in the multi-kilobyte amounts.
- the Transmit DMA Engine 106 may include a DMA buffer (such as a 4 kilobyte buffer) to efficiently handle the data transfer for user data.
- DMA Queue Entry Type This field indicates whether the DMA Queue Entry is for a normal IO operation, or for a large CDB operation.
- Device Address This field indicates some form of device addressing information to specify the unique target device that the SAS frame is transmitted to.
- Frame Type This field indicates the value of the FRAME TYPE field of the transmitted SAS frame (as specified by the SAS specification).
- TAG This field indicates the value of the TAG field of the transmitted SAS frame.
- CDB Address This field contains the address pointer as indicated Pointer from the original Message Frame 101 specifying the location of the CDB in CDB Memory 103.
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
Abstract
Description
Entry Type | This field indicates whether the DMA Queue Entry |
is for a normal IO operation, or for a large CDB | |
operation. | |
Device Address | This field indicates some form of device addressing |
information to specify the unique target device that | |
the SAS frame is transmitted to. | |
Frame Type | This field indicates the value of the FRAME TYPE |
field of the transmitted SAS frame (as specified by | |
the SAS specification). | |
TAG | This field indicates the value of the TAG field of the |
transmitted SAS frame. | |
CDB Address | This field contains the address pointer as indicated |
Pointer | from the |
the location of the CDB in |
|
Claims (12)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US12/315,704 US8078771B2 (en) | 2008-10-31 | 2008-12-05 | Sending large command descriptor block (CDB) structures in serial attached SCSI (SAS) controller |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US19797408P | 2008-10-31 | 2008-10-31 | |
US12/315,704 US8078771B2 (en) | 2008-10-31 | 2008-12-05 | Sending large command descriptor block (CDB) structures in serial attached SCSI (SAS) controller |
Publications (2)
Publication Number | Publication Date |
---|---|
US20100115152A1 US20100115152A1 (en) | 2010-05-06 |
US8078771B2 true US8078771B2 (en) | 2011-12-13 |
Family
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Application Number | Title | Priority Date | Filing Date |
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US12/315,704 Expired - Fee Related US8078771B2 (en) | 2008-10-31 | 2008-12-05 | Sending large command descriptor block (CDB) structures in serial attached SCSI (SAS) controller |
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US (1) | US8078771B2 (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US9152553B1 (en) * | 2011-12-15 | 2015-10-06 | Marvell International Ltd. | Generic command descriptor for controlling memory devices |
US9824004B2 (en) | 2013-10-04 | 2017-11-21 | Micron Technology, Inc. | Methods and apparatuses for requesting ready status information from a memory |
US10108372B2 (en) | 2014-01-27 | 2018-10-23 | Micron Technology, Inc. | Methods and apparatuses for executing a plurality of queued tasks in a memory |
US9454310B2 (en) | 2014-02-14 | 2016-09-27 | Micron Technology, Inc. | Command queuing |
WO2016122514A1 (en) * | 2015-01-29 | 2016-08-04 | Hewlett Packard Enterprise Development Lp | Communications over a serial attached small computer interface (sas) |
CN111181819B (en) * | 2019-12-25 | 2022-03-08 | 交控科技股份有限公司 | Serial port communication method for receiving multi-byte data frame based on linked list structure |
Citations (13)
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US5664145A (en) * | 1991-02-19 | 1997-09-02 | International Business Machines Corporation | Apparatus and method for transferring data in a data storage subsystems wherein a multi-sector data transfer order is executed while a subsequent order is issued |
US6088750A (en) * | 1994-12-13 | 2000-07-11 | International Business Machines Corporation | Method and system for arbitrating between bus masters having diverse bus acquisition protocols |
US6292855B1 (en) * | 1998-12-18 | 2001-09-18 | Lsi Logic Corporation | Method to allow hardware configurable data structures |
US6314477B1 (en) * | 1998-10-30 | 2001-11-06 | Agilent Technologies, Inc. | Performance of fibre channel protocol sequence reassembly using expected frame information and buffer list calculations |
US6408341B1 (en) * | 1996-10-22 | 2002-06-18 | International Business Machines Corporation | Multi-tasking adapter for parallel network applications |
US20030093637A1 (en) * | 2001-11-14 | 2003-05-15 | Shao-Kuang Lee | Command order maintenance scheme for multi-in/multi-out FIFO in multi-threaded I/O links |
US6594712B1 (en) * | 2000-10-20 | 2003-07-15 | Banderacom, Inc. | Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link |
US20060031600A1 (en) * | 2004-08-03 | 2006-02-09 | Ellis Jackson L | Method of processing a context for execution |
US20060064516A1 (en) * | 2004-09-22 | 2006-03-23 | Ellis Jackson L | Instruction removal for context re-evaluation |
US20070088864A1 (en) * | 2005-10-03 | 2007-04-19 | Foster Joseph E | RAID performance using command descriptor block pointer forwarding technique |
US20080016275A1 (en) * | 2003-01-13 | 2008-01-17 | Donia Sebastian | Allocation-unit-based virtual formatting methods and devices employing allocation-unit-based virtual formatting methods |
US20080109617A1 (en) * | 2003-06-12 | 2008-05-08 | Forrer Jr Thomas R | Method and system for simultaneously supporting different block sizes on a single hard drive |
US7986630B1 (en) * | 2004-02-09 | 2011-07-26 | Lsi Corporation | High performance architecture for fiber channel targets and target bridges |
-
2008
- 2008-12-05 US US12/315,704 patent/US8078771B2/en not_active Expired - Fee Related
Patent Citations (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5664145A (en) * | 1991-02-19 | 1997-09-02 | International Business Machines Corporation | Apparatus and method for transferring data in a data storage subsystems wherein a multi-sector data transfer order is executed while a subsequent order is issued |
US6088750A (en) * | 1994-12-13 | 2000-07-11 | International Business Machines Corporation | Method and system for arbitrating between bus masters having diverse bus acquisition protocols |
US6408341B1 (en) * | 1996-10-22 | 2002-06-18 | International Business Machines Corporation | Multi-tasking adapter for parallel network applications |
US6314477B1 (en) * | 1998-10-30 | 2001-11-06 | Agilent Technologies, Inc. | Performance of fibre channel protocol sequence reassembly using expected frame information and buffer list calculations |
US6292855B1 (en) * | 1998-12-18 | 2001-09-18 | Lsi Logic Corporation | Method to allow hardware configurable data structures |
US6594712B1 (en) * | 2000-10-20 | 2003-07-15 | Banderacom, Inc. | Inifiniband channel adapter for performing direct DMA between PCI bus and inifiniband link |
US20030093637A1 (en) * | 2001-11-14 | 2003-05-15 | Shao-Kuang Lee | Command order maintenance scheme for multi-in/multi-out FIFO in multi-threaded I/O links |
US20080016275A1 (en) * | 2003-01-13 | 2008-01-17 | Donia Sebastian | Allocation-unit-based virtual formatting methods and devices employing allocation-unit-based virtual formatting methods |
US20080109617A1 (en) * | 2003-06-12 | 2008-05-08 | Forrer Jr Thomas R | Method and system for simultaneously supporting different block sizes on a single hard drive |
US7986630B1 (en) * | 2004-02-09 | 2011-07-26 | Lsi Corporation | High performance architecture for fiber channel targets and target bridges |
US20060031600A1 (en) * | 2004-08-03 | 2006-02-09 | Ellis Jackson L | Method of processing a context for execution |
US20060064516A1 (en) * | 2004-09-22 | 2006-03-23 | Ellis Jackson L | Instruction removal for context re-evaluation |
US20070088864A1 (en) * | 2005-10-03 | 2007-04-19 | Foster Joseph E | RAID performance using command descriptor block pointer forwarding technique |
Also Published As
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US20100115152A1 (en) | 2010-05-06 |
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