US7856633B1 - LRU cache replacement for a partitioned set associative cache - Google Patents

LRU cache replacement for a partitioned set associative cache Download PDF

Info

Publication number
US7856633B1
US7856633B1 US09534191 US53419100A US7856633B1 US 7856633 B1 US7856633 B1 US 7856633B1 US 09534191 US09534191 US 09534191 US 53419100 A US53419100 A US 53419100A US 7856633 B1 US7856633 B1 US 7856633B1
Authority
US
Grant status
Grant
Patent type
Prior art keywords
cache
thread
trace
processor
instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US09534191
Inventor
Chan W. Lee
Glenn Hinton
Robert Krick
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46Multiprogramming arrangements
    • G06F9/50Allocation of resources, e.g. of the central processing unit [CPU]
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0842Multiuser, multiprocessor or multiprocessing cache systems for multiprocessing or multitasking
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/12Replacement control
    • G06F12/121Replacement control using replacement algorithms
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017Runtime instruction translation, e.g. macros
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3802Instruction prefetching
    • G06F9/3808Instruction prefetching for instruction reuse, e.g. trace cache, branch target cache
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3818Decoding for concurrent execution
    • G06F9/382Pipelined decoding, e.g. using predecoding
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3838Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384Register renaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3851Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for program control, e.g. control units
    • G06F9/06Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution
    • G06F9/3855Reordering, e.g. using a queue, age tags

Abstract

A method of partitioning a memory resource, associated with a multi-threaded processor, includes defining the memory resource to include first and second portions that are dedicated to the first and second threads respectively. A third portion of the memory resource is then designated as being shared between the first and second threads. Upon receipt of an information item, (e.g., a microinstruction associated with the first thread and to be stored in the memory resource), a history of Least Recently Used (LRU) portions is examined to identify a location in either the first or the third portion, but not the second portion, as being a least recently used portion. The second portion is excluded from this examination on account of being dedicated to the second thread. The information item is then stored within a location, within either the first or the third portion, identified as having been least recently used.

Description

FIELD OF THE INVENTION

The present invention relates generally to the field of multi-threaded processors and, more specifically, to a method and apparatus for partitioning a processor resource within a multi-threaded processor.

BACKGROUND OF THE INVENTION

Multi-threaded processor design has recently been considered as an increasingly attractive option for increasing the performance of processors. Multithreading within a processor, inter alia, provides the potential for more effective utilization of various processor resources, and particularly for more effective utilization of the execution logic within a processor. Specifically, by feeding multiple threads to the execution logic of a processor, clock cycles that would otherwise have been idle due to a stall or other delay in the processing of a particular thread may be utilized to service another thread. A stall in the processing of a particular thread may result from a number of occurrences within a processor pipeline. For example, a cache miss or a branch missprediction (i.e., a long-latency operation) for an instruction included within a thread typically results in the processing of the relevant thread stalling. The negative effect of long-latency operations on execution logic efficiencies is exacerbated by the recent increases in execution logic throughput that have outstripped advances in memory access and retrieval rates.

Multi-threaded computer applications are also becoming increasingly common in view of the support provided to such multi-threaded applications by a number of popular operating systems, such as the Windows NT® and Unix operating systems. Multi-threaded computer applications are particularly efficient in the multi-media arena.

Multi-threaded processors may broadly be classified into two categories (i.e., fine or coarse designs) according to the thread interleaving or switching scheme employed within the relevant processor. Fine multi-threaded designs support multiple active threads within a processor and typically interleave two different threads on a cycle-by-cycle basis. Coarse multi-threaded designs typically interleave the instructions of different threads on the occurrence of some long-latency event, such as a cache miss. A coarse multi-threaded design is discussed in Eickemayer, R.; Johnson, R.; et al., “Evaluation of Multithreaded Uniprocessors for Commercial Application Environments”, The 23rd Annual International Symposium on Computer Architecture, pp. 203-212, May 1996. The distinctions between fine and coarse designs are further discussed in Laudon, J; Gupta, A, “Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors”, Multithreaded Computer Architectures: A Summary of the State of the Art, edited by R. A. Iannuci et al., pp. 167-200, Kluwer Academic Publishers, Norwell, Mass., 1994. Laudon further proposes an interleaving scheme that combines the cycle-by-cycle switching of a fine design with the full pipeline interlocks of a coarse design (or blocked scheme). To this end, Laudon proposes a “back off” instruction that makes a specific thread (or context) unavailable for a specific number of cycles. Such a “back off” instruction may be issued upon the occurrence of predetermined events, such as a cache miss. In this way, Laudon avoids having to perform an actual thread switch by simply making one of the threads unavailable.

Where resource sharing is implemented within a multi-threaded processor (i.e., there is limited or no duplication of function units for each thread supported by the processor) it is desirable to effectively share resources between the threads.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not limited in the figures of the accompanying drawings, in which like references indicate similar elements and in which:

FIG. 1 is a block diagram illustrating an exemplary pipeline of a processor within which the present invention may be implemented.

FIG. 2 is a block diagram illustrating an exemplary embodiment of a processor, in the form of a general-purpose multi-threaded microprocessor, within which the present invention may be implemented.

FIG. 3 is a block diagram illustrating selected components of an exemplary multi-threaded microprocessor, and specifically depicts various functional units that provide a buffering (or storage) capability as being logically partitioned to accommodate multiple thread.

FIG. 4 is a block diagram showing further details regarding various components of an exemplary trace delivery engine (TDE).

FIG. 5 is a block diagram illustrating further architectural details of an exemplary trace cache fill buffer.

FIG. 6 is a block diagram illustrating further architectural details of an exemplary trace cache (TC).

FIG. 7 is a block diagram illustrating further structural details of an exemplary trace cache (TC)

FIG. 8 is a block diagram illustrating various inputs and outputs of exemplary thread selection logic.

FIG. 9 is a block diagram illustrating three exemplary components of exemplary thread selection logic in the form of a thread selection state machine, and a counter and comparator for a second thread.

FIG. 10 is a state diagram illustrating exemplary operation of an exemplary thread selection state machine.

FIG. 11 is a block diagram illustrating architectural details of an exemplary embodiment of victim selection logic.

FIG. 12 is a flow chart illustrating an exemplary method of partitioning a memory resource, such as for example a trace cache, within a multi-threaded processor.

FIG. 13 is a flow chart illustrating an exemplary method of partitioning a resource, in the exemplary form of a memory resource, utilizing a Least Recently Used (LRU) history associated with the relevant memory resource.

FIG. 14 is a block diagram illustrating an exemplary LRU history data structure.

FIG. 15 is a block diagram illustrating further details pertaining to inputs to, and outputs from, exemplary victim selection logic.

DETAILED DESCRIPTION

A method and apparatus for partitioning a processor resource within a multi-threaded processor are described. In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be evident, however, to one skilled in the art that the present invention may be practiced without these specific details.

For the purposes of the present specification, the term “event” shall be taken to include any event, internal or external to a processor, that causes a change or interruption to the servicing of an instruction stream (macro- or micro-instruction) within a processor. Accordingly, the term “event” shall be taken to include, but not limited to, branch instructions, exceptions and interrupts that may be generated within or outside the processor.

For the purposes of the present specification, the term “processor” shall be taken to refer to any machine that is capable of executing a sequence of instructions (e.g., macro- or micro-instructions), and shall be taken to include, but not be limited to, general purpose microprocessors, special purpose microprocessors, graphics controllers, audio controllers, multi-media controllers and microcontrollers. Further, the term “processor” shall be taken to refer to, inter alia, Complex Instruction Set Computers (CISC), Reduced Instruction Set Computers (RISC), or Very Long Instruction Word (VLIW) processors.

For the purposes of the present specification, the term “resource” shall be taken to include any unit, component or module of a processor, and shall be taken to include, but not be limited to, a memory resource, a processing resource, a buffering resource, a communications resource or bus, a sequencing resource or a translating resource.

Processor Pipeline

FIG. 1 is a high-level block diagram illustrating an exemplary embodiment of processor pipeline 10 within which the present invention may be implemented. The pipeline 10 includes a number of pipe stages, commencing with a fetch pipe stage 12 at which instructions (e.g., macroinstructions) are retrieved and fed into the pipeline 10. For example, a macroinstruction may be retrieved from a cache memory that is integral with the processor, or closely associated therewith, or may be retrieved from an external main memory via a processor bus. From the fetch pipe stage 12, the macroinstructions are propagated to a decode pipe stage 14, where macroinstructions are translated into microinstructions (also termed “microcode”) suitable for execution within the processor. The microinstructions are then propagated downstream to an allocate pipe stage 16, where processor resources are allocated to the various microinstructions according to availability and need. The microinstructions are then executed at an execute stage 18 before being retired, or “written-back” (e.g., committed to an architectural state) at a retire pipe stage 20.

Microprocessor Architecture

FIG. 2 is a block diagram illustrating an exemplary embodiment of a processor 30, in the form of a general-purpose microprocessor, within which the present invention may be implemented. The processor 30 is described below as being a multi-threaded (MT) processor, and is accordingly able simultaneously to process multiple instruction threads (or contexts). However, a number of the teachings provided below in the specification are not specific to a multi-threaded processor, and may find application in a single threaded processor. In an exemplary embodiment, the processor 30 may comprise an Intel Architecture (IA) microprocessor that is capable of executing the Intel Architecture instruction set. An example of such an Intel Architecture microprocessor is the Pentium Pro® microprocessor or the Pentium III® microprocessor manufactured by Intel Corporation of Santa Clara, Calif.

The processor 30 comprises an in-order front end and an out-of-order back end. The in-order front end includes a bus interface unit 32, which functions as the conduit between the processor 30 and other components (e.g., main memory) of a computer system within which the processor 30 may be employed. To this end, the bus interface unit 32 couples the processor 30 to a processor bus (not shown) via which data and control information may be received at and propagated from the processor 30. The bus interface unit 32 includes Front Side Bus (FSB) logic 34 that controls communications over the processor bus. The bus interface unit 32 further includes a bus queue 36 that provides a buffering function with respect to communications over the processor bus. The bus interface unit 32 is shown to receive bus requests 38 from, and to send snoops or bus returns 40 to, a memory execution unit 42 that provides a local memory capability within the processor 30. The memory execution unit 42 includes a unified data and instruction cache 44, a data Translation Lookaside Buffer (TLB) 46, and memory ordering buffer 48. The memory execution unit 42 receives instruction fetch requests from, and delivers raw instructions (i.e., coded macroinstructions) to, a microinstruction translation engine 54 that translates the received macroinstructions into a corresponding set of microinstructions.

The microinstruction translation engine 54 effectively operates as a trace cache “miss handler” in that it operates to deliver microinstructions to a trace cache 62 in the event of a trace cache miss. To this end, the microinstruction translation engine 54 functions to provide the fetch and decode pipe stages 12 and 14 in the event of a trace cache miss. The microinstruction translation engine 54 is shown to include a next instruction pointer (NIP) 100, an instruction Translation Lookaside Buffer (TLB) 102, a branch predictor 104, an instruction streaming buffer 106, an instruction pre-decoder 108, instruction steering logic 110, an instruction decoder 112, and a branch address calculator 114. The next instruction pointer 100, TLB 102, branch predictor 104 and instruction streaming buffer 106 together constitute a branch prediction unit (BPU). The instruction decoder 112 and branch address calculator 114 together comprise an instruction translate (IX) unit.

The next instruction pointer 100 issues next instruction requests to the unified cache 44. In the exemplary embodiment where the processor 30 comprises a multi-threaded microprocessor capable of processing two threads, the next instruction pointer 100 may include a multiplexer (MUX) (not shown) that selects between instruction pointers associated with either the first or second thread for inclusion within the next instruction request issued therefrom. In one embodiment, the next instruction pointer 100 will interleave next instruction requests for the first and second threads on a cycle-by-cycle (“ping pong”) basis, assuming instructions for both threads have been requested, and instruction streaming buffer 106 resources for both of the threads have not been exhausted. The next instruction pointer requests may be for either 16, 32 or 64-bytes depending on whether the initial request address is in the upper half of a 32-byte or 64-byte aligned line. The next instruction pointer 100 may be redirected by the branch predictor 104, the branch address calculator 114 or by the trace cache 62, with a trace cache miss request being the highest priority redirection request.

When the next instruction pointer 100 makes an instruction request to the unified cache 44, it generates a two-bit “request identifier” that is associated with the instruction request and functions as a “tag” for the relevant instruction request. When returning data responsive to an instruction request, the unified cache 44 returns the following tags or identifiers together with the data:

    • 1. The “request identifier” supplied by the next instruction pointer 100;
    • 2. A three-bit “chunk identifier” that identifies the chunk returned; and
    • 3. A “thread identifier” that identifies the thread to which the returned data belongs.

Next instruction requests are propagated from the next instruction pointer 100 to the instruction TLB 102, which performs an address lookup operation, and delivers a physical address to the unified cache 44. The unified cache 44 delivers a corresponding macroinstruction to the instruction streaming buffer 106. Each next instruction request is also propagated directly from the next instruction pointer 100 to the instruction streaming buffer 106 so as to allow the instruction streaming buffer 106 to identify the thread to which a macroinstruction received from the unified cache 44 belongs. The macroinstructions from both first and second threads are then issued from the instruction streaming buffer 106 to the instruction pre-decoder 108, which performs a number of length calculation and byte marking operations with respect to a received instruction stream (of macroinstructions). Specifically, the instruction pre-decoder 108 generates a series of byte marking vectors that serve, inter alia, to demarcate macroinstructions within the instruction stream propagated to the instruction steering logic 110.

The instruction steering logic 110 then utilizes the byte marking vectors to steer discrete macroinstructions to the instruction decoder 112 for the purposes of decoding. Macroinstructions are also propagated from the instruction steering logic 110 to the branch address calculator 114 for the purposes of branch address calculation. Microinstructions are then delivered from the instruction decoder 112 to the trace delivery engine 60.

During decoding, flow markers are associated with each microinstruction. A flow marker indicates a characteristic of the associated microinstruction and may, for example, indicate the associated microinstruction as being the first or last microinstruction in a microcode sequence representing a macroinstruction. The flow markers include a “beginning of macroinstruction” (BOM) and an “end of macroinstruction” (EOM) flow markers. According to the present invention, the decoder 112 may further decode the microinstructions to have shared resource (multiprocessor) (SHRMP) flow markers and synchronization (SYNC) flow markers associated therewith. Specifically, a shared resource flow marker identifies a microinstruction as a location within a particular thread at which the thread may be interrupted (e.g., re-started or paused) with less negative consequences than elsewhere in the thread. The decoder 112, in an exemplary embodiment of the present invention, is constructed to mark microinstructions that comprise the end or the beginning of a parent macroinstruction with a shared resource flow marker. A synchronization flow market identifies a microinstruction as a location within a particular thread at which the thread may be synchronized with another thread responsive to, for example, a synchronization instruction within the other thread.

From the microinstruction translation engine 54, decoded instructions (i.e., microinstructions) are sent to a trace delivery engine 60. The trace delivery engine 60 includes the trace cache 62, a trace branch predictor (BTB) 64, a microcode sequencer 66 and a microcode (uop) queue 68. The trace delivery engine 60 functions as a microinstruction cache, and is the primary source of microinstructions for a downstream execution unit 70. By providing a microinstruction caching function within the processor pipeline, the trace delivery engine 60, and specifically the trace cache 62, allows translation work done by the microinstruction translation engine 54 to be leveraged to provide an increased microinstruction bandwidth. In one exemplary embodiment, the trace cache 62 may comprise a 256 set, 8 way set associate memory. The term “trace”, in the present exemplary embodiment, may refer to a sequence of microinstructions stored within entries of the trace cache 62, each entry including pointers to preceding and proceeding microinstructions comprising the trace. In this way, the trace cache 62 facilitates high-performance sequencing in that the address of the next entry to be accessed for the purposes of obtaining a subsequent microinstruction is known before a current access is complete. Traces may be viewed as “blocks” of instructions that are distinguished from one another by trace heads, and are terminated upon encountering an indirect branch or by reaching one of many present threshold conditions, such as the number of conditioned branches that may be accommodated in a single trace or the maximum number of total microinstructions that may comprise a trace. The trace cache branch prediction unit 64 provides local branch predictions pertaining to traces within the trace cache 62. The trace cache 62 and the microcode sequencer 66 provide microinstructions to the microcode queue 68, from where the microinstructions are then fed to an out-of-order execution cluster. The microcode sequencer 66 furthermore includes a number of event handlers embodied in microcode, that implement a number of operations within the processor 30 in response to the occurrence of an event such as an exception or an interrupt. The event handlers 67 are invoked by an event detector (not shown) included within a register renamer 74 in the back end of the processor 30.

The processor 30 may be viewed as having an in-order front-end, comprising the bus interface unit 32, the memory execution unit 42, the microinstruction translation engine 54 and the trace delivery engine 60, and an out-of-order back-end that will be described in detail below.

Microinstructions dispatched from the microcode queue 68 are received into an out-of-order cluster 71 comprising a scheduler 72, the register renamer 74, an allocator 76, a reorder buffer 78 and a replay queue 80. The scheduler 72 includes a set of reservation stations, and operates to schedule and dispatch microinstructions for execution by the execution unit 70. The register renamer 74 performs a register renaming function with respect to hidden integer and floating point registers (that may be utilized in place of any of the eight general purpose registers or any of the eight floating-point registers, where a processor 30 executes the Intel Architecture instruction set). The allocator 76 operates to allocate resources of the execution unit 70 and the cluster 71 to microinstructions according to availability and need. In the event that insufficient resources are available to process a microinstruction, the allocator 76 is responsible for asserting a stall signal 82, that is propagated through the trace delivery engine 60 to the microinstruction translation engine 54, as shown at 58. Microinstructions, which have had their source fields adjusted by the register renamer 74, are placed in a reorder buffer 78 in strict program order. When microinstructions within the reorder buffer 78 have completed execution and are ready for retirement, they are then removed from the reorder buffer 162. The replay queue 80 propagates microinstructions that are to be replayed to the execution unit 70.

The execution unit 70 is shown to include a floating-point execution engine 84, an integer execution engine 86, and a level 0 data cache 88. In one exemplary embodiment in which is the processor 30 executes the Intel Architecture instruction set, the floating point execution engine 84 may further execute MMX® instructions.

Multithreading Implementation

In the exemplary embodiment of the processor 30 illustrated in FIG. 2, there may be limited duplication or replication of resources to support a multithreading capability, and it is accordingly necessary to implement some degree of resource sharing between threads. The resource sharing scheme employed, it will be appreciated, is dependent upon the number of threads that the processor is able simultaneously to process. As functional units within a processor typically provide some buffering (or storage) functionality and propagation functionality, the issue of resource sharing may be viewed as comprising (1) storage and (2) processing/propagating bandwidth sharing components. For example, in a processor that supports the simultaneous processing of two threads, buffer resources within various functional units may be statically or logically partitioned between two threads. Similarly, the bandwidth provided by a path for the propagation of information between two functional units must be divided and allocated between the two threads. As these resource sharing issues may arise at a number of locations within a processor pipeline, different resource sharing schemes may be employed at these various locations in accordance with the dictates and characteristics of the specific location. It will be appreciated that different resource sharing schemes may be suited to different locations in view of varying functionalities and operating characteristics.

FIG. 3 is a block diagram illustrating selected components of the processor 30 illustrated in FIG. 2, and depicts various functional units that provide a buffering capability as being logically partitioned to accommodate two threads (i.e., thread 0 and thread 1). The logical partitioning for two threads of the buffering (or storage) and processing facilities of a functional unit may be achieved by allocating a first predetermined set of entries within a buffering resource to a first thread and allocating a second predetermined set of entries within the buffering resource to a second thread. Specifically, this may be achieved by providing two pairs of read and write pointers, a first pair of read and write pointers being associated with a first thread and a second pair of read and write pointers being associated with a second thread. The first set of read and write pointers may be limited to a first predetermined number of entries within a buffering resource, while the second set of read and write pointers may be limited to a second predetermined number of entries within the same buffering resource. In the exemplary embodiment, the instruction streaming buffer 106, the trace cache 62, and an instruction queue 103 are shown to each provide a storage capacity that is logically partitioned between the first and second threads. Each of these units is also shown to include a “shared” capacity that may, according to respective embodiments, be dynamically allocated to either the first or the second thread according to certain criteria.

Trace Delivery Engine

One embodiment of the present invention is described below as being implemented within a trace delivery engine 60, and specifically with respect to a trace cache 62. However, it will be appreciated that the present invention may be applied to a partition any resources within or associated with a processor, and the trace delivery engine 60 is merely provided as an exemplary embodiment.

As alluded to above, the trace delivery engine 60 may function as a primary source of microinstructions during periods of high performance by providing relatively low latency and high bandwidth. Specifically, for a CISC instruction set, such as the Intel Architecture x86 instruction set, decoding of macroinstructions to deliver microinstructions may introduce a performance bottleneck as the variable length of such instructions complicates parallel decoding operations. The trace delivery engine 60 attempts to address this problem to a certain extent by providing for the caching of microinstructions, thus obviating the need for microinstructions executed by the execution unit to be continually decoded.

To provide high-performance sequencing of cached microinstructions, the trace delivery engine 60 creates sequences of entries (or microinstructions) that may conveniently be labeled “traces”. A trace may, in one embodiment, facilitate sequencing in that the address of a subsequent entry can be known during a current access operation, and before a current access operation is complete. In one embodiment, a trace of microinstructions may only be entered through a so-called “head” entry, that includes a linear address that determines a set of subsequent entries of the trace event stored in successive sets, with every entry (except a tail entry) containing a way pointer to a next entry. Similarly, every entry (except a head entry) contains a way pointer to a previous entry.

In one embodiment, the trace delivery engine 60 may implement two modes to either provide input thereto or output therefrom. The trace delivery engine 60 may implement a “build mode” when a miss occurs with respect to a trace cache 62, such a miss being passed on to the microinstruction translation engine 54. In the “build mode”, the microinstruction translation engine 54 will then perform a translation operation on a macroinstruction received either from the unified cache 44, or by performing a memory access operation via the processor bus. The microinstruction translation engine 54 then provides the microinstructions, derived from the macroinstruction(s), to the trace delivery engine 60 which populates the trace cache 62 with these microinstructions.

When a trace cache hit occurs, the trace delivery engine 60 operates in a “stream mode” where a trace, or traces, of microinstructions are fed from the trace delivery engine 60, and specifically the trace cache 62, to the processor back end via the microinstruction queue 68.

FIG. 4 is a block diagram showing further details regarding the various components of the trace delivery engine (TDE) 60 shown in FIG. 2. The next instruction pointer 100, which forms part of the microinstruction translation engine 54, is shown to receive a prediction output 65 from the trace branch prediction unit 64. The next instruction pointer 100 provides an instruction pointer output 67, which may correspond to the prediction output 65, to the trace cache 62.

A trace branch address calculator (TBAC) 120 monitors the output of the microsequencer microinstruction queue 68, and performs a number of functions to provide output to a trace branch information table 122. Specifically, the trace branch address calculator 120 is responsible for bogus branch detection, the validation of branch target and branch prediction operations, for computing a Next Linear Instruction Pointer (NILIP) for each instruction, and for detecting limit violations for each instruction.

The trace branch information table (TBIT) 122 stores information required to update the trace branch prediction unit 64. The table 122 also holds information for events and, in one embodiment, is hard partitioned to support multithreading. Of course, in an alternative embodiment, the table 122 may be dynamically partitioned.

The trace branch information table 122 provides input to a trace branch target buffer (trace BTB) 124 that operates to predict “leave trace” conditions and “end-of-trace” branches. To this end, the buffer 124 may operate to invalidate microinstructions.

When operating in the above-mentioned “build mode”, microinstructions are received into the trace cache 62 via a trace cache fill buffer (TCFB) 125, which is shown in FIG. 4 to provide input into the trace cache 62.

FIG. 5 is a block diagram illustrating further architectural details of the trace cache fill buffer 125. In one embodiment of the buffer 125 includes first and second buffers 134 and 136, each of which is dedicated to a specific thread (e.g., thread 0 and thread 1). Each of the buffers 134 and 136 provides four (4) entries for an associated thread, and outputs microinstructions to a staging buffer 138, from where the microinstructions are communicated to the trace cache 62. The trace cache fill buffer 125 implements a build algorithm in hardware that realizes the “build mode”, and provides microinstruction positioning, and the detection of “end-of-line” and “end-of-trace” conditions.

The trace cache 62 is shown in FIG. 4 to include a data array 128 and an associated tag array 126. The data array 128 provides a storage for, in one embodiment, 12 KB of microinstructions.

FIG. 6 is a block diagram illustrating further architectural details pertinent to the trace cache 62. The thread selection logic 140 implements a thread selection state machine that, in one embodiment, decides on a cycle-by-cycle basis which of multiple threads (e.g., thread 0 or thread 1) is propagated to subsequent pipe stages of a processor 30.

FIG. 6 also illustrates the partitioning of the trace cache 62 into three portions (or sections), namely a first portion 148 dedicated to a first thread, a second portion 152 dedicated to a second thread, and a third portion 150 that is dynamically shared between the first and second threads. In the exemplary embodiment, each of the first and second portions 148 and 152 comprises two (2) ways of the data array 128 (and the associated tag array 126) of the trace cache 62. The third, shared portion 150 constitutes four (4) of the data array 128, and the associated tag array 126. The illustrated partitioning of the trace cache 62 is implemented by victim selection logic 154, which will be described in further detail below.

FIG. 7 is a block diagram illustrating an exemplary structure of the trace cache 62, according to one embodiment. Each of the tag array 126 and the data array 128 are each shown to comprise an eight-way, set associative arrangement, including 256 sets thus providing a total of 2048 entries within each of the tag and data arrays 126 and 128. Each entry 148 within the tag array 126 is show to store, inter alia, tag field information 151, a thread bit 153, a valid bit 155 and a Least Recently Used (LRU) bit 240 for each corresponding entry 156 within the data 128. The thread bit 153 marks the data within the associated entry 156 as belonging, for example, to either a first or a second thread. The valid bit 155 marks the data within the corresponding entry 156 of the data array 128 as being valid or invalid.

One embodiment of the trace cache 62 may also include a further minitag array 127, as illustrated in FIG. 7, that is a subset of the full tag array 126 and that is utilized to perform high-speed tag match operations and for reducing power consumption related to performing a lookup with respect to the trace cache 62. A hit on the minitag array 127 may be regarded as “mutually exclusive”, as will be described in further detail below.

Thread Selection Logic

Dealing first with the thread selection logic 140, which determines, inter alia, the output of the trace cache 62, FIG. 8 is a block diagram illustrating the various inputs and outputs of the thread selection logic 140. The thread selection logic 140 is shown to take inputs from (1) a trace cache build engine 139, located in the microinstruction translation engine interface, (2) the microinstruction queue 68 and (3) trace cache/microsequencer control logic 137. Utilizing these inputs, the thread selection logic 140 attempts to generate an advantageous thread selection (e.g., thread 0 or thread 1) for a particular cycle. Thread selection, in one embodiment, is performed on a cycle-by-cycle basis and attempts to optimize performance while not starving either thread of processor resources.

The output of the thread selection logic 140 is shown to be communicated to the microcode sequencer 66, the trace branch prediction unit 60 and the trace cache 62 to affect thread selection within each of these units.

FIG. 9 is a block diagram illustrating three components of the thread selection logic 140, namely a thread selection state machine 160, a counter and comparator 162 for a first thread (e.g., thread 0) and a further counter and comparator 164 for a second thread (e.g., thread 1).

The thread selection state machine 160 is shown to receive build and mode signals 161, indicating whether the processor is operating in a multithreaded (MT) or a single threaded (ST) mode and if operating in a multithreaded mode, indicating whether or not each thread is in a build mode. The thread selection state machine 160 is also shown to receive respective full inputs 172 and 174 from the counter and comparator units 162 and 164. The full signals 172 and 174 indicate whether a threshold number of microinstructions for a particular thread are within the trace delivery engine 160. In one embodiment, each of the units 162 and 164 allow a total 4×6 microinstruction lines within the trace delivery engine 60. The full signals 172 and 174 are routed to all the units within the trace delivery engine 160, responsive to which such units are responsible for recycling their states. Each of the counter comparator units 162 and 164 is shown to receive a queue deallocation signal 166 from the microcode sequencer 66, a collection of clear, nuke, reset and store signals 168 and valid bits 170 from the trace cache tag array 126.

FIG. 10 is a state diagram illustrating operation of the thread selection state machine 160, illustrated in FIG. 9. When in multithreading mode, the state machine attempts to time-multiplex multiple threads on a cycle-by-cycle basis. When a thread encounters a relatively long stall, the state machine 160 attempts to provide full bandwidth to the thread that has not stalled. When multiple threads (e.g., thread 0 and thread 1) experience long latency stalls, the state machine 160 may, in certain circumstances, require a one-cycle bubble (e.g., if both threads are stalled and the state machine 160 is in “thread 0” state and a “thread 1” stall is removed).

Referring back to FIG. 6, it will be noted that the selection signal 141, outputted from the thread selection logic 140, is not itself regarded as a “valid bit”, but is rather used as a 2-1 MUX selection control to the MUX 142. The MUX 142 operates to select between control signals outputted from a first thread control 144 and a second thread control 146. The outputs of the controls 144 and 146 are dependent upon valid bits being set for the relevant threads. For example, the selection signal 141 may indicate a thread entry for a particular thread (e.g., thread 0) to be outputted from the trace cache 62. However, the valid bit for the relevant entry may be set to 0, indicating an invalid entry.

Victim Selection Logic

The partitioning of the trace cache 62, as illustrated in FIG. 6, may, in one embodiment, be implemented by the victim selection logic 154. The victim selection logic 154 is responsible for identifying the way (in both the tag array 126 and the data array 128) to which a microinstruction is written.

FIG. 11 is a block diagram illustrating architectural details of one embodiment of the victim selection logic 154. The victim selection logic 154 is shown to include minitag victim selection logic 180, valid victim selection logic 182 and Least Recently Used (LRU) victim selection logic 184. A priority multiplexing operation is performed on the outputs of the selection logics 180, 182 and 184 by a priority MUX 186. The priority ordering implemented by the priority MUX 186 is as follows:

1. Minitag victim;

2. Valid victim; and

3. LRU victim.

A multi-threaded latch structure 190 is used to pass the results of the priority MUX to the trace cache 62.

FIG. 12 is a flow chart illustrating an exemplary method 200, according to one embodiment, of partitioning a memory resource, such as for example, the trace cache, within a multi-threaded processor. The operation of the various units of the victim selection logic 154 illustrated in FIG. 11 will be described with reference to the flow chart shown in FIG. 12.

The method 200 commences at block 202 where the minitag victim selection logic 180 performs a minitag victim determination with respect to the minitag array 127. Specifically, the logic 180 attempts to identify a conflict between an existing valid minitag array entry and a current instruction pointer (e.g., the current Linear Instruction Pointer (CLIP)).

At decision box 204, a determination is made as to whether a minitag victim was located at block 202. If so, the method 200 advances to block 212, where relevant trace cache data (e.g., a microinstruction) is written to the identified victim entry within the trace cache 62. As a minitag hit is regarded as being “mutually exclusive”, an identified minitag victim is given the highest priority by the victim selection logic 154.

Following a negative determination at decision box 204, at block 206, a valid victim determination operation is performed by the valid victim selection logic 182. This operation involves simply identifying an invalid entry within the trace cache 62 by examining valid bits 155 stored within the tag array 126 of the trace cache 62. Following a positive determination at decision box 208, the method 200 advances to block 212. On the other hand, following a negative determination (i.e., no invalid entries are identified) at decision box 208, the method 200 proceeds to box 210, where a LRU victim determination operation is performed. Following completion of the operation at block 210, the method 200 again advances to block 212. The method 200 then terminates at step 214.

FIG. 13 is a flow chart illustrating an exemplary method 210, according to one embodiment, of partitioning a resource, in the exemplary form of a memory resource, utilizing a LRU history associated with the relevant memory resource.

FIG. 14 is a block diagram illustrating an exemplary LRU history 240 that may be utilized in the performance of the method 210, the execution of which will be described with reference to FIG. 10.

The method 210 commences at block 222 with the receipt of a microinstruction, and associated tag information, at the victim selection logic 154.

At block 224, a set into which the microinstruction may potentially be written is identified (e.g., by a write pointer).

At block 226, having identified a victim set, the LRU victim selection logic 184 examines the LRU history for the relevant set. FIG. 14 illustrates the LRU history 240, as maintained within the tag array 126 of the trace cache 184, the LRU history 240 containing a LRU history for each set within the data array 128.

At decision box 228, the LRU victim selection logic 184 determines whether the tail entry, indicating a specific way within the set, is available to a relevant thread (e.g., thread 0 or thread 1). As mentioned above, in an exemplary embodiment, ways 0 and 1 may be available exclusively to a first thread (e.g., thread 0), ways 6 and 7 may be available exclusively to a second thread (e.g., thread 1) and ways 2-5 may be dynamically shared multiple threads. Referencing the exemplary LRU history for a set N, way 6 is indicated by the tail entry as being the least recently used way in the relevant set N. Assume, for example, that the microinstruction to be cache belongs to a first thread (e.g., thread 0) in which way 6 would not be available to receive the microinstruction on account of way 6 having been dedicated exclusively to the storage of microinstructions for a second thread (e.g., thread 1).

Returning to FIG. 13, following a negative determination at decisions box 228, the LRU victim selection logic 184 proceeds to examine entries within the LRU history 252 for the relevant set behind the tail entry to identify a way that may receive the microinstruction for the relevant thread. As indicated at block 230, the LRU victim selection logic 184 examines a predetermined set M of tail entries (e.g., the three entries closest to the tail of the LRU history 252 for the set) to locate a way, closest to the tail of the LRU history, that is available to the relevant thread.

In the example provided in FIG. 14, the next-to-last entry within the LRU history for the relevant set identifies way 3 which, under the scheme described above, would be available to receive a microinstruction for a first thread (e.g., thread 0) as way 3 is located in the “shared” portion of the trace cache 62.

FIG. 14 illustrates how the entry for way 3, within the LRU history 252 for the relevant set, is moved to the head of the LRU history 252 on account of this way being designated for storage of the relevant microinstruction.

Returning to the flow chart in FIG. 13, at block 232, the victim entry (i.e., the victim way) within the relevant set that is available to the relevant thread is identified, and the microinstruction written to that way within the set. The method 220 then ends at step 234.

FIG. 15 is a block diagram illustrating further details regarding the inputs to, and output from, the victim selection logic 184. The victim selection logic 184, in one embodiment, comprises discrete logic components that implement the methodology described above. In an alternative embodiment, the victim selection logic 184 may execute code to implement the described methodology. Specifically, the logic is shown to receive a 7-bit pending multi-thread (PENDING_MT) signal 250, a 28-bit least recently used (LRU) signal 252, a second thread status (NT1) signal 254 and a first thread status (MT0) signal 256 as inputs. The signal 250 indicates the way selected to receive a micro-instruction of a current thread or further thread (other than a thread currently being considered) by the selection logic 184 as indicated by the selection logic 184 during a previous victim selection operation, or as determined by further victim selection logic 154 associated with the further thread. The signal 250 is utilized by the LRU victim selection logic 184 to insure that the selection logic 184 does not “doubly select” the same way between two threads, or that multiple LRU victim selection logics 184 do not select the same way between two threads. To this end, the victim selection logic 184 implements discrete logic that prevents it from selecting the same way as indicated by the signal 250.

The signal 250 accordingly, in one embodiment, indicates the way that was previously selected as a victim, while the LRU signal 252 provides the LRU history 252 for the relevant set to the logic 184. The status signals 254 and 256 indicate to the logic 184 which of the threads are “alive” or executing within a processor 30. The logic 184 then outputs a 7-bit selection signal 260 for a relevant set, indicating the way within a relevant set to which the microinstruction should be written for caching purposes within the trace cache 62.

By implementing a pseudo-dynamic partitioning of a resource, such as the trace cache 62, the present invention ensures that a certain predetermined minimum threshold of the capacity of a resource is always reserved and available for a particular thread within a multithreaded processor. Nonetheless, by defining a “shared” portion that is accessible to both threads, the present invention facilitates dynamic redistribution of a resource's capacity between multiple threads according to the requirements of such threads.

Further, the LRU victim selection methodology discussed above enables hits to occur on ways allocated to a further thread, but simply disallows the validation of such a hit, and forces the LRU victim selection algorithm to select a further way, according to an LRU history, that is available to a particular thread.

As mentioned above, the logic for implementing any one of the methodologies discussed above may be implemented as discrete logic within a functional unit, or may comprise a sequence of instructions (e.g., code) that is executed within the processor to implement the method. The sequence of instructions, it will be appreciated, may be stored on any medium from which it is retrievable for execution. Examples of these mediums may be a removable storage medium (e.g., a diskette, CD-ROM) or a memory resource associated with, or included within, a processor (e.g., Random Access Memory (RAM), cache memories or the like). Accordingly, any such medium should be regarded as comprising a “computer-readable” medium and may be included in a processor, or accessible by a processor employed within a computer system.

Thus, a method and apparatus for partitioning a processor resource within a multi-threaded processor have been described. Although the present invention has been described with reference to specific exemplary embodiments, it will be evident that various modifications and changes may be made to these embodiments without departing from the broader spirit scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims (35)

1. A method including:
dedicating a first portion comprising one or more ways of an N way set associative cache exclusively to a first thread;
dedicating a second portion comprising one or more ways of the cache exclusively to a second thread;
dynamically sharing a third portion comprising one or more ways of the cache between the first and second threads; and
performing victim selection in the cache by,
examining a Least Recently Used (LRU) history for a selected set to identify a least recently used way within the cache as a candidate way to store an information item associated with the first thread;
determining whether the candidate way is within the first or the third portion of the cache;
if the candidate way is within the first or the third portion of the cache, then storing the information associated with the first thread in the candidate way; and
if the candidate way is within the second portion of the cache, then identifying a further way within the cache as being the candidate way, wherein the further way is not the candidate way previously identified.
2. The method of claim 1 wherein the dynamic sharing of the third portion of the cache is performed according to resource demands of the respective first and second threads.
3. The method of claim 1 wherein the examining includes examining the LRU history to identify M least recently used ways within the cache, wherein M>1, and wherein the determining is performed for the M candidate ways, and wherein the further way is another of the M candidate ways.
4. The method of claim 1 wherein the identifying of the further way as being the candidate way comprises identifying a second-least recently used way within the cache.
5. The method of claim 1 wherein the examining includes examining entries within the LRU history for the selected set, each entry corresponding to a respective one of the ways, wherein the entries are ordered in a sequence determined by least recent usage of the respective ways.
6. The method of claim 1 wherein the cache is a trace cache memory, and wherein the information item associated with the first thread comprises a microinstruction of the first thread.
7. An N way set associative cache comprising:
a first portion comprising one or more ways dedicated to utilization by a first thread executing within a multi-threaded processor;
a second portion comprising one or more ways dedicated to utilization by a second thread executing within the multi-threaded processor;
a third portion comprising one or more ways shared by the first and second threads; and
selection logic to examine a Least Recently Used (LRU) history for a selected set to identify a least recently used way within the cache as a candidate way within which to store an information item associated with the first thread, to store the information associated the first thread in the candidate way if the candidate way is within the first or third portions of the cache, but if the candidate way is within the second portion of the cache, then to identify a further way within the cache as being the candidate way, wherein the further way is not the candidate way previously identified.
8. The cache of claim 7 wherein the third portion of the cache is shared according to resource demands of the first and second threads.
9. The cache of claim 7 wherein the selection logic is to examine for the selected set the LRU history to identify M least recently used ways within the cache, and wherein M>1.
10. The cache of claim 7 wherein the selection logic identifies as the further way a second-least recently used way within the cache.
11. The cache of claim 7 wherein the selection logic examines entries within the LRU history for the selected set to identify the least recently used way, wherein the entries are ordered in a sequence determined by least recent usage of the ways to which they correspond.
12. The cache of claim 7 wherein the cache is a trace cache memory, and wherein the information item associated with the first thread comprises a microinstruction of the first thread.
13. A method including:
configuring an N way set associative cache, associated with a multi-threaded processor, to include first and second portions comprising one or more ways dedicated to the first and second threads respectively and a third portion comprising one or more ways shared between the first and second threads;
for an information item associated with the first thread, examining for a selected set a history of least recently used ways until one is found that is within one of the first and third portions; and
storing the information item within the found way.
14. The method of claim 13 wherein the sharing of the third portion of the cache is performed according to resource demands of the respective first and second threads.
15. The method of claim 13, wherein the examining is performed on M ways of the history of least recently used ways, and where M>1.
16. The method of claim 13 wherein the examination of the history of least recently used ways includes examining entries within the history, each entry corresponding to a respective one of the ways, wherein the entries are ordered in a sequence determined by least recent usage of the respective ways.
17. The method of claim 13 wherein the cache is a trace cache memory, and wherein the information item associated with the first thread comprises a microinstruction of the first thread.
18. A computer storage storing a sequence of instructions that, when executed within a processor, causes the processor to perform the steps of:
dedicating a first portion comprising one or more ways of an N way set associative cache exclusively to a first thread;
dedicating a second portion comprising one or more ways of the cache exclusively to a second thread;
dynamically sharing a third portion comprising one or more ways of the cache between the first and second threads; and
performing victim selection in the cache by,
examining a Least Recently Used (LRU) history for a selected set to identify a least recently used way within the cache as a candidate way to store an information item associated with the first thread;
determining whether the candidate way is within the first or the third portion of the cache;
if the candidate way is within the first or the third portion of the cache, then storing the information associated with the first thread in the candidate way; and
if the candidate way is within the second portion of the cache, then identifying a further way within the cache as being the candidate way, wherein the further way is not the candidate way previously identified.
19. The computer storage of claim 18 wherein the dynamic sharing of the third portion of the cache is performed according to resource demands of the respective first and second threads.
20. The computer storage of claim 18 wherein the examining includes examining the LRU history to identify M least recently used ways within the cache, wherein M>1, and wherein the determining is performed for the M candidate ways, and wherein the further way is another of the M candidate ways.
21. The computer storage of claim 18 wherein the identifying of the further way as being the candidate way comprises identifying a second-least recently used way within the cache.
22. The computer storage of claim 18 wherein the examining includes examining entries within the LRU history for the selected set, each entry corresponding to a respective one of the ways, wherein the entries are ordered in a sequence determined by least recent usage of the respective ways.
23. The computer storage of claim 18 wherein the cache is a trace cache memory, and wherein the information item associated with the first thread comprises a microinstruction of the first thread.
24. A method comprising:
detecting misses in an N way set associative cache of a processor;
performing victim selection responsive to each of the misses in a manner that partitions the capacity of the cache to make a first and second portion each comprising one or more ways available for replacement respectively only by each of a first and second instruction threads while at the same time that defines a shared portion comprising one or more ways available to both the first and second instruction threads, wherein the performing victim selection responsive to each of the misses includes examining entries of a least recently used history until an available one of said ways within a selected set is found.
25. The method of claim 24, further comprising:
performing fine multithreading of the first and second threads in the processor.
26. The method of claim 24, wherein the examining includes examining M of the entries corresponding to the M least recently used of the ways, and wherein M>1.
27. The method of claim 24 wherein the shared portion of the cache is shared according to resource demands of the respective first and second threads.
28. The method of claim 24 wherein each of the entries corresponds to a respective one of the ways, and wherein the entries are ordered in a sequence determined by least recent usage of the respective ways.
29. The method of claim 24 wherein the cache is a trace cache memory to store microinstructions of the first and second instruction threads.
30. An apparatus comprising:
a processor including,
an N way set associative cache having a storage capacity, and
victim selection logic including logic to partition the storage capacity of the cache having a dedicated portion comprising one or more ways for each of a first and second instruction threads while at the same time having a shared portion comprising one or more ways accessible by both the first and second threads, wherein the victim selection logic responsive to each of the misses in the cache to examine entries of a least recently used history for a selected set of the cache until one of said ways is found that is available to the instruction thread causing that cache miss.
31. The apparatus of claim 30, wherein the cache is a trace cache and the processor is capable of fine simultaneous multithreading.
32. The apparatus of claim 30, wherein the cache is a trace cache, wherein the trace cache is to store microinstructions of the first and second threads.
33. The apparatus of claim 30 wherein the entries are ordered in a sequence determined by least recent usage of the ways to which they correspond.
34. The apparatus of claim 30 wherein the victim selection logic responsive to each of the misses in the cache to examine M entries corresponding to M least recently used ways within the cache, and wherein M>1.
35. The apparatus of claim 30 wherein the shared portion of the cache is shared according to resource demands of the respective first and second threads.
US09534191 2000-03-24 2000-03-24 LRU cache replacement for a partitioned set associative cache Active US7856633B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09534191 US7856633B1 (en) 2000-03-24 2000-03-24 LRU cache replacement for a partitioned set associative cache

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US09534191 US7856633B1 (en) 2000-03-24 2000-03-24 LRU cache replacement for a partitioned set associative cache
GB0224460A GB2377529B (en) 2000-03-24 2001-01-16 Method and apparatus for partitioning a resource between multiple threads within a multi-threaded processor
PCT/US2001/001577 WO2001077820A3 (en) 2000-03-24 2001-01-16 Method and apparatus for partitioning a resource between multiple threads within a multi-threaded processor
DE2001195962 DE10195962T1 (en) 2000-03-24 2001-01-16 Method and apparatus for dividing a resource between multiple threads in a multithreaded processor
CN 01809728 CN1429361B (en) 2000-03-24 2001-01-16 Method and device for partitioning resource between multiple threads within multi-threaded processor

Publications (1)

Publication Number Publication Date
US7856633B1 true US7856633B1 (en) 2010-12-21

Family

ID=24129052

Family Applications (1)

Application Number Title Priority Date Filing Date
US09534191 Active US7856633B1 (en) 2000-03-24 2000-03-24 LRU cache replacement for a partitioned set associative cache

Country Status (5)

Country Link
US (1) US7856633B1 (en)
CN (1) CN1429361B (en)
DE (1) DE10195962T1 (en)
GB (1) GB2377529B (en)
WO (1) WO2001077820A3 (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110022773A1 (en) * 2009-07-27 2011-01-27 International Business Machines Corporation Fine Grained Cache Allocation
US20110055827A1 (en) * 2009-08-25 2011-03-03 International Business Machines Corporation Cache Partitioning in Virtualized Environments
US20120226861A1 (en) * 2011-03-03 2012-09-06 Hitachi, Ltd. Storage controller and method of controlling storage controller
US20130097387A1 (en) * 2011-10-14 2013-04-18 The Board Of Trustees Of The Leland Stanford Junior University Memory-based apparatus and method
CN104461928A (en) * 2013-09-16 2015-03-25 华为技术有限公司 Method and device for dividing caches
US20150100763A1 (en) * 2013-10-09 2015-04-09 Arm Limited Decoding a complex program instruction corresponding to multiple micro-operations

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7380085B2 (en) 2001-11-14 2008-05-27 Intel Corporation Memory adapted to provide dedicated and or shared memory to multiple processors and method therefor
US7127561B2 (en) 2001-12-31 2006-10-24 Intel Corporation Coherency techniques for suspending execution of a thread until a specified memory access occurs
US7363474B2 (en) 2001-12-31 2008-04-22 Intel Corporation Method and apparatus for suspending execution of a thread until a specified memory access occurs
US20030229740A1 (en) * 2002-06-10 2003-12-11 Maly John Warren Accessing resources in a microprocessor having resources of varying scope
US8024735B2 (en) 2002-06-14 2011-09-20 Intel Corporation Method and apparatus for ensuring fairness and forward progress when executing multiple threads of execution
US7529914B2 (en) * 2004-06-30 2009-05-05 Intel Corporation Method and apparatus for speculative execution of uncontended lock instructions
US8195922B2 (en) 2005-03-18 2012-06-05 Marvell World Trade, Ltd. System for dynamically allocating processing time to multiple threads
GB2427045B (en) 2005-06-06 2007-11-21 Transitive Ltd Method and apparatus for converting program code with access coordination for a shared resource
CN100487660C (en) 2007-05-28 2009-05-13 中兴通讯股份有限公司 Multithreading processor dynamic EMS memory management system and method
US8458447B2 (en) * 2011-06-17 2013-06-04 Freescale Semiconductor, Inc. Branch target buffer addressing in a data processor

Citations (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771138A (en) 1971-08-31 1973-11-06 Ibm Apparatus and method for serializing instructions from two independent instruction streams
EP0346003A2 (en) 1988-06-07 1989-12-13 Fujitsu Limited Multiprocessor control system
EP0352935A2 (en) 1988-07-27 1990-01-31 International Computers Limited Pipelined processor
US5167024A (en) 1989-09-08 1992-11-24 Apple Computer, Inc. Power management for a laptop computer with slow and sleep modes
US5228131A (en) 1988-02-24 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Data processor with selectively enabled and disabled branch prediction operation
US5325526A (en) 1992-05-12 1994-06-28 Intel Corporation Task scheduling in a multicomputer system
US5337285A (en) 1993-05-21 1994-08-09 Rambus, Inc. Method and apparatus for power control in devices
US5357617A (en) 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5361337A (en) 1989-08-03 1994-11-01 Sun Microsystems, Inc. Method and apparatus for rapidly switching processes in a computer system
US5386561A (en) 1992-03-31 1995-01-31 International Business Machines Corporation Method of integrated system load control through dynamic time-slicing in a virtual storage environment
RU2029359C1 (en) 1991-12-29 1995-02-20 Вычислительный центр коллективного пользования РАН Data processing device
US5392437A (en) 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5404469A (en) 1992-02-25 1995-04-04 Industrial Technology Research Institute Multi-threaded microprocessor architecture utilizing static interleaving
US5428810A (en) 1991-03-15 1995-06-27 Hewlett-Packard Company Allocation of resources of a pipelined processor by clock phase for parallel execution of dependent processes
US5430850A (en) 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads
US5454117A (en) 1993-08-25 1995-09-26 Nexgen, Inc. Configurable branch prediction for a processor performing speculative execution
US5473572A (en) 1993-02-16 1995-12-05 Chips And Technologies, Inc. Power saving system for a memory controller
US5495617A (en) 1984-08-10 1996-02-27 Nec Corporation On demand powering of necesssary portions of execution unit by decoding instruction word field indications which unit is required for execution
US5499349A (en) 1989-05-26 1996-03-12 Massachusetts Institute Of Technology Pipelined processor with fork, join, and start instructions using tokens to indicate the next instruction for each of multiple threads of execution
US5511198A (en) 1993-04-28 1996-04-23 Fujitsu Limited Optimizing compiler for shortening execution time of object program
US5524263A (en) 1994-02-25 1996-06-04 Intel Corporation Method and apparatus for partial and full stall handling in allocation
US5528513A (en) 1993-11-04 1996-06-18 Digital Equipment Corp. Scheduling and admission control policy for a continuous media server
EP0725335A1 (en) 1995-02-03 1996-08-07 International Business Machines Corporation Method and system for processing instruction threads
US5553291A (en) 1992-09-16 1996-09-03 Hitachi, Ltd. Virtual machine control method and virtual machine system
EP0747816A2 (en) 1995-06-07 1996-12-11 International Business Machines Corporation Method and system for high performance multithread operation in a data processing system
US5586332A (en) 1993-03-24 1996-12-17 Intel Corporation Power management for low power processors through the use of auto clock-throttling
US5590061A (en) 1994-05-12 1996-12-31 Apple Computer, Inc. Method and apparatus for thermal management in a computer system
EP0768608A2 (en) 1995-10-13 1997-04-16 Sun Microsystems, Inc. Maximal concurrent lookup cache for computing systems having a multi-threaded environment
US5623471A (en) 1994-05-26 1997-04-22 International Business Machines Corporation Adaptive backup for storage library
US5630130A (en) 1992-12-23 1997-05-13 Centre Electronique Horloger S.A. Multi-tasking low-power controller having multiple program counters
US5632038A (en) 1994-02-22 1997-05-20 Dell Usa, L.P. Secondary cache system for portable computer
GB2311880A (en) 1996-04-03 1997-10-08 Advanced Risc Mach Ltd Partitioned cache memory
US5701448A (en) 1995-12-15 1997-12-23 Cyrix Corporation Detecting segment limit violations for branch target when the branch unit does not supply the linear address
EP0827071A2 (en) 1996-08-27 1998-03-04 Matsushita Electric Industrial Co., Ltd. Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream
US5740417A (en) 1995-12-05 1998-04-14 Motorola, Inc. Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states
US5742782A (en) 1994-04-15 1998-04-21 Hitachi, Ltd. Processing apparatus for executing a plurality of VLIW threads in parallel
RU2110089C1 (en) 1995-12-22 1998-04-27 Бурцев Всеволод Сергеевич Computer system
US5761522A (en) 1995-05-24 1998-06-02 Fuji Xerox Co., Ltd. Program control system programmable to selectively execute a plurality of programs
US5787297A (en) 1992-03-31 1998-07-28 Seiko Epson Corporation Selective power-down for high performance CPU/system
EP0856797A1 (en) 1997-01-30 1998-08-05 Sgs-Thomson Microelectronics Ltd. A cache system for concurrent processes
US5799180A (en) 1995-10-31 1998-08-25 Texas Instruments Incorporated Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken
EP0863462A2 (en) 1997-03-04 1998-09-09 Matsushita Electric Industrial Co., Ltd. Processor capable of efficiently executing many asynchronous event tasks
US5809271A (en) 1994-03-01 1998-09-15 Intel Corporation Method and apparatus for changing flow of control in a processor
US5809522A (en) 1995-12-18 1998-09-15 Advanced Micro Devices, Inc. Microprocessor system with process identification tag entries to reduce cache flushing after a context switch
EP0864960A1 (en) 1997-03-14 1998-09-16 Nokia Mobile Phones Ltd. Power saving an a data processing circuit
US5854922A (en) 1997-01-16 1998-12-29 Ford Motor Company Micro-sequencer apparatus and method of combination state machine and instruction memory
US5872965A (en) 1997-06-30 1999-02-16 Sun Microsystems, Inc. System and method for performing multiway branches using a visual instruction set
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
US5880979A (en) 1995-12-21 1999-03-09 Intel Corporation System for providing the absolute difference of unsigned values
JPH1166849A (en) 1997-08-13 1999-03-09 Toshiba Corp Semiconductor storage device
US5892959A (en) 1990-06-01 1999-04-06 Vadem Computer activity monitor providing idle thread and other event sensitive clock and power control
WO1999021088A1 (en) 1997-10-23 1999-04-29 International Business Machines Corporation An apparatus and method to guarantee forward progress in a multithreaded processor
WO1999021082A1 (en) 1997-10-23 1999-04-29 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
WO1999021081A1 (en) 1997-10-23 1999-04-29 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US5900025A (en) 1995-09-12 1999-05-04 Zsp Corporation Processor having a hierarchical control register file and methods for operating the same
US5968160A (en) 1990-09-07 1999-10-19 Hitachi, Ltd. Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
US5968167A (en) 1996-04-04 1999-10-19 Videologic Limited Multi-threaded data processing management system
US5983339A (en) 1995-08-21 1999-11-09 International Business Machines Corporation Power down system and method for pipelined logic functions
US5996085A (en) 1997-07-15 1999-11-30 International Business Machines Corporation Concurrent execution of machine context synchronization operations and non-interruptible instructions
US5996083A (en) 1995-08-11 1999-11-30 Hewlett-Packard Company Microprocessor having software controllable power consumption
US5999963A (en) * 1997-11-07 1999-12-07 Lucent Technologies, Inc. Move-to-rear list scheduling
US5999932A (en) 1998-01-13 1999-12-07 Bright Light Technologies, Inc. System and method for filtering unsolicited electronic mail messages using data matching and heuristic processing
EP0962856A2 (en) 1998-06-05 1999-12-08 Texas Instruments Incorporated A dual-mode VLIW architecture with software-controlled parallelism
US6009454A (en) 1994-09-30 1999-12-28 Allen-Bradley Company, Llc Multi-tasking operation system for industrial controller
US6035374A (en) 1997-06-25 2000-03-07 Sun Microsystems, Inc. Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
US6052709A (en) 1997-12-23 2000-04-18 Bright Light Technologies, Inc. Apparatus and method for controlling delivery of unsolicited electronic mail
US6052708A (en) 1997-03-11 2000-04-18 International Business Machines Corporation Performance monitoring of thread switch events in a multithreaded processor
US6085218A (en) 1991-09-26 2000-07-04 International Business Machines Corporation Monitoring processor execution cycles to prevent task overrun in multi-task, hard, real-time system
US6085215A (en) 1993-03-26 2000-07-04 Cabletron Systems, Inc. Scheduling mechanism using predetermined limited execution time processing threads in a communication network
US6088788A (en) 1996-12-27 2000-07-11 International Business Machines Corporation Background completion of instruction and associated fetch request in a multithread processor
US6092175A (en) 1998-04-02 2000-07-18 University Of Washington Shared register storage mechanisms for multithreaded computer systems with out-of-order execution
US6115709A (en) 1998-09-18 2000-09-05 Tacit Knowledge Systems, Inc. Method and system for constructing a knowledge profile of a user having unrestricted and restricted access portions according to respective levels of confidence of content of the portions
US6161167A (en) * 1997-06-27 2000-12-12 Advanced Micro Devices, Inc. Fully associate cache employing LRU groups for cache replacement and mechanism for selecting an LRU group
US6182210B1 (en) 1997-12-16 2001-01-30 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6205519B1 (en) * 1998-05-27 2001-03-20 Hewlett Packard Company Cache management for a multi-threaded processor
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
US6233599B1 (en) 1997-07-10 2001-05-15 International Business Machines Corporation Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
US20010004755A1 (en) 1997-04-03 2001-06-21 Henry M Levy Mechanism for freeing registers on processors that perform dynamic out-of-order execution of instructions using renaming registers
US6256775B1 (en) 1997-12-11 2001-07-03 International Business Machines Corporation Facilities for detailed software performance analysis in a multithreaded processor
US6272517B1 (en) * 1997-10-31 2001-08-07 Sun Microsystems, Incorporated Method and apparatus for sharing a time quantum
US6289461B1 (en) 1998-06-09 2001-09-11 Placeware, Inc. Bi-directional process-to-process byte stream protocol
US6308279B1 (en) 1998-05-22 2001-10-23 Intel Corporation Method and apparatus for power mode transition in a multi-thread processor
US6314530B1 (en) 1997-04-08 2001-11-06 Advanced Micro Devices, Inc. Processor having a trace access instruction to access on-chip trace memory
US6330584B1 (en) 1998-04-03 2001-12-11 Mmc Networks, Inc. Systems and methods for multi-tasking, resource sharing and execution of computer instructions
US20020013892A1 (en) 1998-05-26 2002-01-31 Frank J. Gorishek Emulation coprocessor
US6353844B1 (en) * 1996-12-23 2002-03-05 Silicon Graphics, Inc. Guaranteeing completion times for batch jobs without static partitioning
US6357016B1 (en) 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
US6366945B1 (en) * 1997-05-23 2002-04-02 Ibm Corporation Flexible dynamic partitioning of resources in a cluster computing environment
US6374286B1 (en) * 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US6381682B2 (en) * 1998-06-10 2002-04-30 Compaq Information Technologies Group, L.P. Method and apparatus for dynamically sharing memory in a multiprocessor system
US6389449B1 (en) 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US20020062435A1 (en) 1998-12-16 2002-05-23 Mario D. Nemirovsky Prioritized instruction scheduling for multi-streaming processors
US20020091914A1 (en) 1996-11-13 2002-07-11 Merchant Amit A. Multi-threading techniques for a processor utilizing a replay queue
US6430593B1 (en) 1998-03-10 2002-08-06 Motorola Inc. Method, device and article of manufacture for efficient task scheduling in a multi-tasking preemptive priority-based real-time operating system
US20020116600A1 (en) 1999-12-09 2002-08-22 Smith Lawrence O. Method and apparatus for processing events in a multithreaded processor
US6442585B1 (en) * 1997-11-26 2002-08-27 Compaq Computer Corporation Method for scheduling contexts based on statistics of memory system interactions in a computer system
US6493800B1 (en) * 1999-03-31 2002-12-10 International Business Machines Corporation Method and system for dynamically partitioning a shared cache
US20030009648A1 (en) 1999-07-01 2003-01-09 International Business Machines Corporation Apparatus for supporting a logically partitioned computer system
US20030023835A1 (en) 1999-04-29 2003-01-30 Stavros Kalafatis Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction
US6542921B1 (en) * 1999-07-08 2003-04-01 Intel Corporation Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor
US6625635B1 (en) 1998-11-02 2003-09-23 International Business Machines Corporation Deterministic and preemptive thread scheduling and its use in debugging multithreaded applications
US6789181B1 (en) 1999-01-28 2004-09-07 Ati International, Srl Safety net paradigm for managing two computer execution modes
US6889319B1 (en) 1999-12-09 2005-05-03 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor

Patent Citations (111)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3771138A (en) 1971-08-31 1973-11-06 Ibm Apparatus and method for serializing instructions from two independent instruction streams
US5495617A (en) 1984-08-10 1996-02-27 Nec Corporation On demand powering of necesssary portions of execution unit by decoding instruction word field indications which unit is required for execution
US5228131A (en) 1988-02-24 1993-07-13 Mitsubishi Denki Kabushiki Kaisha Data processor with selectively enabled and disabled branch prediction operation
EP0346003A2 (en) 1988-06-07 1989-12-13 Fujitsu Limited Multiprocessor control system
EP0352935A2 (en) 1988-07-27 1990-01-31 International Computers Limited Pipelined processor
US5499349A (en) 1989-05-26 1996-03-12 Massachusetts Institute Of Technology Pipelined processor with fork, join, and start instructions using tokens to indicate the next instruction for each of multiple threads of execution
US5361337A (en) 1989-08-03 1994-11-01 Sun Microsystems, Inc. Method and apparatus for rapidly switching processes in a computer system
US5167024A (en) 1989-09-08 1992-11-24 Apple Computer, Inc. Power management for a laptop computer with slow and sleep modes
US5892959A (en) 1990-06-01 1999-04-06 Vadem Computer activity monitor providing idle thread and other event sensitive clock and power control
US5968160A (en) 1990-09-07 1999-10-19 Hitachi, Ltd. Method and apparatus for processing data in multiple modes in accordance with parallelism of program by using cache memory
US5428810A (en) 1991-03-15 1995-06-27 Hewlett-Packard Company Allocation of resources of a pipelined processor by clock phase for parallel execution of dependent processes
US5430850A (en) 1991-07-22 1995-07-04 Massachusetts Institute Of Technology Data processing system with synchronization coprocessor for multiple threads
US6085218A (en) 1991-09-26 2000-07-04 International Business Machines Corporation Monitoring processor execution cycles to prevent task overrun in multi-task, hard, real-time system
US5357617A (en) 1991-11-22 1994-10-18 International Business Machines Corporation Method and apparatus for substantially concurrent multiple instruction thread processing by a single pipeline processor
US5875464A (en) * 1991-12-10 1999-02-23 International Business Machines Corporation Computer system with private and shared partitions in cache
RU2029359C1 (en) 1991-12-29 1995-02-20 Вычислительный центр коллективного пользования РАН Data processing device
US5404469A (en) 1992-02-25 1995-04-04 Industrial Technology Research Institute Multi-threaded microprocessor architecture utilizing static interleaving
US5787297A (en) 1992-03-31 1998-07-28 Seiko Epson Corporation Selective power-down for high performance CPU/system
US5386561A (en) 1992-03-31 1995-01-31 International Business Machines Corporation Method of integrated system load control through dynamic time-slicing in a virtual storage environment
US5325526A (en) 1992-05-12 1994-06-28 Intel Corporation Task scheduling in a multicomputer system
US5553291A (en) 1992-09-16 1996-09-03 Hitachi, Ltd. Virtual machine control method and virtual machine system
US5392437A (en) 1992-11-06 1995-02-21 Intel Corporation Method and apparatus for independently stopping and restarting functional units
US5630130A (en) 1992-12-23 1997-05-13 Centre Electronique Horloger S.A. Multi-tasking low-power controller having multiple program counters
US5473572A (en) 1993-02-16 1995-12-05 Chips And Technologies, Inc. Power saving system for a memory controller
US5586332A (en) 1993-03-24 1996-12-17 Intel Corporation Power management for low power processors through the use of auto clock-throttling
US6085215A (en) 1993-03-26 2000-07-04 Cabletron Systems, Inc. Scheduling mechanism using predetermined limited execution time processing threads in a communication network
US5511198A (en) 1993-04-28 1996-04-23 Fujitsu Limited Optimizing compiler for shortening execution time of object program
US5337285A (en) 1993-05-21 1994-08-09 Rambus, Inc. Method and apparatus for power control in devices
US5454117A (en) 1993-08-25 1995-09-26 Nexgen, Inc. Configurable branch prediction for a processor performing speculative execution
US5528513A (en) 1993-11-04 1996-06-18 Digital Equipment Corp. Scheduling and admission control policy for a continuous media server
US5632038A (en) 1994-02-22 1997-05-20 Dell Usa, L.P. Secondary cache system for portable computer
US5524263A (en) 1994-02-25 1996-06-04 Intel Corporation Method and apparatus for partial and full stall handling in allocation
US5809271A (en) 1994-03-01 1998-09-15 Intel Corporation Method and apparatus for changing flow of control in a processor
US5742782A (en) 1994-04-15 1998-04-21 Hitachi, Ltd. Processing apparatus for executing a plurality of VLIW threads in parallel
US5590061A (en) 1994-05-12 1996-12-31 Apple Computer, Inc. Method and apparatus for thermal management in a computer system
US5623471A (en) 1994-05-26 1997-04-22 International Business Machines Corporation Adaptive backup for storage library
US6009454A (en) 1994-09-30 1999-12-28 Allen-Bradley Company, Llc Multi-tasking operation system for industrial controller
EP0725335A1 (en) 1995-02-03 1996-08-07 International Business Machines Corporation Method and system for processing instruction threads
US5761522A (en) 1995-05-24 1998-06-02 Fuji Xerox Co., Ltd. Program control system programmable to selectively execute a plurality of programs
EP0747816A2 (en) 1995-06-07 1996-12-11 International Business Machines Corporation Method and system for high performance multithread operation in a data processing system
US5996083A (en) 1995-08-11 1999-11-30 Hewlett-Packard Company Microprocessor having software controllable power consumption
US5983339A (en) 1995-08-21 1999-11-09 International Business Machines Corporation Power down system and method for pipelined logic functions
US5900025A (en) 1995-09-12 1999-05-04 Zsp Corporation Processor having a hierarchical control register file and methods for operating the same
EP0768608A2 (en) 1995-10-13 1997-04-16 Sun Microsystems, Inc. Maximal concurrent lookup cache for computing systems having a multi-threaded environment
US5799180A (en) 1995-10-31 1998-08-25 Texas Instruments Incorporated Microprocessor circuits, systems, and methods passing intermediate instructions between a short forward conditional branch instruction and target instruction through pipeline, then suppressing results if branch taken
US5740417A (en) 1995-12-05 1998-04-14 Motorola, Inc. Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states
US5701448A (en) 1995-12-15 1997-12-23 Cyrix Corporation Detecting segment limit violations for branch target when the branch unit does not supply the linear address
US5809522A (en) 1995-12-18 1998-09-15 Advanced Micro Devices, Inc. Microprocessor system with process identification tag entries to reduce cache flushing after a context switch
US5880979A (en) 1995-12-21 1999-03-09 Intel Corporation System for providing the absolute difference of unsigned values
RU2110089C1 (en) 1995-12-22 1998-04-27 Бурцев Всеволод Сергеевич Computer system
GB2311880A (en) 1996-04-03 1997-10-08 Advanced Risc Mach Ltd Partitioned cache memory
US5968167A (en) 1996-04-04 1999-10-19 Videologic Limited Multi-threaded data processing management system
US6105127A (en) 1996-08-27 2000-08-15 Matsushita Electric Industrial Co., Ltd. Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream
EP0827071A2 (en) 1996-08-27 1998-03-04 Matsushita Electric Industrial Co., Ltd. Multithreaded processor for processing multiple instruction streams independently of each other by flexibly controlling throughput in each instruction stream
US20020091914A1 (en) 1996-11-13 2002-07-11 Merchant Amit A. Multi-threading techniques for a processor utilizing a replay queue
US6353844B1 (en) * 1996-12-23 2002-03-05 Silicon Graphics, Inc. Guaranteeing completion times for batch jobs without static partitioning
US6088788A (en) 1996-12-27 2000-07-11 International Business Machines Corporation Background completion of instruction and associated fetch request in a multithread processor
US5854922A (en) 1997-01-16 1998-12-29 Ford Motor Company Micro-sequencer apparatus and method of combination state machine and instruction memory
US6295580B1 (en) * 1997-01-30 2001-09-25 Sgs-Thomson Microelectronics Limited Cache system for concurrent processes
EP0856797A1 (en) 1997-01-30 1998-08-05 Sgs-Thomson Microelectronics Ltd. A cache system for concurrent processes
EP0863462A2 (en) 1997-03-04 1998-09-09 Matsushita Electric Industrial Co., Ltd. Processor capable of efficiently executing many asynchronous event tasks
US6470376B1 (en) 1997-03-04 2002-10-22 Matsushita Electric Industrial Co., Ltd Processor capable of efficiently executing many asynchronous event tasks
US6052708A (en) 1997-03-11 2000-04-18 International Business Machines Corporation Performance monitoring of thread switch events in a multithreaded processor
EP0864960A1 (en) 1997-03-14 1998-09-16 Nokia Mobile Phones Ltd. Power saving an a data processing circuit
US20010004755A1 (en) 1997-04-03 2001-06-21 Henry M Levy Mechanism for freeing registers on processors that perform dynamic out-of-order execution of instructions using renaming registers
US6314530B1 (en) 1997-04-08 2001-11-06 Advanced Micro Devices, Inc. Processor having a trace access instruction to access on-chip trace memory
US6366945B1 (en) * 1997-05-23 2002-04-02 Ibm Corporation Flexible dynamic partitioning of resources in a cluster computing environment
US6035374A (en) 1997-06-25 2000-03-07 Sun Microsystems, Inc. Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
US6161167A (en) * 1997-06-27 2000-12-12 Advanced Micro Devices, Inc. Fully associate cache employing LRU groups for cache replacement and mechanism for selecting an LRU group
US5872965A (en) 1997-06-30 1999-02-16 Sun Microsystems, Inc. System and method for performing multiway branches using a visual instruction set
US6233599B1 (en) 1997-07-10 2001-05-15 International Business Machines Corporation Apparatus and method for retrofitting multi-threaded operations on a computer by partitioning and overlapping registers
US5996085A (en) 1997-07-15 1999-11-30 International Business Machines Corporation Concurrent execution of machine context synchronization operations and non-interruptible instructions
JPH1166849A (en) 1997-08-13 1999-03-09 Toshiba Corp Semiconductor storage device
US6697935B1 (en) 1997-10-23 2004-02-24 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
WO1999021088A1 (en) 1997-10-23 1999-04-29 International Business Machines Corporation An apparatus and method to guarantee forward progress in a multithreaded processor
WO1999021081A1 (en) 1997-10-23 1999-04-29 International Business Machines Corporation Method and apparatus for selecting thread switch events in a multithreaded processor
US6212544B1 (en) 1997-10-23 2001-04-03 International Business Machines Corporation Altering thread priorities in a multithreaded processor
WO1999021082A1 (en) 1997-10-23 1999-04-29 International Business Machines Corporation Method and apparatus to force a thread switch in a multithreaded processor
US6272517B1 (en) * 1997-10-31 2001-08-07 Sun Microsystems, Incorporated Method and apparatus for sharing a time quantum
US5999963A (en) * 1997-11-07 1999-12-07 Lucent Technologies, Inc. Move-to-rear list scheduling
US6442585B1 (en) * 1997-11-26 2002-08-27 Compaq Computer Corporation Method for scheduling contexts based on statistics of memory system interactions in a computer system
US6256775B1 (en) 1997-12-11 2001-07-03 International Business Machines Corporation Facilities for detailed software performance analysis in a multithreaded processor
US6247121B1 (en) 1997-12-16 2001-06-12 Intel Corporation Multithreading processor with thread predictor
US6182210B1 (en) 1997-12-16 2001-01-30 Intel Corporation Processor having multiple program counters and trace buffers outside an execution pipeline
US6052709A (en) 1997-12-23 2000-04-18 Bright Light Technologies, Inc. Apparatus and method for controlling delivery of unsolicited electronic mail
US5999932A (en) 1998-01-13 1999-12-07 Bright Light Technologies, Inc. System and method for filtering unsolicited electronic mail messages using data matching and heuristic processing
US6430593B1 (en) 1998-03-10 2002-08-06 Motorola Inc. Method, device and article of manufacture for efficient task scheduling in a multi-tasking preemptive priority-based real-time operating system
US6092175A (en) 1998-04-02 2000-07-18 University Of Washington Shared register storage mechanisms for multithreaded computer systems with out-of-order execution
US6330584B1 (en) 1998-04-03 2001-12-11 Mmc Networks, Inc. Systems and methods for multi-tasking, resource sharing and execution of computer instructions
US6374286B1 (en) * 1998-04-06 2002-04-16 Rockwell Collins, Inc. Real time processor capable of concurrently running multiple independent JAVA machines
US6308279B1 (en) 1998-05-22 2001-10-23 Intel Corporation Method and apparatus for power mode transition in a multi-thread processor
US20020013892A1 (en) 1998-05-26 2002-01-31 Frank J. Gorishek Emulation coprocessor
US6205519B1 (en) * 1998-05-27 2001-03-20 Hewlett Packard Company Cache management for a multi-threaded processor
EP0962856A2 (en) 1998-06-05 1999-12-08 Texas Instruments Incorporated A dual-mode VLIW architecture with software-controlled parallelism
US6289461B1 (en) 1998-06-09 2001-09-11 Placeware, Inc. Bi-directional process-to-process byte stream protocol
US6381682B2 (en) * 1998-06-10 2002-04-30 Compaq Information Technologies Group, L.P. Method and apparatus for dynamically sharing memory in a multiprocessor system
US6115709A (en) 1998-09-18 2000-09-05 Tacit Knowledge Systems, Inc. Method and system for constructing a knowledge profile of a user having unrestricted and restricted access portions according to respective levels of confidence of content of the portions
US6625635B1 (en) 1998-11-02 2003-09-23 International Business Machines Corporation Deterministic and preemptive thread scheduling and its use in debugging multithreaded applications
US20020062435A1 (en) 1998-12-16 2002-05-23 Mario D. Nemirovsky Prioritized instruction scheduling for multi-streaming processors
US6389449B1 (en) 1998-12-16 2002-05-14 Clearwater Networks, Inc. Interstream control and communications for multi-streaming digital processors
US6789181B1 (en) 1999-01-28 2004-09-07 Ati International, Srl Safety net paradigm for managing two computer execution modes
US6493800B1 (en) * 1999-03-31 2002-12-10 International Business Machines Corporation Method and system for dynamically partitioning a shared cache
US20030023835A1 (en) 1999-04-29 2003-01-30 Stavros Kalafatis Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instruction
US6535905B1 (en) * 1999-04-29 2003-03-18 Intel Corporation Method and apparatus for thread switching within a multithreaded processor
US20030009648A1 (en) 1999-07-01 2003-01-09 International Business Machines Corporation Apparatus for supporting a logically partitioned computer system
US6542921B1 (en) * 1999-07-08 2003-04-01 Intel Corporation Method and apparatus for controlling the processing priority between multiple threads in a multithreaded processor
US6357016B1 (en) 1999-12-09 2002-03-12 Intel Corporation Method and apparatus for disabling a clock signal within a multithreaded processor
US7039794B2 (en) 1999-12-09 2006-05-02 Intel Corporation Method and apparatus for processing an event occurrence for a least one thread within a multithreaded processor
US20020116600A1 (en) 1999-12-09 2002-08-22 Smith Lawrence O. Method and apparatus for processing events in a multithreaded processor
US6889319B1 (en) 1999-12-09 2005-05-03 Intel Corporation Method and apparatus for entering and exiting multiple threads within a multithreaded processor
US6496925B1 (en) 1999-12-09 2002-12-17 Intel Corporation Method and apparatus for processing an event occurrence within a multithreaded processor

Non-Patent Citations (85)

* Cited by examiner, † Cited by third party
Title
"A Benchmark Evaluation of a Multi-Threaded RISC Processor Architecture", R. Guru Prasadh and Chuan-lin Wu, 1991 International Conference on Parallel Processing, pp. I-84-I91.
"Architectural and Implementation Tradeoffs in the Design of Multiple-Context Processors", James Laudon, Anoop Gupta and Mark Horowitz, Multithreaded Computer Architecture: A Summary of the State of the Art, chapter 8, pp. 167-200, Kluwer Academic Publishers 1994.
"Evaluation of Multithreaded Uniprocessors for Commercial Application Environments", Richard J . Eickemeyer, Ross E. Johnson, Steven R. Kunkel, Mark S. Squillante and Shiafun Liu, Proceedings of the 23rd Annual International Symposium on Computer Architecture. May 22-24, 1996, pp. 203-212.
"Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor", Dean M. Tullsen, Susan J. Eggers, Joel S. Emer, Henry M. Levy, Jack L. Lo and Rebecca L. Stammm, Proceedings of the 23rd Annual International Symposium on Computer Architecture, May 22-24, 1996, pp. 191-202.
"Instruction Cache Fetch Policies for Speculative Execution", Dennis Lee, Jean-Loup Baer, Brad Calder and Dirk Grunwald, 22nd International Symposium on Computer Architecture, Jun. 1995.
"Multithreading Comes of Age", Peter Song, Microdesign Resources, Jul. 14, 1997, pp. 13-18.
"Multithreading for Rookies", Ruediger R. Asche, http://www.microsoft.com/win32dev/base/threads.htm, Jul. 31, 1998.
"Performance Study of a Multithreaded Superscalar Microprocessor", Manu Gulati and Nader Bagherzadeh, Proceedings Second International Symposium on High-Performance Computer Architecture, Feb. 3-7, 1996, pp. 291-301.
Agarwal, A., et al., "April: A Processor Architecture for Multiprocessing", Proceedings of the 17th Annual International Symposium on Computer Architecture, pp. 104-114. 1990.
Amamiya, M., et al., "Datarol: A Parallel Machine Architecture for Fine-Grain Multithreading", IEEE 1998, pp. 151-162.
Chinese Office Action Issued Apr. 18, 2008 for Chinese Application No. 01809728.6, 16 pages.
Chinese Office Action issued Apr. 2, 2004 for Chinese Application No. 00818829.7, 8 pages.
Chinese Office Action issued Apr. 20, 2007 for Chinese Application No. 200610002572.9, 7 pages.
Chinese Office Action issued Aug. 21, 2009 for Chinese Application No. 01809728.6, 7 pages.
Chinese Office Action issued Aug. 25, 2006 for Chinese Application No. 200510007035.9, 2 pages. (English translation only).
Chinese Office Action issued Dec. 19, 2003 for Chinese Application No. 01809728.6, 15 pages.
Chinese Office Action issued Dec. 26, 2003 for Chinese Application No. 00818829.7, 10 pages.
Chinese Office Action issued Jan. 16, 2004 for Chinese Application No. 00809404.7, 34 pages.
Chinese Office Action Issued Jan. 23, 2009 for Chinese Application No. 01809728.6, 5 pages,
Chinese Office Action issued Jan. 30, 2004 for Chinese Application No. 00818879.3, 11 pages.
Chinese Office Action issued Jun. 11, 2004 for Chinese Application No. 00809404.7, 12 pages.
Chinese Office Action issued Mar. 18, 2005 for Chinese Application No. 00818830.0, 15 pages.
Chinese Office Action issued Sep. 22, 2006 for Chinese Application No. 01809728.6, 8 pages.
Dean M. Tullsen,et al. "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multihreading Processor" Dept. of Computer Science & Engineering, University of WA, Seattle, WA.
Dongwook K et al: "A Partitioned on-Chip Virtual Cache for Fast Processors" Journal of Systems Architecture, Elsevier Science Publishers BV., Amsterdam, NL, vol. 43, No. 8, May 1, 1997, pp. 519-531, XP000685730.
Eggers, S., et al., "Simultaneous Multithreading: A Platform for Next-Generation Processors", IEEE Micro, pp. 12-19, Sep./Oct. 1997.
European Office Action issued Dec. 22, 2006 for European Application No. 00 970 895.6-1243, 3 pages.
European Office Action issued May 20, 2005 for European Application No. 00 970 896.7-2211, 5 pages.
European Office Action issued May 4, 2004 for European Application No. 00 926 240.3-2211, 3 pages.
European Office Action issued Oct. 31, 2005 for European Application No. 00 970 828.0-1243, 6 pages.
Farrens, MK; Pleszkun, AR., "Strategies for Achieving Improved Processor Throughput" The 18th Annual International Symposium on Computer Architecture, May 27-30, 1991, pp. 362-369.
German Office Action issued Aug. 7, 2009 for German Application No. 101 95 962.1-53, 6 pages.
German Office Action issued Feb. 28, 2005 for German Application No. 100 85 363.3-53, 11 pages.
German Office Action issued Jul. 28, 2005 for German Application No. 100 84 804.4-53, 8 pages.
German Office Action issued Mar. 23, 2005 for German Application No. 101 95 962.1-53, 9 pages.
German Office Action issued Oct. 17, 2005 for German Application No. 100 85 363.3-53, 4 pages.
Gregory T. Byrd, et al., "Multithreaded Processor Architectures", Western Carolina University, 8045 IEEE Spectrum, 32(1995) Aug. No. 8, New York, US.
IBM, "Improved Dispatching in a Rendering Context Manager" IBM Technical Disclosure Bulletin, Dec. 1990, pp. 131-134, vol. 33, No. 7, XP000108363 ISSN: 0018-8689, Armonk, NY.
Indian Office Action issued Apr. 23, 2004 for Indian Application No. IN/PCT/2002/00743/MUM, 9 pages.
Indian Office Action issued Apr. 29, 2004 for Indian Application No. IN/PCT/2002/00742/MUM, 9 pages.
Indian Office Action issued Jan. 19, 2004 for Indian Application No. IN/PCT/2001/01337/MUM, 6 pages.
Indian Office Action issued May 7, 2004 for Indian Application No. IN/PCT/2002/00741/MUM, 2 pages.
Indian Office Action issued Sep. 19, 2006 for Indian Application No. 355/MUMNP/2005, 2 pages.
INTEL, "P6 Family of Processors", Hardware Developer's Manual, Sep. 1998, XP-002153160.
International Preliminary Examination Report issued Feb. 22, 2002 for PCT Application No. PCT/US2001/01577, 4 pages.
Israel Office Action issued Dec. 18, 2005 for Israel Application No. 146,159, 5 pages.
Jonsson, J., et al., "Non-Preemptive Scheduling of Real-Time Threads on Multi-level-Context Architecture", IEEE Workshop on Parallel and Distributed Systems, Apr. 12-13, 1999, pp. 1-26.
Korean Notice of Preliminary Rejection issued Mar. 28, 2005 for Korean Application No. 10-2002-7007314, 4 pages.
Korean Notice of Preliminary Rejection issued Sep. 15, 2004 for Korean Application No. 10-20027007314, 3 pages.
Mark R. Thistle, et al., "A Processor Architecture for Horizon", Institute for Defense Analyses, Supercomputing Research Center, Lanham, Maryland 20706.
Mendelson, A; Bekerman, M., "Design Alternatives of Multithreaded Architecture", International Journal of Parallel Programming, Dec. 9, 1996, vol. 27, No. 3, pp. 161-193, Pulenum Publishing Corporation.
Miyake, J., et al., "A Highly Integrated 40-MIPS (Peak) 64-b RISC Microprocessor", IEEE Journal of SolidState Circuits, vol. 25, No. 5, Oct. 1990.
Ortiz, D., et al., "A Preliminary Study of Architectural Support for Multithreading", IEEE 1997, pp. 227233.
PCT International Preliminary Examination Report, PCT/US00/10800, 4 pages, Nov. 15, 2001.
PCT International Preliminary Examination Report, PCT/US00/17664, 4 pages, Aug. 16, 2001.
PCT International Preliminary Examination Report, PCT/US00/28213, Sep. 26, 2001.
PCT International Preliminary Examination Report, PCT/US00/28421, 4 pages, Sep. 28, 2001.
PCT International Preliminary Examination Report, PCT/US00/28422, 4 pages, Sep. 26, 2002.
PCT International Preliminary Examination Report, PCT/US00/32241, 4 pages, Oct. 23, 2002.
PCT International Search Report, PCT/US00/10800, 7 pages, Feb. 20, 2001.
PCT International Search Report, PCT/US00/17664, 7 pages, Nov. 30, 2000.
PCT International Search Report, PCT/US00/28213, 6 pages, Sep. 14, 2001.
PCT International Search Report, PCT/US00/28421, 6 pages, Feb. 2, 2001.
PCT International Search Report, PCT/US00/28422, 7 pages, Sep. 26, 2001.
PCT International Search Report, PCT/US00/32241, 7 pages, Mar. 23, 2001.
PCT Written Opinion, Apr. 26, 2001, PCT/US00/10800.
PCT Written Opinion, PCT/US00/17664, 4 pages, Apr. 4, 2001.
PCT Written Opinion, PCT/US00/32241, 4 pages, Sep. 14, 2001.
PCT Written Opinion, PCT/US01/01577, 5 pages, Nov. 9, 2001.
PCT-International Search Report-PCT/US01/01577, Sep. 10, 2001.
Roa P. Pokala,et al., "Physical Synthesis for Performance Optimization", Vertex Semiconductor, San Jose, CA.
Rosenberg Dictionary of Computers, Information Processing and Telecommunications, 2nd Ed., p. 7, 1987.
Rosenberg Dictionary of Computers, Information Processing and Telecommunications, pp. 299-300, 1987.
Russian Office Action issued Sep. 10, 2003 for Russian Application No. 2002118211, 5 pages.
Simon W. Moore, Multithreaded Processor Design, Kluwer Academic Publishers, 1996.
Steere D et al.., "A Feedback-driven Proportion Allocator for Real-Rate Scheduling", Third Symposium on Operating Systems Design and Implementations, Feb. 22-25, 1999, pp. 145-158, XP002153159.
Taiwanese Office Action issued Feb. 20, 2003 for Taiwan Application No. 089128138, 3 pages.
Taiwanese Office Action issued Jul. 23, 2004 for Taiwan Application No. 090106484, 3 pages.
Taiwanese Office Action issued Oct. 2, 2002 for Taiwan Application No. 090106484, 3 pages.
Taiwanese Office Action issued Oct. 31, 2003 for Taiwan Application No. 090106484, 3 pages.
Tullsen, D., et al., "Simultaneous Multithreading: Maximizing On-Chip Parallelism", Proceedings of the 22nd Annual International Symposium on Computer Architecture, 12 pgs., Jun. 1995.
UK Office Action issued Feb. 26, 2004 for UK Application No. GB 0224460.6, 3 pages.
UK Office Action issued Jun. 24, 2003 for UK Application No. GB 0200078.4, 3 pages.
UK Office Action issued Oct. 28, 2003 for UK Application No. GB 0215189.2, 4 pages.
Zilles, C., et al., "The Use of Multithreading for Exception Handling", Proceedings of the 32nd Annual Symposium on Microarchitecture, IEEE, pp. 219-229. 1990.

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110022773A1 (en) * 2009-07-27 2011-01-27 International Business Machines Corporation Fine Grained Cache Allocation
US8543769B2 (en) 2009-07-27 2013-09-24 International Business Machines Corporation Fine grained cache allocation
US20110055827A1 (en) * 2009-08-25 2011-03-03 International Business Machines Corporation Cache Partitioning in Virtualized Environments
US8739159B2 (en) 2009-08-25 2014-05-27 International Business Machines Corporation Cache partitioning with a partition table to effect allocation of shared cache to virtual machines in virtualized environments
US8745618B2 (en) * 2009-08-25 2014-06-03 International Business Machines Corporation Cache partitioning with a partition table to effect allocation of ways and rows of the cache to virtual machine in virtualized environments
US20120226861A1 (en) * 2011-03-03 2012-09-06 Hitachi, Ltd. Storage controller and method of controlling storage controller
US8370578B2 (en) * 2011-03-03 2013-02-05 Hitachi, Ltd. Storage controller and method of controlling storage controller
US20130097387A1 (en) * 2011-10-14 2013-04-18 The Board Of Trustees Of The Leland Stanford Junior University Memory-based apparatus and method
CN104461928A (en) * 2013-09-16 2015-03-25 华为技术有限公司 Method and device for dividing caches
US20150100763A1 (en) * 2013-10-09 2015-04-09 Arm Limited Decoding a complex program instruction corresponding to multiple micro-operations
CN104572016A (en) * 2013-10-09 2015-04-29 Arm 有限公司 Decoding a complex program instruction corresponding to multiple micro-operations
US9934037B2 (en) * 2013-10-09 2018-04-03 Arm Limited Decoding a complex program instruction corresponding to multiple micro-operations

Also Published As

Publication number Publication date Type
DE10195962T0 (en) grant
CN1429361B (en) 2010-06-23 grant
WO2001077820A3 (en) 2002-04-18 application
CN1429361A (en) 2003-07-09 application
GB0224460D0 (en) 2002-11-27 grant
DE10195962T1 (en) 2003-02-20 grant
GB2377529B (en) 2004-10-27 grant
GB2377529A (en) 2003-01-15 application
WO2001077820A2 (en) 2001-10-18 application

Similar Documents

Publication Publication Date Title
US5632023A (en) Superscalar microprocessor including flag operand renaming and forwarding apparatus
US5751981A (en) High performance superscalar microprocessor including a speculative instruction queue for byte-aligning CISC instructions stored in a variable byte-length format
US6035374A (en) Method of executing coded instructions in a multiprocessor having shared execution resources including active, nap, and sleep states in accordance with cache miss latency
US6119222A (en) Combined branch prediction and cache prefetch in a microprocessor
US5546597A (en) Ready selection of data dependent instructions using multi-cycle cams in a processor performing out-of-order instruction execution
US6038645A (en) Microprocessor circuits, systems, and methods using a combined writeback queue and victim cache
US6094716A (en) Register renaming in which moves are accomplished by swapping rename tags
US6721874B1 (en) Method and system for dynamically shared completion table supporting multiple threads in a processing system
US5740417A (en) Pipelined processor operating in different power mode based on branch prediction state of branch history bit encoded as taken weakly not taken and strongly not taken states
US5931957A (en) Support for out-of-order execution of loads and stores in a processor
Kessler et al. The Alpha 21264 microprocessor architecture
US6052769A (en) Method and apparatus for moving select non-contiguous bytes of packed data in a single instruction
US6473833B1 (en) Integrated cache and directory structure for multi-level caches
US6728866B1 (en) Partitioned issue queue and allocation strategy
US5740398A (en) Program order sequencing of data in a microprocessor with write buffer
US5721857A (en) Method and apparatus for saving the effective address of floating point memory operations in an out-of-order microprocessor
US7711929B2 (en) Method and system for tracking instruction dependency in an out-of-order processor
US6021485A (en) Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching
US5898849A (en) Microprocessor employing local caches for functional units to store memory operands used by the functional units
US7051329B1 (en) Method and apparatus for managing resources in a multithreaded processor
US6141747A (en) System for store to load forwarding of individual bytes from separate store buffer entries to form a single load word
US6694425B1 (en) Selective flush of shared and other pipeline stages in a multithread processor
US6279105B1 (en) Pipelined two-cycle branch target address cache
US5721855A (en) Method for pipeline processing of instructions by controlling access to a reorder buffer using a register file outside the reorder buffer
US6230260B1 (en) Circuit arrangement and method of speculative instruction execution utilizing instruction history caching

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTEL CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LEE, CHAN W.;HINTON, GLENN;KRICK, ROBERT;SIGNING DATES FROM 20000814 TO 20001110;REEL/FRAME:011359/0446

FPAY Fee payment

Year of fee payment: 4