US7790336B2 - Method of joining a plurality of reticles for use in producing a semiconductor layout pattern, a computerized system for implementing such a method and a semiconductor mask arrangement produced by implementing such a method - Google Patents
Method of joining a plurality of reticles for use in producing a semiconductor layout pattern, a computerized system for implementing such a method and a semiconductor mask arrangement produced by implementing such a method Download PDFInfo
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- US7790336B2 US7790336B2 US11/598,792 US59879206A US7790336B2 US 7790336 B2 US7790336 B2 US 7790336B2 US 59879206 A US59879206 A US 59879206A US 7790336 B2 US7790336 B2 US 7790336B2
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/50—Mask blanks not covered by G03F1/20 - G03F1/34; Preparation thereof
Definitions
- the invention relates to a method for joining a plurality of reticles for use in producing a semiconductor layout pattern, so that said reticles will collectively map a circuit arrangement on a semiconductor substrate whilst providing a plurality of matching patterns that are each geometrically linked to a respective particular reticle as being furthermore recited in the preamble of Claim 1 .
- a plurality of matching patterns that are each geometrically linked to a respective particular reticle as being furthermore recited in the preamble of Claim 1 .
- the matching patterns are generally too big to fit in the normal array granularity, so that they will generally be positioned at an edge of “their” reticle. In practice, this will allow a maximum array size of 2 ⁇ 2 patterns, and in many instances, only a 1 ⁇ n pattern, wherein n is an integer of 2 or more.
- reticle is used as corresponding to a “photomask”, wherein a photomask comprises all functionality necessary in the ultimate semiconductor chip. It is possible to use a plurality of reticles to therefrom construct an extended chip, see FIG. 2 hereinafter. Alternatively, a reticle can be subdivided into sub-reticles, wherein various sub-reticles may project respective different functionality parts, so that the whole chip must necessarily be formed by using sub-reticles of more than one different class, see FIGS. 4 and 6 hereinafter.
- the invention is characterized according to the characterizing part of claim 1 .
- the distinguishing between the bulk sub-reticles and the peripheral sub-reticles has been recognized as a conceptual step that allows a variety of embodiments that all effect various aspects of improving the optical adjustment and matching between various sub-reticles.
- the including of a peripheral sub-reticle between its associated matching pattern and a corresponding matching pattern of the bulk sub-reticle on the one hand, and the image of the bulk circuitry contained in the bulk sub-reticle on the other hand include a quantum conceptual step. Note that bulk is not limited to meaning exclusively repetitive. The bulk could for example contain so-called wild logic.
- the invention also relates to a computerized system for implementing the method as claimed in claim 1 , to a compound reticle, to a semiconductor mask arrangement, and to a semiconductor device manufactured by using such method, reticle, or arrangement. Further advantageous aspects of the invention are recited in dependent Claims.
- FIG. 1 a combination of two matching patterns
- FIG. 2 a first layout possibility for two-dimensional stitching
- FIG. 3 a chip resulting therefrom
- FIG. 4 a second layout possibility for two-dimensional stitching
- FIG. 5 a chip resulting therefrom
- FIG. 6 a third layout possibility for two-dimensional stitching
- FIG. 7 a chip resulting therefrom
- FIG. 8 an alternative to the layout of FIG. 6 .
- FIG. 1 illustrates a combination of two matching patterns OB and IB both in the shape of a hollow square or rectangle.
- Each pattern forms part of its associated reticle or sub-reticle, so that verification of the correct respective positions of the two rectangles will also verify the respective positions of their respective (sub-)reticles.
- Typical dimensions of matching patterns now in use are 20 by 20 microns. Of course, various other shapes are feasible, such as circles or meanders. Now, advanced CMOS processes will at present go to minimum details of 0.5 micron and below, and it will often be impossible to position the matching patterns within the often repetitive pattern of the overall circuit functionality.
- FIG. 2 illustrates a first layout possibility for two-dimensional stitching, that is the geometrical joining of various partial reticles into a larger compound reticle.
- the patterns should be outside the eventual functional array.
- the positioning of the patterns at the abutting edges is not a critical restriction, and they can be located in the scribing area of the semiconductor substrate. Note that a succession of various reticles may be applied on any location in view of respectively associated processing steps to be executed.
- FIG. 3 illustrates a chip resulting from the usage of the four patterns of FIG. 1 .
- the four partial reticles have been shown through lining their matching patterns up at abutting corners, as indicated by bold lines.
- a well lined up wafer can be produced by means of four different reticles, and four different positioning operations are necessary that are alternated by steps between positioning one of the four localizing patterns.
- this allows constructing a 2 ⁇ n pattern, such as extending in the horizontal direction. By the way, this would necessitate providing six different reticles instead of four.
- rotating the reticles for thereby producing the matching is generally impractical.
- the providing of many non-identical reticles and the associate repeated centering will let both costs and processing times explode to inappropriate values.
- FIG. 4 illustrates a second layout possibility for two-dimensional stitching.
- the main or bulk functionality of the eventual circuit is represented by central sub-reticle 41 that is present in a single version and is not provided with matching patterns.
- peripheral sub-reticles 42 through 48 that collectively surround central reticle 41 .
- the patterns shown in FIG. 4 represent the complete functionality of the eventual circuit.
- Each respective sub-reticle can now be selected by shielding off the other sub-reticles so that only a single sub-reticle will be exposed in the stepper or scanner apparatus. By repeating this for every sub-reticle, the overall chip can be composed on the wafer.
- the gaps between adjacent sub-reticles are necessary for shielding and for adhering to the design rules of reticles for the stepper the scanner.
- this can on the one hand be peripheral electrical circuitry for together with the content of central sub-reticle 41 realizing the overall functionality.
- they can contain the device sealing ring, the scribe lane, and the matching patterns for overlay monitoring.
- the technique described can significantly increase wafer throughput in the photolithographic or other manufacturing equipment. Furthermore, it will become feasible to produce arrays with various different sizes by using the same reticle set.
- FIG. 5 illustrates a chip resulting from the applying of the various (sub-)reticles of FIG. 4 for a 2 ⁇ 2 arrangement of central sub-reticle 41 .
- the arrangement shown can be extended in both coordinate directions in an unconstrained fashion.
- the overlay monitoring of the central field 41 is not possible directly, neither with respect to the peripheral sub-reticles 42 through 49 , nor among various different instances of central sub-reticle 41 itself. In manufacturing environments such monitoring can however be mandatory.
- FIG. 6 hereinafter.
- the degree of the match between various matching patterns can be quantized and the matching degrees subjected to statistical processing. In various situations this could lead to ascertaining a sufficiently or, alternatively, insufficiently lining out for the central sub-reticle. However, still better matching should be possible.
- FIG. 6 illustrates a third layout possibility for two-dimensional stitching.
- the arrangement corresponds to that of FIG. 4 in that one central or bulk sub-reticle 61 has been provided that is surrounded by eight peripheral sub-reticles 62 through 69 .
- the latter are provided with the same matching patterns as earlier shown in FIG. 4 , such as exemplified by patterns 80 , 82 , 84 , 86 , so that line-out among those eight sub-reticles will be effected likewise.
- central sub-reticle 61 has been shown with new matching patterns as indicated by 72 , 76 on its right hand side. In practice, these two could collectively be constituted by a single matching pattern.
- Corresponding matching patterns have been shown on all four sides of sub-reticle 61 . Sometimes, their addition can be sufficient when present on less than all four edges, such as on two or three only.
- Corresponding matching patterns 70 and 74 regarding patterns 72 and 76 , respectively, have been added to peripheral sub-reticle 63 . Now in contradistinction to earlier embodiments, matching patterns 72 and 76 are so far from central sub-reticle 61 , that it is possible to expose sub-reticle 61 either with matching patterns 72 , 76 , or rather without the latter.
- the distance “A” between central reticle 61 and patterns 72 , 76 has been dimensioned so that all of peripheral sub-reticle 63 at a width of “B” will fit therebetween, so that matching pattern pairs 70 / 72 and 74 / 76 can then be monitored for checking their correct layout. Similar procedures can be effected at the left hand side with respect to peripheral sub-reticle 65 , at the top edge with respect to sub-reticle 62 and at the bottom edge with respect to sub-reticle 64 .
- FIG. 7 illustrates a 2 ⁇ 2 array on a chip resulting from the rub-reticle chip layout of FIG. 6 .
- the instances of the various sub-reticles have been identified as in FIG. 6 .
- instances of the various matching patterns 80 , 82 , 84 , 86 have been shown likewise.
- FIG. 8 illustrates an alternative to the layout of FIG. 6 .
- the rationale is that often, a plurality of identical semiconductor chips can be placed on a single wafer.
- certain peripheral sub-reticles can be projected concurrently. For example, between the rightmost projection of central sub-reticle 61 , both peripheral sub-reticles 63 and 65 can be projected in abuttance to the above array, after which reticle 65 has already been projected in place for use with the next array to the right hand side.
- the cluster of four peripheral sub-reticles 66 through 69 the same applies for use with four neighboring arrays.
- the various matching patterns have not been numbered.
- sub-reticles 63 and 65 can be positioned so close to each other in a horizontal direction in the Figure, that their respectively associated matching patterns will coincide, so that only one instance thereof is necessary. The same change can then be effected on sub-reticles 64 , 62 in a vertical direction. Also, sub-reticles 66 , 67 , 68 and 69 will then join their matching patterns in both horizontal and vertical directions. Note that the overall size of the matching patterns of FIG. 1 is generally large compared to the minimum circuitry detail, but quite small in comparison with the overall sizes of the various (sub-)reticles.
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US11/598,792 US7790336B2 (en) | 2006-11-14 | 2006-11-14 | Method of joining a plurality of reticles for use in producing a semiconductor layout pattern, a computerized system for implementing such a method and a semiconductor mask arrangement produced by implementing such a method |
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US11/598,792 US7790336B2 (en) | 2006-11-14 | 2006-11-14 | Method of joining a plurality of reticles for use in producing a semiconductor layout pattern, a computerized system for implementing such a method and a semiconductor mask arrangement produced by implementing such a method |
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US20080113276A1 US20080113276A1 (en) | 2008-05-15 |
US7790336B2 true US7790336B2 (en) | 2010-09-07 |
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Citations (11)
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US5437946A (en) * | 1994-03-03 | 1995-08-01 | Nikon Precision Inc. | Multiple reticle stitching for scanning exposure system |
US5663017A (en) * | 1995-06-07 | 1997-09-02 | Lsi Logic Corporation | Optical corrective techniques with reticle formation and reticle stitching to provide design flexibility |
US6201598B1 (en) | 1998-04-23 | 2001-03-13 | Nikon Corporation | Charged-particle-beam microlithographic exposure apparatus and reticles for use with same |
US6204912B1 (en) * | 1996-05-08 | 2001-03-20 | Nikon Corporation | Exposure method, exposure apparatus, and mask |
US20010041297A1 (en) * | 1998-06-17 | 2001-11-15 | Kenji Nishi | Mask producing method |
US6337162B1 (en) * | 1998-03-26 | 2002-01-08 | Nikon Corporation | Method of exposure, photomask, method of production of photomask, microdevice, and method of production of microdevice |
US6362491B1 (en) | 1999-10-01 | 2002-03-26 | Taiwan Semiconductor Manufacturing Company | Method of overlay measurement in both X and Y directions for photo stitch process |
US6433347B1 (en) | 1998-06-19 | 2002-08-13 | Nikon Corporation | Charged-particle-beam projection-exposure methods and apparatus that selectively expose desired exposure units of a reticle pattern |
US6591412B2 (en) | 2000-12-04 | 2003-07-08 | Nikon Corporation | Methods for dividing a pattern in a segmented reticle for charged-particle-beam microlithography |
US20040070740A1 (en) | 1998-11-06 | 2004-04-15 | Nikon Corporation | Exposure method and exposure apparatus |
US20050068467A1 (en) * | 2003-09-30 | 2005-03-31 | Arno Bleeker | Methods and systems to compensate for a stitching disturbance of a printed pattern in a maskless lithography system not utilizing overlap of the exposure zones |
-
2006
- 2006-11-14 US US11/598,792 patent/US7790336B2/en active Active
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5437946A (en) * | 1994-03-03 | 1995-08-01 | Nikon Precision Inc. | Multiple reticle stitching for scanning exposure system |
US5663017A (en) * | 1995-06-07 | 1997-09-02 | Lsi Logic Corporation | Optical corrective techniques with reticle formation and reticle stitching to provide design flexibility |
US6204912B1 (en) * | 1996-05-08 | 2001-03-20 | Nikon Corporation | Exposure method, exposure apparatus, and mask |
US6337162B1 (en) * | 1998-03-26 | 2002-01-08 | Nikon Corporation | Method of exposure, photomask, method of production of photomask, microdevice, and method of production of microdevice |
US6201598B1 (en) | 1998-04-23 | 2001-03-13 | Nikon Corporation | Charged-particle-beam microlithographic exposure apparatus and reticles for use with same |
US20010041297A1 (en) * | 1998-06-17 | 2001-11-15 | Kenji Nishi | Mask producing method |
US20040036846A1 (en) | 1998-06-17 | 2004-02-26 | Nikon Corporation | Mask producing method |
US6433347B1 (en) | 1998-06-19 | 2002-08-13 | Nikon Corporation | Charged-particle-beam projection-exposure methods and apparatus that selectively expose desired exposure units of a reticle pattern |
US20040070740A1 (en) | 1998-11-06 | 2004-04-15 | Nikon Corporation | Exposure method and exposure apparatus |
US6362491B1 (en) | 1999-10-01 | 2002-03-26 | Taiwan Semiconductor Manufacturing Company | Method of overlay measurement in both X and Y directions for photo stitch process |
US6591412B2 (en) | 2000-12-04 | 2003-07-08 | Nikon Corporation | Methods for dividing a pattern in a segmented reticle for charged-particle-beam microlithography |
US20050068467A1 (en) * | 2003-09-30 | 2005-03-31 | Arno Bleeker | Methods and systems to compensate for a stitching disturbance of a printed pattern in a maskless lithography system not utilizing overlap of the exposure zones |
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