US7769798B2  Full CMOS minsum analog iterative decoders  Google Patents
Full CMOS minsum analog iterative decoders Download PDFInfo
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 US7769798B2 US7769798B2 US10832806 US83280604A US7769798B2 US 7769798 B2 US7769798 B2 US 7769798B2 US 10832806 US10832806 US 10832806 US 83280604 A US83280604 A US 83280604A US 7769798 B2 US7769798 B2 US 7769798B2
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 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
 H03M13/1102—Codes on graphs and decoding on graphs, e.g. lowdensity parity check [LDPC] codes
 H03M13/1105—Decoding

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/65—Purpose and implementation aspects
 H03M13/6597—Implementations using analogue techniques for coding or decoding, e.g. analogue Viterbi decoder

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
 H03M13/2957—Turbo codes and decoding

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/37—Decoding methods or techniques, not specific to the particular type of coding provided for in groups H03M13/03  H03M13/35
 H03M13/39—Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
 H03M13/3905—Maximum a posteriori probability [MAP] decoding and approximations thereof based on trellis or lattice decoding, e.g. forwardbackward algorithm, logMAP decoding, maxlogMAP decoding; MAP decoding also to be found in H04L1/0055
Abstract
Description
The invention relates to analog iterative decoders.
In recent years, there has been much excitement in the digital communications and coding community about a class of error correcting codes which are very powerful and yet can be decoded practically using iterative algorithms. Two wellknown examples are turbo codes and lowdensity paritycheck (LDPC) codes.
See for example Berrou, C., and Glavieux A., and Thitimajshima, P. “Near Shannon limit errorcorrecting coding: turbo codes,” in Proc. IEEE ICC'93, Geneva, Switzerland, 1993, pp. 10641070 and Gallager, R. G., “Lowdensity parity check codes,” IRE Trans. Inform. Theory, vol. 8, pp. 2128 January 1962.
The iterative algorithms can be most naturally described using graph representations of the codes. The execution of the algorithms can be described as performing certain computations at the nodes of the graph and passing real messages (soft information) along the edges, in both directions and iteratively. There are only a small number of different types of nodes in terms of their computations. In fact, this number is only two and three for LDPC codes and turbo codes, respectively.
The need for floating point computations and the iterative nature of these decoding algorithms have motivated some very recent research on the analog electronic implementation of the algorithms.
See for example S. Hemati and A. H. Banihashemi, “New Analog VLSI Circuits for Iterative Decoding,” Proceedings of the 21st Biennial Symposium on Communications, Queen's University, Kingston, Ontario, Canada, pp. 261263, Jun. 25, 2002; S. Hemati and A. H. Banihashemi, “Iterative Decoding in Analog CMOS,” Proceedings of the 13th ACM Great Lakes Symposium on VLSI, ACM GLSVLSI 2003, Washington D.C., USA, pp. 1520, Apr. 2729, 2003; S. Hemati and A. H. Banihashemi, “Full CMOS MinSum Analog Iterative Decoder,” Proceedings of the 2003 IEEE International Symposium on Information Theory, ISIT2003, Yokohama, Japan, pp. 347, Jun. 29Jul. 4, 2003; S. Hemati and A. H. Banihashemi, “Analog Asynchronous Iterative Decoding, Different Dynamics with Better Performance,” 2nd Analog Decoding Workshop Zürich, Switzerland, September 2003; S. Hemati and A. H. Banihashemi, “A CurrentMode Maximum WinnerTakeAll Circuit with Low Voltage Requirement for MinSum Analog Iterative Decoders,” Proceedings of the 10th IEEE International Conference on Electronics, Circuits and Systems, ICECS2003, Sharjah, UAE, pp 58, Dec. 1417, 2003; S. Hemati and A. H. Banihashemi, “On the Dynamics of Analog Asynchronous Iterative Decoders,” Proceedings of the 41st Annual Allerton Conference on Communication, Control and Computing, University of Illinois, US, pp. 16791687, Oct. 13, 2003; Hagenauer, J., Moerz, M., and Offer, E., “Analog turbo networks in VLSI: the next step in turbo decoding and equalization,” in Proc. Int. Symp. on Turbo Codes and Related Topics, Brest, France, September 2000, pp. 209218, Loeliger, H. A., Lustenberger, F., Helfenstein, M., and Tarkoy, F., “Probability propagation and decoding in analog VLSI,” IEEE Trans. Inform. Theory, vol. 47, no. 2, pp. 837843, February 2001 and Winstead, C., Dai, J., Little, S., YongBin, K., and Jin Kim, W., “Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS”, in Proc. Advanced Research in VLSI conference, 2001, pp. 132147.
In analog implementations, each node in the graph acts as a computational module which communicates asynchronously with other nodes of the graph through edges. Iterations are thus eliminated and are replaced by the settling behaviour of the system. This is projected to improve the ratio of speed to power consumption by two orders of magnitude.
There are a wide variety of iterative decoding algorithms, each resulting in a different performance/complexity tradeoff. Among these, sumproduct (SP), also referred to as belief propagation, performs the best but is considered to be the most complex to implement. In its original form, SP requires basic operations of addition and multiplication of real numbers, and thus the name “sumproduct.” While implementing adders is rather straightforward and does not require much power and area in an integrated circuit, implementing a large number of high precision digital multipliers is more challenging. In fact, this is one of the reasons for shifting from digital to analog for implementing iterative decoders. In analog circuits, the Gilbert differential multiplier is a wellknown solution for implementing multiplication and is widely used in mixer and PLL circuits.
See for example Gray, P. R., and Meyer, R. G., Analysis and Design of Analog Integrated Circuits, third edition, John Wiley & Sons, 1993. In the Gilbert multiplier, bipolar transistors play a key role. In fact, most of the previously reported analog decoders for iterative schemes have been based on SP algorithm, have used the Gilbert multiplier as the core circuit, and have mostly been implemented by BiCMOS technology. BiCMOS technology has the advantage of using fast bipolar transistors together with low power and small size MOSFETs. However, the BiCMOS technology has a complex fabrication process compared to standard CMOS and this translates into higher cost.
There have also been some attempts to implement the SP algorithm with MOSFETs in weak inversion mode (subthreshold region) where transistors are partially turned on, and behave like slow bipolar transistors. See for example Winstead, C., Dai, J., Little, S., YongBin, K., and Jin Kim, W., “Analog MAP decoder for (8, 4) Hamming code in subthreshold CMOS,” in Proc. Advanced Research in VLSI conference, 2001, pp. 132147 and Johns, D. A. and Martin, K., Analog Integrated Circuit Design, first edition, John Wiley & Sons, 1997. Subthreshold circuits in general have the advantage of consuming a very small amount of power, but often suffer from low speed, mismatch problems and low accuracy.
Another iterative decoding algorithm is referred to as “minsum” (MS), described in, for example, Forney, Jr, G. D. “On iterative decoding and twoway algorithm”, in Proc. Int. Symp. on Turbo Codes and Related Topics, Brest, France, September 1997, pp. 1225, which can be regarded as an approximation of SP. Other common names for minsum algorithm are “maxsum”, “maxproduct”, “maxlog MAP” and “BPbased decoding”. For many codes, the performance of MS is slightly (a few tenths of a dB) worse than that of SP. However, it has lower complexity, and unlike SP, does not require an estimate of noise power. More recently, it has also been shown that MS is more robust against quantization noise than SP. See Zarkeshvari, F., and Banihashemi, A. H. “On implementation of minsum algorithm for decoding lowdensity paritycheck (LDPC) codes,” in Proc. Globecom 2002, Taipei, Taiwan, Nov. 1721, 2002.
In fact, MS can be implemented digitally by using only 4 bits compared to 6 bits for a similar implementation of SP. Moreover, there are simple modifications of minsum that can perform very close to sumproduct algorithm. These modifications were presented in Zarkeshvari, F., and Banihashemi, A. H. “On implementation of minsum algorithm for decoding lowdensity paritycheck (LDPC) codes,” in Proc. Globecom 2002, Taipei, Taiwan, Nov. 1721, 2002; J. Zhao, “Effects of clipping and quantization on minsum algorithm and its modifications for decoding lowdensity paritycheck codes,” M. Sc. dissertation, Dept. of Systems and Computer Engineering, Carleton University, Ottawa, Canada, 2003; J. Chen and M. Fossorier, “Near optimum universal belief propagation based decoding of lowdensity paritycheck codes,” IEEE Tran. Comm., vol. 50, pp. 406414, March 2002; J. Chen, A. Dholakia, E. Eleftheriou, M. Fossorier and X.Y. Hu, “Near optimal reduced complexity decoding algorithms for LDPC codes,” Proc. IEEE ISIT, Lausanne, Switzerland, p. 455, Jun. 30Jul. 5, 2002; J. Chen and M. Fossorier, “Density evolution for two improved BPbased decoding algorithms of LDPC codes,” IEEE Comm. Lett., vol. 6, no. 5, pp. 208210, May 2002; J. Chen and M. Fossorier, “Density evolution for BPbased decoding algorithms of LDPC codes and their quantized versions,” Proc. IEEE Globecom, pp. 13781382, November 2002. These modifications involve reducing the absolute value of the outgoing messages in paritycheck nodes and performing clipping.
Because of imperfections in the fabrication process, the problem of mismatch in large analog integrated circuits becomes very important and the higher robustness in minsum can also greatly help in mitigating this problem.
Minsum analog iterative decoders for LDPC codes based on new max WTA circuits are provided. Currentmode full CMOS circuits are provided for implementing the minsum decoder. The circuits can be fabricated by standard CMOS technology. This means lower fabrication cost and simpler design compared to the previously reported analog iterative decoders. An architecture for minsum decoder is presented. Min WTA voltage mode circuits may be used as well.
Modules with large number of inputs can be fabricated easily and with less delay compared to previously reported analog iterative decoders. The modules can also be used as building blocks for implementing the decoders for other iterative coding schemes than LDPC codes. These include turbo, convolutional and block codes.
A new currentmode maximum winnertakeall (Max WTA) circuit is provided. In some embodiments, the inputs and the output of the circuit are high swing, and the voltage requirements for the inputs and the output are very low and just about V_{eff (V} _{sat}) and 2V_{eff }(2V_{sat}), respectively. Because of the cascode configuration, the proposed circuits show very good precision even for short channel MOSFETs.
Advantageously, the new circuits can be implemented with standard CMOS technology and use conventional biasing methods. This makes them more practical and affordable.
According to one broad aspect, the invention provides an analog minsum iterative decoder comprising: a plurality of standard CMOS variable nodes and a plurality of standard CMOS check nodes, the variable nodes and the check nodes being interconnected with a plurality of interconnections in accordance with a code to be decoded; wherein realvalued messages are passed on each interconnection between one of said variable nodes and one of said check nodes.
In some embodiments, each interconnection between one variable node and one check node comprises a first line from the variable node to the check node conveying a first real valued message, and a second line from the check node to the variable node conveying a second real valued message.
In some embodiments, each interconnection between one variable node and one check node comprises a first pair of lines from the variable node to the check node conveying a first differential real valued message, and a second pair of lines from the check node to the variable node conveying a second differential real valued message.
In some embodiments, each check node and each variable node has an output impedance substantially greater than an Rds of a single transistor in an output stage of the check node or variable node.
In some embodiments, each check node and each variable node has a high swing output stage.
In some embodiments, each check node and each variable node has an output stage allowing a swing at least between 2Veff and V_{dd}, where V_{eff }is an effective gate voltage and V_{dd }is a power supply voltage.
In some embodiments, a decoder further comprises shielding and/or guard rings around any digital circuits and digital interconnections within check nodes or variable nodes to reduce effects of switching noise.
In some embodiments, each standard CMOS check node comprises: a respective real to absolute and sign function for each input to the check node, the real to absolute and sign function producing a respective absolute value output and a respective sign output; for each input to the check node: a respective minimum WTA function connected to receive absolute value outputs of the real to absolute and sign functions other than the absolute value output respective the input, adapted to produce a minimum WTA output which is a minimum of the absolute value inputs; a respective XOR function connected to receive sign outputs of the real to absolute and sign functions other than the sign output respective the input, adapted to produce a sign output; an absolute and sign to real converter connected to receive the minimum WTA output and the sign output, adapted to produce a real valued output.
In some embodiments, each analog standard CMOS check node comprises: a respective real to absolute and sign function for each input to the check node, the real to absolute and sign function producing a respective absolute value output and a respective sign output; a minimum WTA function connected to receive absolute value outputs of all of the real to absolute and sign functions, adapted to produce a minimum WTA output which is a minimum of the absolute value inputs; a second minimum WTA function connected to receive absolute value outputs of all of the real to absolute and sign functions, adapted to produce a second minimum WTA output which is a second minimum of the absolute value inputs; switching circuitry adapted to select either the minimum WTA output or the second minimum WTA output as a respective min WTA output for each input; for each input: a respective XOR function connected to receive sign outputs of the real to absolute and sign functions other than the sign output respective the input, adapted to produce a sign output; an absolute and sign to real converter connected to receive the respective minimum WTA output and the sign output, adapted to produce a real valued output.
In some embodiments, each real to absolute and sign function for each input to the check node comprises: a PMOS current mirror and an NMOS current mirror each connected to receive the input; a high swing cascode current mirror having an output connected to a diode connected circuit; wherein an output of the NMOS current mirror is connected to an input of the high swing cascode current mirror, and an output of the NMOS current mirror is connected to the output of the high swing cascode current mirror; a sign conversion circuit connected to receive the input and produce a sign output.
In some embodiments, each minimum WTA function comprises: a maximum WTA function comprising: a common high swing output stage; a plurality of input stages each having a respective feedback path, the feedback paths competing to establish a shared voltage so as to produce a winning current in the common high swing output stage substantially equal to the maximum input current.
In some embodiments, the minimum WTA function has an output resistance at least on the order of Rds^{2}.
In some embodiments, the shared output stage has a cascode structure.
In some embodiments, a decoder further comprises: a plurality of reference current sources for realizing the minimum WTA function from the maximum WTA function.
In some embodiments, in each max WTA circuit: for each input stage: a) the input stage comprises a cascode structure with an input current being input at a first end of the cascode structure, and with the shared voltage being connected to a gate of a transistor at a second end of the cascode structure; b) the respective feedback path comprises a connection from the top of the cascode structure through a feedback transistor to a point at which said shared voltage is established; the common high swing output stage comprises a cascode structure substantially similar to the cascode structure of the input stages, wherein an output current is produced at a first end of the cascode structure as a result of the shared voltage being connected to a gate of a transistor at a second end of the cascode structure.
In some embodiments, the output stage comprises a bleeding transistor to which said shared voltage is applied.
In some embodiments, in each max WTA circuit: each input stage comprises a cascode structure with an input current being input between a first transistor and a second transistor of the cascode structure, and with the shared voltage being connected to gates of the first and second transistors; the output stage comprises a cascode structure having an output between a first transistor and a second transistor of the cascode structure at which a feedback current is produced, with the shared voltage being connected to gates of the first and second transistors; each input stage has a respective feedback path comprising a connection from the top of the cascode structure through a gate of a feedback transistor, the feedback transistor being connected to the input of the output stage; wherein the input stages compete to establish the shared voltage which is applied to the output stage to produce the feedback current substantially equal to the maximum input current, and the feedback current is applied through the feedback transistor(s) of the winning input stage(s) to produce an output current.
In some embodiments, each absolute and sign to real converter receives an absolute input and a sign input, and the absolute and sign to real converter comprises: an NMOS current mirror having two output stages, the NMOS being connected to receive the absolute input, and a PMOS current mirror having an input stage and an output stage, the PMOS current mirror being connected above the two output stages of the NMOS current mirror; a first switch between the two output stages of the NMOS current mirror; a second switch between the input and output stages of the PMOS current mirror; wherein the first and second switches have opposite states controlled by the sign input such that either the output stage of the NMOS current mirror is active, or the second output stage of the PMOS current mirror is active.
In some embodiments, each variable node has at least one check node input each from a respective check node and a has decoder input, and each variable node has a corresponding check node output for each check node input and has a decoder output, the variable node comprising: for each input, a respective input current buffer converting a sign of the input to produce a negative input, each input current buffer having a respective first input current buffer output stage; a sum current buffer connected to receive a sum of negative inputs produced by the input current buffers to produce a sum current equal to a sum of the inputs, the sum current buffer having a first sum current buffer output stage; a sign detecting circuit connected to determine the sign of the sum current, the sign of the output being the decoder output; for each check node output: a respective sum current buffer output stage of which said first sum current buffer output stage may be one, adapted to produce/reproduce the sum current output; a second input current buffer output stage connected to the respective input current input stage and adapted to produce a replica of the negative input current; a respective real valued output for the check node output being produced by adding the sum current output to the replica of the negative input current.
In some embodiments, each input current buffer comprises a PMOS current mirror and an NMOS current mirror connected to receive the input and to generate the negative input.
In some embodiments, the sum current buffer comprises a PMOS current mirror and an NMOS current mirror connected to receive the sum of the negative input currents and to produce sum current output.
In some embodiments, a decoder each sign detecting circuit comprises a pair of NOT circuits connected consecutively.
According to another broad aspect, the invention provides a circuit for implementing a plurality of minimum WTA functions, the circuit comprising: a minimum WTA function connected to receive absolute value inputs, adapted to produce a minimum WTA output which is a minimum of the absolute value inputs; a second minimum WTA function connected to receive the absolute value inputs, adapted to produce a second minimum WTA output which is a second minimum of the absolute value inputs; and switching circuitry adapted to select either the minimum WTA output or the second minimum WTA output as a respective min WTA output for each input.
According to another broad aspect, the invention provides a maximum WTA circuit comprising: a common high swing output stage; a plurality of input stages each having a respective feedback path, the feedback paths competing to establish a shared voltage so as to produce a winning current in the common high swing output stage substantially equal to the maximum input current.
In some embodiments, a maximum WTA circuit has an output resistance at least on the order of Rds^{2}.
In some embodiments, the shared output stage has a cascode structure.
In some embodiments, a minimum WTA circuit comprises: a maximum WTA circuit; a plurality of reference current sources for realizing the minimum WTA function from the maximum WTA function.
In some embodiments, for each input stage: a) the input stage comprises a cascode structure with an input current being input at a first end of the cascode structure, and with the shared voltage being connected to a gate of a transistor at a second end of the cascode structure; b) the respective feedback path comprises a connection from the top of the cascode structure through a feedback transistor to a point at which said shared voltage is established; the common high swing output stage comprises a cascode structure substantially similar to the cascode structure of the input stages, wherein an output current is produced at a first end of the cascode structure as a result of the shared voltage being connected to a gate of a transistor at a second end of the cascode structure.
In some embodiments, the output stage comprises a bleeding transistor to which said shared voltage is applied.
In some embodiments, each input stage comprises a cascode structure with an input current being input between a first transistor and a second transistor of the cascode structure, and with the shared voltage being connected to gates of the first and second transistors; the output stage comprises a cascode structure having an output between a first transistor and a second transistor of the cascode structure at which a feedback current is produced, with the shared voltage being connected to gates of the first and second transistors; each input stage has a respective feedback path comprising a connection from the top of the cascode structure through a feedback transistor to the input of the output stage; wherein the input stages compete to establish the shared voltage which is applied to the output stage to produce the feedback current substantially equal to the maximum input current, and the feedback current is applied through the feedback transistor(s) of the winning input stage(s) to produce an output current.
According to another broad aspect, the invention provides a second maximum WTA circuit comprising: a common high swing output stage; a plurality of input stages; for each combination of two input stages, a feedback path containing a two transistors, each of the two transistors being controlled by a respective one of the two input stages, the feedback paths competing to establish a shared voltage so as to produce a winning current in the common high swing output stage substantially equal to the second maximum input current.
In some embodiments, different feedback paths share transistors.
In some embodiments, a second maximum WTA circuit has an output resistance at least on the order of Rds^{2}.
In some embodiments, the shared output stage has a cascode structure.
In some embodiments, for each input stage, the input stage comprises a cascode structure with an input current being input at a first end of the cascode structure, and with the shared voltage being connected to a gate of a transistor at a second end of the cascode structure; for each pair of input stages, the respective feedback path is connected to the shared voltage, the respective feedback path comprising a series connection of two transistors, one of the two transistors having a gate voltage connection to the top of a first of the pair of input stages, the other of the two transistors having a gate voltage connection to the top of a second of the pair of input stages; the common high swing output stage comprises a cascode structure substantially similar to the cascode structure of the input stages, wherein an output current is produced at a first end of the cascode structure as a result of the shared voltage being connected to a gate of a transistor at a second end of the cascode structure.
In some embodiments, the output stage comprises a bleeding transistor to which said shared voltage is applied.
In some embodiments, each input stage comprises a cascode structure with an input current being input between a first transistor and a second transistor of the cascode structure, and with the shared voltage being connected to gates of the first and second transistors; the output stage comprises a cascode structure having an output between a first transistor and a second transistor of the cascode structure at which a feedback current is produced, with the shared voltage being connected to gates of the first and second transistors; each combination of two input stages has a respective feedback path comprising a series connection of two transistors, one controlled by a voltage at the top of the one of the two input stages, and the other controlled by a voltage at the top of the other of the two input stages; wherein the input stages compete to establish the shared voltage which is applied to the output stage to produce the feedback current substantially equal to the second maximum input current, and the feedback current is applied through the feedback transistor(s) of the winning input stage(s) to produce an output current.
Preferred embodiments of the invention will now be described with reference to the attached drawings in which:
MinSum Decoding Algorithm
To explain the minsum algorithm, binary LDPC codes will be considered together with the bipartite graph that represents the code through its paritycheck equations, referred to as a “Tanner graph”. See for example Tanner, R. M., “A recursive approach to lowcomplexity codes,” IEEE Trans. Inform. Theory, vol. 27, pp. 533547, September 1981.
There are two sets of nodes in a Tanner graph: 1) variable nodes representing code bits, and 2) check nodes representing paritycheck equations. To implement the minsum algorithm in such a graph, two types of computational modules are required: one for variable nodes (VAR) and the other for check nodes (CHK). The operations performed in VAR and CHK modules depend on the representation of soft information (messages that are passed among CHK and VAR nodes through edges).
Referring first to
The operations in the VAR and CHK modules will then be
where M_{v} ^{(0) }is the initial local message at variable node v (i.e. the initial input), N(.) represents the set of neighbouring nodes, and sgn(.) returns 1 or −1 depending on its argument being nonnegative or negative, respectively. Equivalently in the circuits, sign is shown by 0 or Vdd voltages and multiplication of the signs is replaced by an XOR function. The initial message M_{v} ^{(0) }is computed by replacing the conditional probability density functions of the channel output y corresponding to v in (1). It can be shown that for the binary input AWGN channel, M_{v} ^{(0) }can in fact be simplified to the received value y.
In its synchronous form, the algorithm starts by all the variable nodes passing M_{v} ^{(0) }to their neighbouring check nodes. Then iterations start. Each iteration consists of all the check nodes passing messages to variable nodes according to (3), and subsequently all variable nodes sending messages to check nodes based on (2). At each iteration, the hard decision assignment for each bit v is decided based on
The algorithm then stops if the assignment is a codeword, or a maximum number of iterations is reached.
Referring now to
Referring now to
One function executed by the CHK modules is a min winner take all (Min WTA) function which can be implemented in a Min WTA circuit by making small changes to a max WTA circuit. In a practical minsum iterative decoder, a large number of Max WTA circuits are implemented. As an example, for implementing a minsum iterative decoder for a (1008,504) regular LDPC code, more than 3000 Max WTA circuits should be implemented and each Max WTA should have 5 inputs. For LDPC codes the number of inputs in Max WTA circuits is usually small.
Beyond such decoding applications, Max WTA circuits have a wide range of applications in analog signal processing such as fuzzy logic controllers, artificial neural networks, and analog rank extractors, to name a few. There are many designs available for Max WTA circuits. See for example J. Lazzaro, S. Lyckenbush, M. A. Malhowad, and C. Mead, “Winnertakeall of O(n) complexity”, in Advances in Neural Signal Processing Systems, pp. 703711, 1989, I. E. Opris, “Analog rank extractors,” IEEE Trans. Circuits Syst. I, vol. 44, no. 12, pp. 1114140, January 1998, I. E. Opris, “Railtorail multipleinput Min/Max circuit,” IEEE Trans. Circuits Syst. II, vol. 45, no. 1, pp. 137140, January 1998, I. E. Opris, Analog rank extractors and sorting networks, Ph.D. dissertation, Stanford Univ., Stanford, Calif., 1996, I. Baturone, J. L. Huertas, A. Barriga and E. SanchezSolano, “Currentmode multipleinput Max circuit,” Electronic. Lett., vol. 30, no. 9, pp. 678679, April 1994, R. G. Carvajal, J. RamirezAngulo and J. Tombs, “Highspeed high precision voltagemode Min/Max circuits in CMOS technology,” in Proc. IEEE Int. Symp. Circuits and Systems, Geneva, Switzerland, pp. 1316, May, 2000, Z. S. Gunay and E. SanchezSinenico “CMOS winnertakeall circuits: A detail comparison,” in Proc. IEEE Int. Symp. Circuits and Systems, pp. 4144, June, 1997, Y. He, and E. SanchezSinencio, “Minnet Winnertakeall CMOS implementation,” Electronic. Lett., vol. 29, no. 14, pp. 12371239, July 1993 and B. Maundy, “Min/Max circuit for analog conventional decoders,” IEEE Trans. Circuits Syst. II, vol. 48, no. 8, pp. 802806, August 2001. For most existing circuits, due to the short channel effect, the accuracy degrades drastically when fabricated by more advanced CMOS technologies.
However, new CMOS fabrication technologies with shorter channel lengths and increasing output conductance, as well as the persistent trend towards reduced supply voltages have made analog design more challenging. It is therefore of great interest to devise topologies with large input/output voltage swing, small voltage requirements and improved accuracy. Moreover, the existing circuits are not high swing, and the minimum allowable voltage at the inputs and the output is larger than V_{T}+V_{eff}, where V_{T }is the MOSFET threshold voltage and V_{eff }is the effective voltage defined as V_{gs}−V_{T}. In I. Baturone, J. L. Huertas, A. Barriga and E. SanchezSolano, “Currentmode multipleinput Max circuit,” Electronic. Lett., vol. 30, no. 9, pp. 678679, April 1994, good accuracy is achieved by using a MOSFETbased cascode configuration, but the voltage requirement at the inputs and the output is still quite high and is equal to 2V_{T}+2V_{eff }and V_{T}+2V_{eff}, respectively. Some building blocks of an analog iterative decoder using standard CMOS technology, and based on the minsum algorithm are taught in Applicant's publication “New Analog VLSI Circuits for Iterative Decoding” which was presented in June 2002 at the 21st Biennial symposium on Communications, Queen's University, Kingston, ON, Canada hereinafter the “2002 paper”. A complete implementation of an analog decoder was not presented, and the designs that were presented suffer from some disadvantages enumerated below.
A first embodiment of the invention provides an analog iterative decoder implemented entirely in standard CMOS technology. The analog iterative decoder is comprised of VAR nodes, and CHK nodes which are interconnected in accordance with the Tanner graph of a given code. An example of a Tanner graph is shown in
Referring now to
Various example standard CMOS implementations of each of the building blocks of the analog iterative decoder will now be provided in accordance with embodiments of the invention. These will include the VAR node, and the CHK node, the CHK node having in turn the building blocks consisting of the real to absolute and sign converters, minimum winner take all circuits, and absolute and sign to real converters. It is noted that many standard CMOS implementations for XOR functions are available and as such these will not be presented here. Most processing is performed in analog domain so the effect of switching noise in XOR digital circuits should be minimized. This can be done by using low noise digital circuits (for instance, DCVSL logic family). Also, preferably suitable guard rings are used around digital gates to provide some shielding to analog circuits against switching noise in digital circuits.
Preferably, digital signals are made available locally only in new designs and can be shielded. It is noted that in the paper 2002 it was not possible to shield as sign bits are sent from variable nodes to paritycheck and vice versa and are globally available.
VAR Node Implementations
To begin,
Referring now to
One of the required outputs of the VAR node is “a+c+d”. This can be obtained by subtracting b from the output 228 of buffer 226. “−b” is generated by reproducing the output stage of the currentbuffer 220 that was used to generate −b. This output stage is shown at 230.
Then “−b” 232 output by output stage 230 is combined with “a+b+c+d” output at 228 by buffer 226 to generate “a+c+d” at 234.
The “a+c+d” can be obtained as described above. The three other outputs for the VAR module also need to be generated. This can be done by using the circuits shown in
Also based on the bias2 voltage 238, which is a function of amplitude and sign of “a+b+c+d”, the sign of (a+b+c+d) can be determined. In order to do that, two not circuits 260,262 are cascaded as shown in
A specific VAR circuit has been presented, but the invention is not limited to this specific implementation. For example, transistor sizes could be changed. Different currentmirrors could be used in currentbuffer. Instead of using current in a wire to represent soft information, it is possible to represent information by a difference of two currents and it would be even advantageous as it is robust against common mode noise but has a drawback that twice as many interconnections are needed.
CHK Node Implementations
Recall the CHK node requires real to absolute and sign (R to As) circuits, Min WTA circuits and absolute and sign to real converters.
R to AS Circuit
Referring now to
The input current 270, if positive goes to the cascode PMOS current mirror 280 and then is applied to the diodeconnected circuit 284, to generate a voltage at 286 corresponding to the current. If the input current 270 is negative and enters the circuit, NMOS cascode current mirror 282 will be active and its output 283 goes to the highswing cascode current mirror 285 and then is applied to the diodeconnected circuit 284 to generate the output voltage 286. To generate the sign of the signal, the voltage at the input wire is compared with the threshold voltage of the NOT circuits 285.
More generally, in other embodiments, any standard CMOS circuit that works as a current rectifier can be used. Also, the output signal could be voltage or current.
Min WTA Circuit
Referring now to
For the Max WTA portion of the circuit, each cell has an input stage consisting of two transistors Q1 330 and Q2 332. The input is received at the top of Q1. The gates of all the Q2s are connected together through bleeding transistor 337 to Q2 338 of the output cell 306. Also shown is a feedback transistor Q3 334 connected from the top of Q1 to the common gate voltage of Q2s.
The output cell simply consists of Q1 336 and Q2 338 connected in the same manner as the input cells. The input stages compete to establish the common gate voltage of the Q2s. Once established, the current of the “winning” input stage is reproduced at the output, since the same voltage is applied to the gate of Q2 338.
In the Max WTA portion of the circuit of
If the shared voltage is higher than that suitable value for regenerating the max input current, the gate voltage of the feedback transistor decreases, this however, will reduce the shared voltage and so the shared voltage will be equal to what it should be. Eventually, after settling, the shared voltage will be what it needs to be to sustain a current equal to the maximum input current.
At the overall output 320, the maximum current among I_{ref}−a, I_{ref}−b, I_{ref}−c appears, but before transferring to the output it is subtracted from I_{ref }to produce the minimum current among a, b and c. The example of
More generally, some sort of min WTA circuit should be used. It could be currentmode or voltage mode.
Referring now to
In the low swing cascode circuit of
A Min WTA circuit based on the Max WTA circuit of
The structure of the ith cell is the same, with the transistors being labelled Q_{s(i)}, Q_{t(i) }and Q_{f(i)}. Transistors with the same index (s, t or f) are identical. The drains of the transistors Q_{f(i) }of all the cells 20,22,24 are connected together to the output 16. The sources of the transistors Q_{f(i) }of all of the cells 20,22,24 are connected together at 40. Also, the gates of the transistors Q_{t(i) }of all of the cells 20,22,24 are connected together at 42.
The output cell 26, has transistors Q_{s(m+1) } 40 having drain 40D, gate 40G and source 40S, Q_{t(m+1) } 42 having drain 42D, gate 42G and source 42S. The gates 40G and 42G of transistors Q_{s(m+1) }and Q_{t(m+1) }are connected together and to the gates of transistors Q_{t(i) }of cells 20,22,24 at 42. The sources of transistors Q_{f(i) }of cells 20,22,24 are connected between source 40S of Q_{s(m+1) }and drain 42D of Q_{t(m+1)}. A bias current 38 is shown applied to the drain 40D of Q_{s(m+1)}.
The biasing current I_{bias}, flowing through each Q_{s(.) }transistor, is fixed. It can be seen that Q_{s(.) }transistors share the same gate voltage and if they operate in saturation, they share the same source voltage too. The Q_{t(.) }transistors always operate in the triode region, since their gatedrain voltages are higher than V_{T}.
As will be shown below, the result of the competition of cells 20,22,24 is a shared gate voltage for Q_{t(.) }and Q_{s(.) }transistors which is imposed by the maximum input current. Cells “compete” to keep their feedback path active (Q_{f}(.)). For the winner cell negative feedback tunes the output current (16) equal to the input current to the cell. It should be noted that the drain voltage of Q_{t(m+1) }and that of the winner transistor(s) are equal since the corresponding Q_{s(.) }transistors are biased in saturation and have the same drain current and consequently have the same source voltages. For the winner Q_{s(.) }transistor(s) to work in saturation, I_{bias }must be chosen properly as will be discussed later. For Q_{s(m+1)}, however, this is guaranteed as it has a diodeconnected configuration. Having the same gate, source and drain voltages, Q_{t(m+1) }and the winner Q_{t(.) }transistor(s) will have the same drain current regardless of their region of operation (which is in fact triode) and regardless of how nonlinear and complicated the behaviour of the transistors are. As a result, Q_{t(.) }transistors can be built very small or with a high conductance to reduce the voltage requirements at the inputs and the output.
As a result of the winning shared voltage being applied to the output stage, the winner input current is regenerated in output cell as feedback current in Q_{t(m+1) }which is feedback through the Q_{f }transistor(s) of the winning input cell(s) and appears at the output.
The shared gate voltage pushes all Q_{t(.) }transistors to have the same drain current and consequently for loser inputs, corresponding Q_{s(.) }will have to leave the saturation region and operate in triode region. This will decrease the drain voltage of loser Q_{s(.) }transistors and will push the corresponding Q_{f(.) }to cutoff. Winner Q_{f(.) }transistor(s) inject a current equal to the maximum input current to the drain of Q_{t(m+1)}. In fact, a negative feedback is formed by Q_{s(m+1)}, Q_{t(m+1)}, and the winner Q_{f(.)}, Q_{t(.) }and Q_{s(.) }transistors. This adjusts the shared gate voltage of Q_{t(m+1) }and makes its drain current equal to I_{bias}+I_{max}.
For the circuit to function properly, I_{bias }is chosen to bias the winner Q_{s(.) }in saturation. Assuming that the kth input is the winner, then we should have
V_{gd,Q} _{ s(k) }≦V_{T}. (6)
This along with
V _{gd,Q} _{ s(k) } =V _{gs,Q} _{ s(m+1) } −V _{gs,Q} _{ f(k) }, (7)
results in the condition
V _{gs,Q} _{ s(m+1) } ≦V _{T} +V _{gs,Q} _{ f(k) }. (8)
Since V_{gs,Q} _{ f(k) }is always greater than V_{T}, this condition will be satisfied if I_{bias }is chosen such that:
V_{gs,Q} _{ s(m+1) }≦2V_{T} (9)
To improve the accuracy of the circuit and to reduce the power consumption, one would like to decrease I_{bias }as much as possible. This however, decreases the speed of the circuit. A compromise has to be made depending on the application.
One can see that the input voltage to the circuit of
r_{out}≈g_{Q} _{ f }r_{o,Q} _{ f }(r_{o,Q} _{ s(m+1) }∥r_{o,Q} _{ t(m+1) }) (10)
where r_{o }and g are the output impedance and the transfer conductance of the transistors, respectively.
In another embodiment, the accuracy can be improved as explained for cell #1 as an example. If 30D and 30G are connected to the inputs of an operational amplifier (op amp) and 34G instead of being connected to 30D is connected to the output of that op amp, the accuracy improves. The reason is this: a complete matching is preferred between Q_{s(.) }and Q_{t(.) }in input cells and Qs(m+1) and Qt(m+1). However, there is a systematic error in the circuit of
Simulation Results
The WTA circuit of
Since an application described is for lowvoltage minsum analog iterative decoders in which the number of inputs is typically small, the simulations considered a Max WTA with four inputs. Four shifted versions of a periodic triangular current source, which has a period of 100 nSec, and varies between 0 and 50 μA, were used as input signals (m=4). Transistor sizes of W/L=600 nm/130 nm, 600 nm/300 nm, and 1 μm/150 nm, were chosen for Q_{t(.)}, Q_{s(.) }and Q_{f(.) }transistors, respectively. A supply voltage of 1.2 volts, and a bias current I_{bias }of 10 μA. At the output, the voltage is fixed at 0.3 volts to demonstrate the lowvoltage behaviour of the proposed circuit. The input and output currents are shown in
The accuracy when the output current follows one of the inputs is better than 0.1%. This degrades to about 2% when the winner input is changed. This extra degradation, is due to the transient responses of the switched Q_{f(.) }transistors. Voltage variations for the gate of Q_{t(1) }(V_{gs,Q} _{ t(1) }), the drain of Q_{t(1) }(V_{ds,Q} _{ t(1) }), and the gate of Q_{f(1) }(V_{g,Q} _{ f(1) }) are also shown in
Basic operation of winnertakeall circuits depends directly on matching and their accuracy degrades heavily by mismatch. However, mismatch problem is a wellknown problem in analog circuit design. Also professional digital designers care about matching of transistor and routes because of skew. There are quite a few ways for constraining mismatch in a circuit. For instance by choosing proper transistor sizing and using commoncentroid layout and dummy transistors at the ends of the row, mismatch problem can be limited. Hereinafter, it assumes that there is no mismatch in our circuits to make the problem more tractable. Simulation results, however, may be too optimistic.
Comparisons between New Circuits and Circuits in 2002 Paper
The new approach is different from what presented in 2002 paper. To begin, the messages that are sent back and forth among the processing modules are different; this has a huge impact on the performance of the analog iterative decoder. It is shown that in terms of functionality, circuits in 2002 paper are too primitive. It is also noted that in the 2002 paper, not all necessary modules are presented for implementing a minsum decoder.
Messages Transmitted between Modules
As it was discussed earlier, in the new implementations, soft information that are either positive, negative or zero are sent back and forth among the processing modules. In page 2 of 2002 paper in 21^{st }Biennial Symposium on Communications, it is stated that “In our circuit design, we use two new variables W and X to represent the message M:
W=M, X=(sgn(M)+1)/2.
It is then clear that for implementing the CHK computation in (3), one only needs to implement min(.) and binary XOR functions”
The outputs of the variable node in
In contrast, in the new circuits, a single wire represents the soft information. With the previous approach, the number of interconnection would be two times larger. For large codes it is a very important issue since there may be much congestion for routing and any increase in the number of interconnections should be avoided.
While W (absolute value of the soft information (M)) is an analog signal, X is a binary digital signal. Globally distributing digital signals could generate lots of switching noise and the effect of this noise could be more severe when analog sensitive interconnections are close to digital signals, exactly as it is for W and X. In some embodiments of the new circuits, digital signals are just available locally inside the processing modules. This allows mitigation of the switching noise by using a guard ring around these digital circuits, something that was not possible in the previous circuits.
Furthermore, the propagation delay for X and W could be different in practice. Therefore incorrect M could be processed in VAR modules.
Output Impedance
The new designs are based on current mode circuits, so current conveyers play a key role in functionality of our circuits. Conventional current conveyors suffer from low output impedance in short channel transistors. This means that output current of a processing block will change if the output voltage changes. The new circuits strive to have the output current to be independent of the output voltage. The output of a current mode circuit is often modeled by an ideal current source and a resistor (Ro) parallel to that. Any change in the output voltage changes the current flowing through the resistor and consequently changes the output current. Since in these circuits information is expressed in terms of current, this problem can degrade the performance of the circuits and reduce the accuracy. As the transistors shrink in newer technologies, this problem could become more severe as rds (the transistor output impedance) gets smaller.
For the Max WTA circuit presented in 2002 paper, the output impedances are equal to the output impedance of the transistor (rds). For the new Min WTA circuits of
It may be possible to get good performance from the circuits in the 2002 paper by increasing the length and width of the transistors. Increasing the length of the transistors significantly improves the output impedance. However, the overall size of the transistor will increase and therefore big codes can not be implemented in this way (lower integrity level).
Swing Voltage: (High Swing Module Versus Low Swing Modules)
Preferably, the analog decoders are implemented with the same technology that is used for digital circuits. It is desirable to have the same supply voltages for these circuits; otherwise separate voltage sources should be available. Having different supply voltages is a drawback that could increase the overall expense but this is not prohibitive. The supply voltage gets smaller and smaller in new technologies, for instance in 0.18 μm standard digital CMOS technology the supply voltage is 1.8 volts and in 0.13 μm standard digital CMOS technology the supply voltage is just 1.2 volts. Design of analog circuits for reduced supply voltages is quite tricky. In the circuits of the 2002 paper to get good output impedances, the output impedance of the transistors can be increased for example by using larger transistors as described above. However, this will eventually cause a considerable amount of voltage drop on the transistors and if the supply voltage is small then there might not be enough room for voltages to swing. This limits the dynamic range of the current and pushes it towards zero.
Comparisons between New WTA Circuits and WTA Circuits in Baturone Paper
Apart from the clear physical differences between these presented circuits for min WTA and the circuits of the abovereferenced Baturone paper include differences in swing voltage at the input and the output. In that paper, the minimum input voltage is equal to 2VT+2Veff and output voltage should be at least VT+2Veff, where VT is the transistor threshold voltage, and Veff the effective voltage. The swing of this circuit consists of the allowed voltages from these values to Vdd, the power supply voltage. In the “low swing” cascode circuit (
Two circuits having high swing at the output have been presented. More generally, in other embodiments of the iterative decoder, other high swing cascodebased min WTA circuits may be employed.
More generally, a min WTA circuit is provided which has a common high swing output stage and a plurality of input stages each having a respective feedback path, the feedback paths competing to establish a shared voltage. The shared voltage is applied to the output stage to produce the winning current. The term “high swing” in this context is well understood by those in the art. For example, typically if the minimum output voltage includes a VT term, it is not considered a high swing output stage. Preferably, the output resistance is also large. A circuit having output resistance of Rds, the output resistance of a single transistor, is typically not considered to have a large output resistance. In cascode output stages, the output resistance is typically proportional to Rds^{2}, and this is considered large in most contexts.
In summary, for technologies beyond 0.18 μm only the new circuits will remain functional. For 0.18 μm technology and 1.8 volt supply the new circuits would work, but the circuits in 2002 paper would have many problems. In the simulations in that paper, a supply voltage equal to 3.3 volts that can be used in 0.18 CMOS technology was used, but is not desirable in practice as was explained earlier.
Simulations
In order to clarify the problems with the circuits of the 2002 paper, simulations were performed using Cadence spectre toolbox and 0.18 CMOS technology and a supply voltage of 1.8 volts. For the winnertakeall circuit presented in the 2002 paper, it was assumed the winner current is equal to 10 μA and width of the transistors was set to values of 2, 5 and 10 μm for respective simulations and the length was changed from 0.2 to 2 μm. The minimum necessary voltage at the output (
Two new Min WTA circuits have been described, one with highswing and the other one with lowswing. Minor modifications to the circuits can be made to implement clipped minsum, normalized minsum, minsum with conditional or unconditional correction. In clipped minsum the maximum of the messages are bounded. In normalized minsum outgoing messages are scaled properly in each iteration. In conditional or unconditional correction the outgoing messages from CHK nodes are corrected by subtracting it by a fixed or variable number, respectively. All these modification can be easily applied to the described circuits.
AS to R Circuit
The AS to R circuit is the output stage of the CHK node. An example implementation is shown in
In practice, if X inside S1 switch 400 is 1 (1.8 Volts), then the analog switch inside S1 switch is on and the S1 switch acts as a short circuit and the input current transfers to the output through the NMOS current mirror 408 and the additional output stage 409. When X is 1, S2 switch 422 is open circuit and PMOS current mirror is not active. When X is 0, S1 switch 420 is open circuit and the input current appears at the output by passing through the PMOS current mirror. Needless to say depending on which switch (S1 or S2) is short circuit, the direction of the current at the output would be different.
In another embodiment, a novel winner take all structure is provided which may be used in the abovediscussed iterative decoders, but which may find application elsewhere. This embodiment is particularly suited for winner take all implementations having a large number of inputs. Referring to
A 2^{nd }min WTA circuit can be produced from a min WTA circuit by changing the feedback circuit. An example of a high swing 2^{nd }min circuit provided by an embodiment of the invention is shown in
As it was described earlier, in a WTA circuit, competition among input cells aims to keep the feedback path open (like short circuit, not open circuit). For a 2nd min WTA circuit, the input and output cells can be exactly same as any of the embodiments described for a WTA circuit. The circuit of
The feedback paths for the circuit of
The same changes to the feedback path can be made to any other max WTA circuit provided by the invention to produce a 2^{nd }max WTA circuit.
Many of the circuits presented employ specific current mirrors. Other current mirrors may alternatively be used. Preferably, current mirrors are selected so as to have improved output resistance compared to simple current mirrors having output resistance Rds. Preferably, the current mirrors employed feature a cascode structure. However, in some embodiments of the iterative decoder, this may not be the case.
Numerous modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be practiced otherwise than as specifically described herein.
For example, while specific variable nodes and check nodes have been presented, more generally, any standard CMOS implementation of a min sum analog decoder having check and variable nodes interconnected to exchange real valued messages is contemplated by another embodiment of the invention. The actual functions implemented by the variable nodes and check nodes may differ.
New current mode min WTA circuits have been provided. For the iterative analog decoder, these or other min WTA circuits may be employed. For example, voltage mode WTA circuits may be employed.
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