US7664973B2 - Integrated circuit and signal processing apparatus using the same - Google Patents
Integrated circuit and signal processing apparatus using the same Download PDFInfo
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- US7664973B2 US7664973B2 US11/688,599 US68859907A US7664973B2 US 7664973 B2 US7664973 B2 US 7664973B2 US 68859907 A US68859907 A US 68859907A US 7664973 B2 US7664973 B2 US 7664973B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/28—Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3209—Monitoring remote activity, e.g. over telephone lines or network connections
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/324—Power saving characterised by the action undertaken by lowering clock frequency
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to an integrated circuit and a signal processing apparatus by use thereof.
- signal processing apparatuses that have a selling point of portability for handiness of carrying and execute signal processing for desired applications such as portable audio players, cellular phones, portable game machines, and PDAs (Personal Digital Assistants).
- Such signal processing apparatuses achieve the portability by mounting an internal power source composed of a secondary battery (nickel hydrogen rechargeable battery, lithium ion rechargeable battery, etc.) and a primary battery (alkaline battery, manganese battery, etc.) (see, e.g., Japanese Patent Application Laid-Open Publication No. 2001-184146).
- an integrated circuit that operates with application of an external power source supplying a first source voltage
- the circuit comprising: a source voltage monitoring unit that monitors the level of the first source voltage supplied from the external power source, and that determines whether the first source voltage is supplied from the external power source; a clock selecting unit that is supplied with a first clock of a first frequency and a second clock of a second frequency lower than the first frequency, and that selects and outputs the first clock when it is determined by the source voltage monitoring unit that the first source voltage is supplied and the second clock when it is determined by the source voltage monitoring unit that the first source voltage is not supplied; and a processor that operates with supply of either one of the first clock and the second clock output by the clock selecting unit and controls the operation of the integrated circuit.
- the present invention enables reduced power consumption by the integrated circuit by appropriately controlling the source voltage supplied depending on the state of supply of external power source.
- FIG. 1 is an explanatory diagram of external connection of a signal processing apparatus according to the present invention
- FIG. 2 is a configuration diagram of the signal processing apparatus according to the present invention.
- FIG. 3 is waveform diagrams of primary signals for description of operation of an integrated circuit according to the present invention.
- FIG. 4 is waveform diagrams of primary signals for description of operation of the integrated circuit according to the present invention.
- FIG. 1 is an explanatory diagram of external connection of a signal processing apparatus according to the present invention.
- a portable audio reproducing device 100 having a USB (Universal Serial Bus) interface 101 that performs digital reproduction of compressed audio data transferred from a personal computer 300 by way of a data line 401 of a USB cable 400 as an example of the signal processing apparatus according to the present invention.
- the signal processing apparatus according to the present invention may be, for example, a cellular phone, a portable game machine, a PDA, etc.
- the USB is a serial interface standard that enables a variety of signal processing apparatuses with common USB interface to be connected to a USB host device.
- the latest version of the USB is “USB2.0” that has three transfer modes of LS (Low Speed), FS (Full Speed), and HS (High Speed), with the three modes being selectable depending on applications.
- the USB permits a maximum number of 127 USB devices to be connected to a host in a tree structure by use of hubs and accommodates a hot plug that permits a new USB device to be connected to the USB host device while the host is powered on.
- the personal computer 300 is equipped with a USB controller 310 and a USB interface 320 .
- the USB cable 400 comprises a two data lines 401 , a power line 402 , and a GND line 403 , and each of the USB interfaces 320 and 101 is equipped with a pair of data terminals D+ and D ⁇ , a power source terminal VBUS, and a GND terminal.
- the personal computer 300 has a power source adapter 360 that converts an AC source voltage supplied by way of a power plug 361 to a DC source voltage, and has a CPU 330 in charge of overall control, a memory 340 such as a ROM for storing various programs, and a hard disk 350 for storing music files, movie files, etc., all interconnected for mutual communication.
- the music files stored in the hard disk 350 are compressed audio data, for example, of MPEG-1 Audio Layer 3 (MP3) format, etc.
- MP3 MPEG-1 Audio Layer 3
- the movie files stored in the hard disk 350 are compressed movie data, for example, of MPEG-2 format, MPEG-4 format, etc.
- the personal computer 300 runs the program stored in the memory 340 and, by polling request, etc., recognizes the portable audio reproducing device 100 as a USB device connected to itself.
- the personal computer 300 reads out an arbitrary music file from the hard disk 350 and transfers the data to the USB controller 310 .
- the USB controller 310 converts the music file read out from the hard disk 350 to the packet format and performs communication protocol processing conforming to the USB standard for differential half duplex transmission to the portable audio reproducing device 100 by way of the USB interface 320 and the USB cable 400 .
- the portable audio reproducing device 100 can take in the music file from the personal computer 300 .
- the portable audio reproducing device 100 executes reproducing processing of the music file, generally with the USB cable 400 disconnected from the USB interface 101 .
- the portable audio reproducing device 100 can execute reproducing processing of the music file.
- the personal computer 300 can supply the DC source voltage generated at the power source adapter 360 (hereinafter, source voltage VBUS) to the portable audio reproducing device 100 by use of the power line 402 provided in the USB cable 400 .
- the portable audio reproducing device 100 can receive the supply of the source voltage VBUS together with the transfer of the music file from the personal computer 300 .
- the portable audio reproducing device 100 can perform the communication protocol processing conforming to the USB standard with the personal computer 300 and the reproducing processing of the music file, using the source voltage VBUS supplied by the personal computer 300 as an operating voltage, to restrain the power consumption of the internal power source 104 .
- FIG. 2 is a diagram of a configuration of the portable audio reproducing device 100 .
- the portable audio reproducing device 100 comprises an ASIC (Application Specific Integrated Circuit) 200 as an embodiment of “integrated circuit” according to the present invention and its peripheral circuits.
- the “integrated circuit” is realized by the ASIC 200 in this embodiment, but may also be realized by an FPGA (Field Programmable Gate Array) or a PLD (Programmable Logic Device).
- the USB interface 101 is an interface for enabling the connection for communication with the personal computer 300 by way of the USB cable 400 containing the power line 402 .
- the USB cable 400 comprises a two data lines 401 , a power line 402 , and a GND line 403 , and the USB interface 101 is provided with a pair of data terminals D+ and D ⁇ , a power source terminal VBUS, and a GND terminal.
- a regulating circuit 103 generates a regulated source voltage VREG (“first source voltage” according to the present invention) by regulating the level of the source voltage VBUS of a power line 102 wired from the USB interface 101 to the level of voltage (3.3 V, 1.5 V, etc.) necessary for execution by ASIC 200 of the communication protocol processing for which a high speed is required (HS mode, FS mode, etc.).
- VREG first source voltage
- the source voltage that is supplied from the personal computer 300 as USB bus power is specified to be within the range of “+4.75 V to +5.25 V” and, in this embodiment, the level of the source voltage VBUS is determined as “5 V”.
- the level of regulated source voltage VREG is determined as “1.5 V”.
- the internal power source 104 is a power source comprising one or more secondary batteries (such as the nickel hydrogen rechargeable battery (nominal voltage of 1.2 V) and the lithium ion rechargeable battery (nominal voltage of 3.6 V to 3.7 V)) or one or more primary batteries (such as the alkaline battery (nominal voltage of 1.5 V) and the manganese battery (nominal voltage of 1.5 V)) and generates a source voltage VDD (“second source voltage” according to the present invention) of a level lower than that of the regulated source voltage VREG.
- secondary batteries such as the nickel hydrogen rechargeable battery (nominal voltage of 1.2 V) and the lithium ion rechargeable battery (nominal voltage of 3.6 V to 3.7 V)
- primary batteries such as the alkaline battery (nominal voltage of 1.5 V) and the manganese battery (nominal voltage of 1.5 V)
- the internal power source 104 is assumed to be composed of the nickel hydrogen rechargeable battery (nominal voltage of 1.2 V) that is rechargeable and is the secondary battery of the lowest nominal voltage.
- the source voltage VDD should preferably be at the level as low as possible for the lower power consumption of the ASIC 200 , but taking into account the normally operable range of the ASIC 200 and a semiconductor process of the ASIC 200 , the source voltage VDD is assumed to be “1.1 V”, the order of 90% of the nominal voltage (1.2 V).
- a source voltage selecting unit 105 determines, based on a selecting signal DET 1 supplied from a source voltage monitoring unit 270 to be described later by way of a DET terminal 207 , that the source voltage VBUS is being supplied from the personal computer 300 to the portable audio reproducing device 100 , the source voltage selecting unit 105 selects the regulated source voltage VREG. On the other hand, when the source voltage selecting unit 105 determines, based on the selecting signal DET 1 , that the source voltage VBUS is not being supplied from the personal computer 300 to the portable audio reproducing device 100 , the source voltage selecting unit 105 selects the source voltage VDD.
- a non-volatile memory 106 is an external memory for storing the music files transferred from the personal computer 300 by way of the USB cable 400 .
- the non-volatile memory 106 may be, for example, a flash memory.
- a hard disk (not shown) may be employed in place of the non-volatile memory 106 .
- a crystal oscillator 107 is an external oscillating device for generating by oscillation a base clock SCK 2 that serves as a reference in a PLL circuit 280 .
- a self-oscillated clock is supplied from outside of the portable audio reproducing device 100 .
- the ASIC 200 comprises terminals of a D+ terminal 201 , a D ⁇ terminal 202 , an MI terminal 203 , an OUT terminal 204 , a XTAL terminal 205 , a VBUS terminal 206 , a DET terminal 207 , and a VDD terminal 208 .
- the D+ terminal 201 and the D ⁇ terminal 202 are an input/output terminals for connection to the data terminals D+ and D ⁇ , respectively, of the USB interface 101 .
- the MI terminal 203 is an input/output terminal for connection to the non-volatile memory 106 .
- the OUT terminal 204 is an output terminal for outputting results of reproduction of the music files.
- the XTAL terminal 205 is a terminal for connection to the crystal oscillator 107 .
- the VBUS terminal 206 is an input terminal for connection to the power line 102 wired from the power source terminal of the USB interface 101 .
- the DET terminal 207 is an output terminal for outputting the selecting signal DET 1 as the result of determination by the source voltage monitoring unit 270 .
- the VDD terminal 208 is an input terminal to which either one of the regulated source voltage VREG and the source voltage VDD as selected by the source voltage selecting unit 105 is applied.
- the ASIC 200 comprises a microcomputer 210 , a USB controller 220 , a memory interface circuit 230 , a DSP (Digital Signal Processor) 240 , a RAM 250 , and a D/A converter 260 , all connected with one another for mutual communication by way of an internal bus 209 , and further comprises the source voltage monitoring unit 270 , the PLL circuit 280 , and a clock selecting unit 290 .
- a microcomputer 210 a USB controller 220 , a memory interface circuit 230 , a DSP (Digital Signal Processor) 240 , a RAM 250 , and a D/A converter 260 , all connected with one another for mutual communication by way of an internal bus 209 , and further comprises the source voltage monitoring unit 270 , the PLL circuit 280 , and a clock selecting unit 290 .
- DSP Digital Signal Processor
- the microcomputer 210 is a processor in control of the ASIC 200 as a whole.
- the microcomputer 210 supervises and controls the communication protocol processing at the USB controller 220 , the processing of reproducing the music files at the DSP 240 , etc.
- the microcomputer 210 operates at a multiplied clock SCK 1 or a base clock SCK 2 supplied by a clock selecting unit 290 to be described later.
- the USB controller 220 performs the processing of the communication protocol on the part of the portable audio reproduction device 100 and comprises a USB transceiver that relays to the internal bus 209 of the ASIC 200 the data differentially input to the D+ terminal 201 and the D ⁇ terminal 202 from the USB interface 101 , a decoder that decodes packets, a FIFO used as a data buffer, etc.
- the USB controller 220 upon command from the microcomputer 210 , transfers the music file transferred from the personal computer 300 to the memory interface circuit 230 by way of the internal bus 209 .
- the memory interface circuit 230 is a circuit for controlling the reading or writing of the data between the ASIC 200 and the non-volatile memory 106 connected to the MI terminal 203 .
- the memory interface circuit 230 performs the processing of writing the music file transferred from the USB controller 220 to the non-volatile memory 106 .
- the DSP 240 is a circuit for performing the digital signal processing associated with the reproduction of the music file. For example, at the time of reproducing the music file, upon command from the microcomputer 210 , the music file written to the non-volatile memory 106 is read out by the memory interface circuit 230 and is stored in the RAM 250 as a working memory. The DSP 240 reads out the music file stored in the RAM 250 and performs decoding processing in conformity to the data format thereof (e.g., the MP3 decoding, etc.). Then, thus decoded digital signal is converted to an analog signal by the D/A converter 260 and thereafter, is output to the outside by way of the OUT terminal 204 .
- the data format thereof e.g., the MP3 decoding, etc.
- the source voltage monitoring unit 270 determines whether the source voltage VBUS is being supplied from the personal computer 300 , by monitoring the level of the source voltage VBUS that can be supplied from the personal computer 300 by way of the power line 402 when the USB cable 400 is connected to the USB interface 101 .
- a pull-down resistor Rd is provided in advance on the power line 102 electrically connected to the power line 402 by way of the USB interface 101 . Then, when the USB cable 400 is connected to the USB interface 101 and the source voltage VBUS is supplied from the personal computer 300 , the level of the voltage applied to the VBUS terminal 206 becomes “5 V”. On the other hand, when the USB cable 400 is disconnected from the USB interface 101 , the source voltage VBUS is not supplied from the personal computer 300 , and therefore, the level of the voltage applied to the VBUS terminal 206 becomes “0 V”, due to the pull-down resistor Rd.
- the source voltage monitoring unit 270 comprises a binarizing processing unit 271 and a determining processing unit 272 .
- the binarizing processing unit 271 by comparing the level of the voltage applied to the VBUS terminal 206 with a predetermined reference level Vth (e.g., 2.5 V), outputs either a High level or a Low level.
- Vth e.g. 2.5 V
- the determining processing unit 272 by measuring a period of time of the High level or the Low level output from the binarizing processing unit 271 , determines that the source voltage VBUS is being supplied from the personal computer 300 when the High level has continued for a certain period of time Th and that the source voltage VBUS is not being supplied from the personal computer 300 when the Low level has continued for a certain period of time Th. In this manner, by not making determination until after the High level or the Low level output by the binarizing processing unit 271 has continued for a certain period of time Th, an erroneous result of determination can be prevented from occurring, for example, due to a power source noise of a spike form.
- the result of determination by the determining processing unit 272 is used as a selecting signal DET 1 for the selection by the source voltage selecting unit 105 of either the regulated source voltage VREG or the source voltage VDD and as a selecting signal DET 2 for the selection by the clock selecting unit 290 of either the multiplied clock SCK 1 or the base clock SCK 2 . Since the source voltage selecting unit 105 is a peripheral circuit of the ASIC 200 , the selecting signal DET 1 is output to the source voltage selecting unit 105 by way of the DET terminal 207 .
- the PLL circuit 280 is a circuit for generating the multiplied clock SCK 1 (“first clock” according to the present invention) in synchronization with the base clock SCK 2 (“second clock” according to the present invention) supplied from the crystal oscillator 107 by way of the XTAL terminal 205 .
- a frequency f 1 (“first frequency” according to the present invention) of the multiplied clock SCK 1 is a frequency obtained by multiplying a frequency f 2 (“second frequency” according to the present invention) of the base clock SCK 2 by a reciprocal of a number for dividing frequency of a frequency divider circuit (not shown) in the PLL circuit 280 .
- the frequency f 1 of the multiplied clock SCK 1 is assumed to be “50 MHz” and the frequency f 2 of the base clock SCK 2 is assumed to be “12 MHz”.
- the clock selecting unit 290 is supplied with the multiplied clock SCK 1 output from the PLL circuit 280 and the base clock SCK 2 before input to the PLL circuit 280 .
- the clock selecting unit 290 selects the multiplied clock SCK 1 and supplies it to the microcomputer 210 .
- the clock selecting unit 290 selects the base clock SCK 2 and supplies it to the microcomputer 210 .
- the regulated source voltage VREG of a level higher than that of the source voltage VDD is selected so that the power of the internal power source 104 will not be consumed and at the same time, on the premise that the regulated source voltage VREG is selected, the multiplied clock SCK 1 of a frequency higher than that of the base clock SCK 2 is selected so that the microcomputer 210 will not stop its operation and hang up.
- the selection of the multiplied clock SCK 1 of a higher frequency results in an increase in the power consumption of the ASIC 200 as compared with the case of selecting the base clock SCK 2 .
- the portable audio reproducing device 100 since the regulated source voltage VREG in accordance with the source voltage VBUS supplied from the personal computer 300 is used as the operating voltage, the portable audio reproducing device 100 does not need to worry about the power consumption of the internal power source 104 .
- the portable audio reproducing device 100 can use, for example, the multiplied clock SCK 1 of a high frequency and consequently, can perform high-speed processing of data transfer of the music file from the personal computer 300 by way of the USB cable 400 .
- the portable audio reproducing device 100 can continue to perform the reproducing processing of the music file, using the regulated source voltage VREG and the multiplied clock SCK 1 , while restraining the power consumption of the internal power source 104 .
- the base clock SCK 2 of a frequency lower than that of the multiplied cock SCK 1 is selected and therefore, the power consumption of the ASIC 200 is reduced as compared with the case of selecting the multiplied clock SCK 1 .
- the source voltage VDD is selected that is of the level lower than that of the regulated source voltage VREG and of the level minimally required for causing the ASIC 200 to operate, the power consumption of the ASIC 200 can be further reduced. As a result of reduced power consumption of the ASIC 200 , a reproducing time of the music file can be extended.
- FIG. 3( a ) depicts a waveform of the level of the voltage applied to the VBUS terminal 206
- FIG. 3( b ) depicts waveforms of the selecting signals DET 1 and DET 2 output from the source voltage monitoring unit 270
- FIG. 3( c ) depicts a waveform of the source voltage applied to the VDD terminal 208
- FIG. 3( d ) depicts a waveform of the clock supplied from the clock selecting unit 290 to the microcomputer 210 .
- the case is assumed to be that the USB cable 400 is connected to the USB interface 101 and the music file is data-transferred, and the source voltage VBUS is supplied, from the personal computer 300 to the portable audio reproducing device 100 .
- the level of the voltage applied to the VBUS terminal 206 is “5 V” (see FIG. 3( a )) and the source voltage monitoring unit 270 determines that the source voltage VBUS is being supplied from the personal computer 300 (both of DET 1 and DET 2 at Low level) (see FIG. 3( b )).
- the source voltage selecting unit 105 selects the regulated source voltage VREG, based on the Low level of the selecting signal DET 1 (see FIG. 3( c )).
- the clock selecting unit 290 selects the multiplied clock SCK 1 , based on the Low level of the selecting signal DET 2 .
- the USB cable 400 is disconnected from the USB interface 101 .
- the level of the voltage applied to the VBUS terminal 206 is attenuated to “0 V”, due to the pull-down resistor Rd connected to the power line 102 (see FIG. 3( a )).
- the level of the voltage applied to the VBUS terminal 206 is below the reference level Vth (see FIG. 3( a )) and the output of the binarizing processing unit 271 is at Low level.
- the selecting signals DET 1 and DET 2 output from the determining processing unit 272 remain at Low level (see FIG. 3( b )).
- the determining processing unit 272 switches the selecting signal DET 2 , earlier than the selecting signal DET 1 , from the Low level to the High level (see FIG. 3( b )).
- the clock selecting unit 290 selects the base clock SCK 2 , based on the High level of the selecting signal DET 2 (see FIG. 3( d )).
- the determining processing unit 272 switches the selecting signal DET 1 from the Low level to the High level.
- the source voltage selecting unit 105 selects the source voltage VDD based on the High level of the selecting signal DET 1 (see FIG. 3( c )).
- the clock selecting unit 290 switches from the selection of the multiplied clock SCK 1 to the selection of the base clock SCK 2 earlier than the selection of the regulated source voltage VREG is switched to the selection of source voltage VDD at the source voltage selecting unit 105 .
- the use of the multiplied clock SCK 1 is absolutely premised on the supply of the regulated source voltage VREG. For this reason, following the disconnection of the USB cable 400 , the regulated source voltage VREG of a higher level is switched to the source voltage VDD of a lower level only after the multiplied clock SCK 1 of a high frequency is switched to the base clock SCK 2 of a low frequency.
- FIGS. 4( a ), 4 ( b ), 4 ( c ), and 4 ( d ) depict same kinds of waveforms as shown in FIGS. 3( a ), 3 ( b ), 3 ( c ), and 3 ( d ), respectively.
- the case is assumed to be that the USB cable 400 is disconnected from the USB interface 101 and the portable audio reproducing device 100 is not supplied with the source voltage VBUS from the personal computer 300 .
- the level of the voltage applied to the VBUS terminal 206 is “0 V” (see FIG. 4( a )) and the source voltage monitoring unit 270 determines that the source voltage VBUS is not being supplied from the personal computer 300 (both of DET 1 and DET 2 at High level) (see FIG. 4( b )).
- the source voltage selecting unit 105 selects the source voltage VDD, based on the High level of the selecting signal DET 1 (see FIG. 4( c )) and the clock selecting unit 290 selects the base clock SCK 2 , based on the High level of the selecting signal DET 2 .
- the USB cable 400 is connected to the USB interface 101 .
- the level of the voltage applied to the VBUS terminal 206 increases from “0 V” to “5 V” (see FIG. 4( a )).
- the level of the voltage applied to the VBUS terminal 206 is above the reference level Vth (see FIG. 4( a )) and the output of the binarizing processing unit 271 is at High level.
- the selecting signals DET 1 and DET 2 output from the determining processing unit 272 remain at High level (see FIG. 4( b )).
- the determining processing unit 272 switches the selecting signal DET 1 , earlier than the selecting signal DET 2 , from High level to Low level (see FIG. 4( b )).
- the determining processing unit 272 does not consider it to be a level change attributable to the power source noise.
- the regulated source voltage VREG is generated by the regulating circuit 103 .
- the source voltage selecting unit 105 selects the regulated source voltage VREG, based on the Low level of the selecting signal DET 1 (see FIG. 4( c )).
- the determining processing unit 272 switches the selecting signal DET 2 from the High level to the Low level.
- the clock selecting unit 290 selects the multiplied clock SCK 1 , based on the Low level of the selecting signal DET 2 (see FIG. 4( d )).
- the clock selecting unit 290 switches from the selection of the base clock SCK 2 to the selection of the multiplied clock SCK 1 later than the selection of the source voltage VDD is switched to the selection of the regulated source voltage VREG at the source voltage selecting unit 105 .
- the use of the multiplied clock SCK 1 is absolutely premised on the supply of the regulated source voltage VREG. For this reason, following the connection of the USB cable 400 , the base clock SCK 2 of a low frequency is switched to the multiplied clock SCK 1 of a high frequency only after the source voltage VDD of a lower level is switched to the regulated source voltage VREG of a higher level.
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JP2006080796A JP4669803B2 (en) | 2006-03-23 | 2006-03-23 | Integrated circuit and signal processing apparatus using the same |
JP2006-080796 | 2006-03-23 |
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US7664973B2 true US7664973B2 (en) | 2010-02-16 |
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Also Published As
Publication number | Publication date |
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TWI338833B (en) | 2011-03-11 |
KR100972271B1 (en) | 2010-07-23 |
US20070229122A1 (en) | 2007-10-04 |
CN101042610A (en) | 2007-09-26 |
CN101042610B (en) | 2010-04-21 |
JP4669803B2 (en) | 2011-04-13 |
KR20070096844A (en) | 2007-10-02 |
JP2007257290A (en) | 2007-10-04 |
TW200809485A (en) | 2008-02-16 |
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