US7552353B2 - Controlling circuit for automatically adjusting clock frequency of a central processing unit - Google Patents
Controlling circuit for automatically adjusting clock frequency of a central processing unit Download PDFInfo
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- US7552353B2 US7552353B2 US11/309,533 US30953306A US7552353B2 US 7552353 B2 US7552353 B2 US 7552353B2 US 30953306 A US30953306 A US 30953306A US 7552353 B2 US7552353 B2 US 7552353B2
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/08—Clock generators with changeable or programmable clock frequency
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- the present invention relates to a controlling circuit for adjusting clock frequency of a central processing unit (CPU), and particularly to a controlling circuit for automatically adjusting clock frequency of a CPU according to a variation of a load on the CPU.
- CPU central processing unit
- a CPU in a computer is a core component integrated with necessary additional circuits onto a single chip called a microprocessor.
- a need of a clock frequency value of the CPU is related to a load on the CPU.
- the clock frequency of the CPU needs to be adjusted according to a variation of the load on the CPU.
- the clock frequency of the CPU is dynamically adjusted according to a temperature of the CPU because the temperature of the CPU increases along with the increase of the load on the CPU.
- some environmental factors e.g. temperature of chipsets around the CPU, and an airflow made by computer fans can influence the temperature as well.
- a fan for cooling of the CPU is broken, the temperature of the CPU increases, resulting in an unwanted change of the clock frequency of the CPU, thereby increasing a risk of burning the CPU.
- a controlling circuit for automatically adjusting clock frequency of a CPU includes: a current sensing circuit for converting a current signal of the CPU to a voltage signal; a voltage amplifying circuit for amplifying the voltage signal; a multi-stage switching circuit for converting the amplified voltage signal to switched signals; and a priority decoding circuit decoding the switched signals, the decoded switched signals being input to a clock generator of the CPU, and thereby adjusting the clock frequency of the CPU to fit different load on the CPU. It is of advantage that the controlling circuit automatically adjusts clock frequency of the CPU according to a variation of the load on the CPU.
- FIG. 1 is a block diagram of a controlling circuit for automatically adjusting clock frequency of a CPU, in accordance with a preferred embodiment of the present invention
- FIG. 2 is circuit diagram of a current sensing circuit, a voltage amplifying circuit, and a multi-stage switching circuit of the controlling circuit of FIG. 1 ;
- FIG. 3 is circuit diagram of a priority decoding circuit of the controlling circuit of FIG. 1 .
- FIG. 1 shows a controlling circuit for automatically adjusting clock frequency of a CPU, in accordance with a preferred embodiment of the present invention.
- the controlling circuit includes a current sensing circuit 10 , a voltage amplifying circuit 20 , a multi-stage switching circuit 30 , and a priority decoding circuit 40 .
- the current sensing circuit 10 connected between a power supply of the CPU and the CPU, converts a current signal I L of the CPU to a voltage signal.
- the voltage amplifying circuit 20 amplifies the voltage signal.
- the multi-stage switching circuit 30 converts the amplified voltage signal to switched signals.
- the priority decoding circuit 40 decodes the switched signals.
- the decoded switched signals are input to a clock generator 60 of the CPU, adjusting the clock frequency of the CPU.
- FIG. 2 shows the current sensing circuit 10 , the voltage amplifying circuit 20 , and the multi-stage switching circuit 30 of the controlling circuit.
- the current sensing circuit 10 includes an inductor L and a resistor R L connected in series between the power supply and the CPU, and a capacitor C and a resistor R S connected in series to each other but parallel across L and R L .
- the voltage amplifying circuit 20 includes resistors R 1 , R 2 , R 3 , R 4 , and an amplifier 21 .
- the amplifier 21 has an inverting input connected to a node between the capacitance C and the resistor R L via the resistor R 1 , and a non-inverting input connected to a node between the capacitance C and the resistor R S via the resistor R 3 and also connected to ground via the resistor R 4 , and the resistor R 2 is connected between an output of the amplifier 21 and the inverting input.
- the multi-stage switching circuit 30 includes a plurality of switching circuits.
- the first switching circuit includes a resistor 31 and an n-channel metal-oxide semiconductor field effect transistor (N-MOSFET) M 1 .
- the N-MOSFET M 1 has a gate connected to the output of the amplifier 21 , a drain connected to a voltage input V CC , and a source connected to ground via the resistor 31 .
- the second switching circuit includes a resistor 32 , a N-MOSFET M 2 , and a diode D 1 .
- the N-MOSFET M 2 has a gate connected to a cathode of the diode D 1 , a drain connected to the voltage input V CC , and a source connected to ground via the resistor 32 .
- the n-stage switching circuit includes a resistor 3 n (the n symbolizes a natural number no less than two), a N-MOSFET Mn, and a diode Dn ⁇ 1.
- the N-MOSFET Mn has a gate connected to a cathode of the diode Dn ⁇ 1, a drain connected to the voltage input V CC , and a source connected to ground via the resistor 3 n.
- An anode of the diode Dn ⁇ 1 is connected to the gate of the N-MOSFET Mn ⁇ 1.
- V G , V S , V D are respectively a gate voltage, a source voltage, a drain voltage, a threshold voltage, a voltage difference between the gate and the source, and a voltage difference between the gate and the drain of the N-MOSFET Mn.
- V G [V out ⁇ (n ⁇ 1) V p] Wherein V p is a threshold voltage of the diode Dn ⁇ 1, and Vout is a voltage output from the amplifier 21 .
- the source voltage V S 0
- Switching signals A1, A2, . . . An are respectively a output voltage of the N-MOSFET M 1 , N-MOSFET M 2 , . . . N-MOSFET Mn.
- FIG. 3 shows the priority decoding circuit 40 of the controlling circuit.
- the priority decoding circuit 40 converts the switched signals A1, A2, . . . An generated by the multi-stage switching circuit 30 to decoded switched signals B1, B2, . . . Bm.
- the multi-stage switching circuit 30 will include a 7-stage switching circuit.
- the switched signals are A1, A2, A4, A5, A6, and A7.
- the decoded switched signals are then B1, B2, and B3.
- a decoding table is as table I. Wherein “1” symbolizes the high level, and “0” symbolizes the low level. If a load on the CPU increases, the current signal I L of the CPU increases. The voltage signal converted by the current sensing circuit 10 thereby increases. And the amplified voltage signal converted by the voltage amplifying circuit 20 also increases. Therefore a number of the switching circuits that are turned on increases.
- the corresponding decoded switched signals decoded by the priority decoding circuit 40 control the clock generator 60 generating a higher clock frequency. Also, if the load on the CPU reduces, the controlling circuit controls the clock generator 60 to generate a lower clock frequency.
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Abstract
A controlling circuit for automatically adjusting clock frequency of a CPU is provided. The controlling circuit includes: a current sensing circuit for converting a current signal of the CPU to a voltage signal; a voltage amplifying circuit for amplifying the voltage signal; a multi-stage switching circuit for converting the amplified voltage signal to switched signals; and a priority decoding circuit decoding the switched signals, the decoded switched signals being input to a clock generator of the CPU, and thereby adjusting the clock frequency of the CPU to fit different load on the CPU.
Description
The present invention relates to a controlling circuit for adjusting clock frequency of a central processing unit (CPU), and particularly to a controlling circuit for automatically adjusting clock frequency of a CPU according to a variation of a load on the CPU.
Computers are being used today to perform a vide variety of tasks. A CPU in a computer is a core component integrated with necessary additional circuits onto a single chip called a microprocessor. A need of a clock frequency value of the CPU is related to a load on the CPU. When a large amount of data is being processed, e.g. a 3D game is being played, the CPU needs to run at a high frequency to ensure game performance. Therefore the clock frequency of the CPU needs to be adjusted according to a variation of the load on the CPU.
Conventionally the clock frequency of the CPU is dynamically adjusted according to a temperature of the CPU because the temperature of the CPU increases along with the increase of the load on the CPU. However, some environmental factors, e.g. temperature of chipsets around the CPU, and an airflow made by computer fans can influence the temperature as well. Furthermore, if a fan for cooling of the CPU is broken, the temperature of the CPU increases, resulting in an unwanted change of the clock frequency of the CPU, thereby increasing a risk of burning the CPU.
What is needed, therefore, is a controlling circuit for automatically adjusting clock frequency of a central processing unit (CPU) according to some other parameter rather than a temperature of the CPU.
A controlling circuit for automatically adjusting clock frequency of a CPU is provided. In a preferred embodiment, the controlling circuit includes: a current sensing circuit for converting a current signal of the CPU to a voltage signal; a voltage amplifying circuit for amplifying the voltage signal; a multi-stage switching circuit for converting the amplified voltage signal to switched signals; and a priority decoding circuit decoding the switched signals, the decoded switched signals being input to a clock generator of the CPU, and thereby adjusting the clock frequency of the CPU to fit different load on the CPU. It is of advantage that the controlling circuit automatically adjusts clock frequency of the CPU according to a variation of the load on the CPU.
Other advantages and novel features will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings, in which:
The voltage amplifying circuit 20 includes resistors R1, R2, R3, R4, and an amplifier 21. The amplifier 21 has an inverting input connected to a node between the capacitance C and the resistor RL via the resistor R1, and a non-inverting input connected to a node between the capacitance C and the resistor RS via the resistor R3 and also connected to ground via the resistor R4, and the resistor R2 is connected between an output of the amplifier 21 and the inverting input.
The multi-stage switching circuit 30 includes a plurality of switching circuits. The first switching circuit includes a resistor 31 and an n-channel metal-oxide semiconductor field effect transistor (N-MOSFET) M1. The N-MOSFET M1 has a gate connected to the output of the amplifier 21, a drain connected to a voltage input VCC, and a source connected to ground via the resistor 31. The second switching circuit includes a resistor 32, a N-MOSFET M2, and a diode D1. The N-MOSFET M2 has a gate connected to a cathode of the diode D1, a drain connected to the voltage input VCC, and a source connected to ground via the resistor 32. An anode of the diode D1 is connected to the gate of the N-MOSFET M1. The rest may be deduced by analogy: the n-stage switching circuit includes a resistor 3 n (the n symbolizes a natural number no less than two), a N-MOSFET Mn, and a diode Dn−1. The N-MOSFET Mn has a gate connected to a cathode of the diode Dn−1, a drain connected to the voltage input VCC, and a source connected to ground via the resistor 3 n. An anode of the diode Dn−1 is connected to the gate of the N-MOSFET Mn−1. The N-MOSFET Mn turns on, if the following equation is satisfied:
V GS =V G −V S >=V T , V GD =V G−V D >=V T
Wherein VG, VS, VD (equal to VCC), VT, VGS, VGD are respectively a gate voltage, a source voltage, a drain voltage, a threshold voltage, a voltage difference between the gate and the source, and a voltage difference between the gate and the drain of the N-MOSFET Mn. The gate voltage VG is found using the following equation:
V G =[V out−(n−1)V p]
Wherein Vp is a threshold voltage of the diode Dn−1, and Vout is a voltage output from theamplifier 21. The source voltage VS=0
An equation is derived using the above equations:
V out>=(n−1)V p +V CC +V T
If the above equation is satisfied, the N-MOSFET Mn turns on and the drain of the N-MOSFET Mn is at a high level. And if the above equation is not satisfied, the N-MOSFET Mn is off and the drain of the N-MOSFET Mn is at a low level. Switching signals A1, A2, . . . An are respectively a output voltage of the N-MOSFET M1, N-MOSFET M2, . . . N-MOSFET Mn.
V GS =V G −V S >=V T , V GD =V G−V D >=V T
Wherein VG, VS, VD (equal to VCC), VT, VGS, VGD are respectively a gate voltage, a source voltage, a drain voltage, a threshold voltage, a voltage difference between the gate and the source, and a voltage difference between the gate and the drain of the N-MOSFET Mn. The gate voltage VG is found using the following equation:
V G =[V out−(n−1)V p]
Wherein Vp is a threshold voltage of the diode Dn−1, and Vout is a voltage output from the
An equation is derived using the above equations:
V out>=(n−1)V p +V CC +V T
If the above equation is satisfied, the N-MOSFET Mn turns on and the drain of the N-MOSFET Mn is at a high level. And if the above equation is not satisfied, the N-MOSFET Mn is off and the drain of the N-MOSFET Mn is at a low level. Switching signals A1, A2, . . . An are respectively a output voltage of the N-MOSFET M1, N-MOSFET M2, . . . N-MOSFET Mn.
As an example, if n equals 7, then the multi-stage switching circuit 30 will include a 7-stage switching circuit. The switched signals are A1, A2, A4, A5, A6, and A7. The decoded switched signals are then B1, B2, and B3. A decoding table is as table I. Wherein “1” symbolizes the high level, and “0” symbolizes the low level. If a load on the CPU increases, the current signal IL of the CPU increases. The voltage signal converted by the current sensing circuit 10 thereby increases. And the amplified voltage signal converted by the voltage amplifying circuit 20 also increases. Therefore a number of the switching circuits that are turned on increases. The corresponding decoded switched signals decoded by the priority decoding circuit 40 control the clock generator 60 generating a higher clock frequency. Also, if the load on the CPU reduces, the controlling circuit controls the clock generator 60 to generate a lower clock frequency.
| TABLE I | |
| Decoded | |
| Switched | switched |
| signals | signals |
| A7 | A6 | A5 | A4 | A3 | A2 | A1 | B3 | B2 | B1 |
| 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 |
| 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 |
| 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 |
| 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
It is believed that the present invention and its advantages will be understood from the foregoing description, and it will be apparent that various changes may be made thereto without departing from the spirit and scope of the invention or sacrificing all of its material advantages, the examples hereinbefore described merely being preferred or exemplary embodiments of the invention.
Claims (15)
1. A controlling circuit for automatically adjusting clock frequency of a central processing unit (CPU), the controlling circuit comprising:
a current sensing circuit for converting a current signal of the CPU to a voltage signal;
a voltage amplifying circuit for amplifying the voltage signal, and comprising an output to output an amplified voltage signal;
a multi-stage switching circuit for converting the amplified voltage signal to switched signals, the multi-stage switching circuit comprising plurality of switching circuits from a first-stage switching circuit to an Nth-stage switching circuit subsequently, the N symbolizing a natural number no less than two; each of the plurality of switching circuits comprising a resistor and a switching element, the switching element comprising a first terminal connected to a voltage input, a second terminal connected to ground via the resistor, and a control terminal for controlling on and off of the switching element wherein the control terminal of the first-stage switching circuit is connected to the ouput of the voltage amplifying circuit to receive amplified voltage signal, the control terminal of the subsequent-stage switching circuit receives a divided voltaae of the voltage received by the control terminal of the previous-stage switching circuit; the second tenninals output the switched signals; and
a priority decoding circuit for decoding the switched signals, the decoded switched signals being input to a clock generator of the CPU, and thereby adjusting the clock frequency of the CPU.
2. The controlling circuit as claimed in claim 1 , wherein the current sensing circuit comprises a first series circuit consisting of an inductor and a resistor connected in series, and a second series circuit consisting of a capacitor and a resistor connected in series, the first and second series circuits are connected in parallel.
3. The controlling circuit as claimed in claim 1 , wherein the voltage amplifying circuit comprises an amplifier for amplifying the voltage signal.
4. The controlling circuit as claimed in claim 1 , wherein the switching element of each of the switching circuits is an n-channel metal-oxide semicnductor field effect transistor (n-MOSFET), the first, second, and control terminals are the drain, source, and gate of the n-MOSFET, respectively.
5. The controlling circuit as claimed in claim 4 , wherein the second-stage switching circuit further comprises a diode, the n-MOSFET of the second-stage switching circuit having the gate connected to a cathode of the diode, and an anode of the diode being connected to the output of the amplifier.
6. The controlling circuit as claimed in claim 5 , wherein when N is greater than 2, the Nth-stage switching circuit further comprises a diode, a cathode of the diode is connected to the gate of the n-MOSFET of the Nth-stage switching circuit, and an anode of the diode being connected to the gate of the n-MOSFET of the (N-1)th-stage switching circuit.
7. A controlling circuit for automatically adjusting clock frequency of a microprocessor, the conirofling circuit comprising:
a current sensing circuit for converting a current signal of the microprocessor to a voltage signal;
a voltage amplifying circuit for amplifying the voltage signal;
a multi-stage switching circuit for converting the amplified voltage signal to switched signals, the multi-stage switching circuit comprising a plurality of switching circuits from a first-stage switching circuit to an Nth-stage switching circuit, the N symbolizing a natural number no less than two,
the first switching circuit comprising a resistor and a switching element, the resistor and the switching element connected in series between a power source and ground, the voltage amplifying circuit outputting an amplified voltage signal to a control terminal of the switching element of the first switching circuit;
the second switching circuit comprising a resistor, a switching element, and a diode, the resistor and the switching element connected in series between a power source and ground, the amplified voltage signal from the voltage amplifying circuit be provided to a control terminal of the switching element of the second switching circuit via the diode;
the Nth-stage switching circuit comprising a resistor, a switching element, and a diode, the resistor and the switching element connected in series between a power source and ground, the amplified voltage signal from the voltage amplifying circuit be provided to a control terminal of the switching element of the Nth-stage switching circuit via (N-1) diodes connected in series; and
a priority decoding circuit for decoding the switched signals, the decoded switched signals being input to a clock generator of the microprocessor, and adjusting the clock frequency of the microprocessor corresponding to the current signal of the microprocessor.
8. The controlling circuit as claimed in claim 7 , wherein the current sensing circuit comprises a first series circuit consisting of an inductor and a resistor connected in series, and a second series circuit consisting of a capacitor and a resistor connected in series.
9. The controlling circuit as claimed in claim 7 , wherein the voltage amplifying circuit comprises an amplifier for amplifying the voltage signal.
10. The controlling circuit as claimed in claim 7 , wherein the switching element of the second switching circuit is an n-channel metal-oxide semiconductor field effect transistor (n-MOSFET), the control terminal is the gate of the n-MOSFET, the gate is connected to a cathode of the diode of the second switching circuit, a drain of the n-MOSFET is connected to the voltage input, and a source of the n-MOSFET is connected to ground via the resistor, and an anode of the diode is connected to the output of the amplifier.
11. The controlling circuit as claimed in claim 7 , wherein when N is greater than 2, the switching element of the Nth-stage switching circuit is an MOSFET, the control terminal is the gate of the n-MOSFET, the gate is connected to a cathode of the diode, a drain of the n-MOSFET is connected to the voltage input, and a source of the n-MOSFET is connected to ground via the resistor, and an anode of the diode is connected to the gate of the n-MOSFET of the (N-1)th-stage switching circuit.
12. The controlling circuit as claimed in claim 7 , wherein the switching element of the first switching circuit is an n-channel metal-oxide semiconductor field effect transistor (n-MOSFET), the control terminal is the gate of the n-MOSFET, the gate is connected to an output of the amplifier, a drain is connected to a voltage input, and a source is connected to ground via the resistor.
13. A controlling circuit for automatically adjusting clock frequency a microprocessor, the controlling circuit comprising:
a current sensing circuit for converting a current signal of the microprocessor which is responsive to a load on the microprocessor to a voltage signal;
a voltage amplifying circuit for amplifying the voltage signal;
a multi-stage switching circuit for converting the amplified voltage signal to switched signals, the multi-stage switching circuit comprising a plurality of switching circuits from a first switchig circuit to a Nth-stage switching circuit, and (N-1) voltage dividers, the N symbolizing a natural number no less than two,
each of the plurality of switching circuits comprising a resistor and a switching element, the resistor and the switching element connected in series between a power source and ground,
the plurality of voltage divider connected in series between an output terminal of the voltage amplifying circuit and a control terminal of the Nth-stage switching element,
a control terminal of the switching element of the first switching circuit connected to the output terminal of the voltage amplifying circuit, control terminals of the switching elements of the subsequent switching circuits connected to nodes between the (N-1) voltage divider, respectively; and
a decoding circuit for decoding the switched signals to control signals which are input to a clock generator of the microprocessor to thereby adjust the clock frequency of the microprocessor to fit the load of the microprocessor.
14. The controlling circuit as claimed in claim 13 , wherein the switching element of each of the plurality of the switching circuit is an n-channel metal-oxide semiconductor field effect transistor (n-MOSFET), the control terminal is the gate of the n-MOSFET, the first switching circuit receiving the amplified voltage signal directly, and the Nth-stage switching circuit receiving the amplified voltage signal via (N-1) diodes.
15. The controlling circuit as claimed in claim 13 , wherein the voltage dividem are diodes connected in series with an anode of the first diode connected to the output tenninal of the voltage amplifying circuit, and a cathode of the (N-1)th diode connected to the control terminal of the switching element of the Nth switching circuit.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200510037032.X | 2005-09-02 | ||
| CNB200510037032XA CN100412755C (en) | 2005-09-02 | 2005-09-02 | In-time adjusting circuit for central processor frequency |
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| Publication Number | Publication Date |
|---|---|
| US20070076498A1 US20070076498A1 (en) | 2007-04-05 |
| US7552353B2 true US7552353B2 (en) | 2009-06-23 |
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| Application Number | Title | Priority Date | Filing Date |
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| US11/309,533 Expired - Fee Related US7552353B2 (en) | 2005-09-02 | 2006-08-18 | Controlling circuit for automatically adjusting clock frequency of a central processing unit |
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| CN (1) | CN100412755C (en) |
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| US20080148090A1 (en) * | 2006-12-18 | 2008-06-19 | Asustek Computer Inc. | Method for adjusting working frequency of chip |
| US20090037754A1 (en) * | 2007-07-30 | 2009-02-05 | Samsung Electronics Co., Ltd. | Battery module, computer system having the same, and control method of the computer system |
| US20100185878A1 (en) * | 2009-01-16 | 2010-07-22 | Anton Rozen | Method for controlling power consumption and a device having power consumption capabilities |
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| DE102008049714A1 (en) * | 2008-09-30 | 2010-04-01 | Siemens Enterprise Communications Gmbh & Co. Kg | Method and arrangement for operating an electronic system |
| CN101807101B (en) * | 2009-02-13 | 2011-08-24 | 英业达股份有限公司 | Voltage compensating device |
| CN101807090B (en) * | 2009-02-16 | 2012-03-28 | 盛群半导体股份有限公司 | Frequency regulation device of electronic system |
| FR2955218B1 (en) * | 2010-01-08 | 2012-02-10 | St Microelectronics Sa | METHOD AND DEVICE FOR CONTROLLING THE FREQUENCY OF A CLOCK SIGNAL OF AN INTEGRATED CIRCUIT |
| CN106292838B (en) * | 2016-07-27 | 2020-08-25 | 联想(北京)有限公司 | Control method, processor and electronic equipment |
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| US20080148090A1 (en) * | 2006-12-18 | 2008-06-19 | Asustek Computer Inc. | Method for adjusting working frequency of chip |
| US7886179B2 (en) * | 2006-12-18 | 2011-02-08 | Asustek Computer Inc. | Method for adjusting working frequency of chip |
| US20090037754A1 (en) * | 2007-07-30 | 2009-02-05 | Samsung Electronics Co., Ltd. | Battery module, computer system having the same, and control method of the computer system |
| US8433938B2 (en) * | 2007-07-30 | 2013-04-30 | Samsung Electronics Co., Ltd. | Battery module, computer system having the same, and control method of the computer system |
| US9405352B2 (en) | 2007-07-30 | 2016-08-02 | Samsung Electronics Co., Ltd. | Battery module, computer system having the same, and control method of the computer system |
| US20100185878A1 (en) * | 2009-01-16 | 2010-07-22 | Anton Rozen | Method for controlling power consumption and a device having power consumption capabilities |
| US8181049B2 (en) * | 2009-01-16 | 2012-05-15 | Freescale Semiconductor, Inc. | Method for controlling a frequency of a clock signal to control power consumption and a device having power consumption capabilities |
Also Published As
| Publication number | Publication date |
|---|---|
| US20070076498A1 (en) | 2007-04-05 |
| CN1924759A (en) | 2007-03-07 |
| CN100412755C (en) | 2008-08-20 |
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