US7333580B2 - Pipelined parallel processing of feedback loops in a digital circuit - Google Patents
Pipelined parallel processing of feedback loops in a digital circuit Download PDFInfo
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- US7333580B2 US7333580B2 US10/147,049 US14704902A US7333580B2 US 7333580 B2 US7333580 B2 US 7333580B2 US 14704902 A US14704902 A US 14704902A US 7333580 B2 US7333580 B2 US 7333580B2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
- H04L25/03057—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception with a recursive structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/04—Distributors combined with modulators or demodulators
- H04J3/047—Distributors with transistors or integrated circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L25/03012—Arrangements for removing intersymbol interference operating in the time domain
- H04L25/03019—Arrangements for removing intersymbol interference operating in the time domain adaptive, i.e. capable of adjustment during data reception
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
- H04L25/03—Shaping networks in transmitter or receiver, e.g. adaptive shaping networks
- H04L25/03006—Arrangements for removing intersymbol interference
- H04L2025/03433—Arrangements for removing intersymbol interference characterised by equaliser structure
- H04L2025/03439—Fixed structures
- H04L2025/03445—Time domain
- H04L2025/03471—Tapped delay lines
- H04L2025/03484—Tapped delay lines time-recursive
- H04L2025/0349—Tapped delay lines time-recursive as a feedback filter
Definitions
- the present invention relates to digital circuits. More particularly, the present invention relates to pipelining of multiplexer loops in a digital circuit.
- digital communications systems are designed, for example, using look-ahead, pipelining, and parallelism techniques. These known techniques have enabled engineers to build digital communications systems, using available manufacturing technologies, which operate at data rates in excess of 1 Gb/s. These known techniques, however, cannot always be applied successfully to the design of higher speed digital communications systems. Applying these techniques is particularly difficult when dealing with nested feedback loops or multiplexer loops.
- look-ahead for example, for fast computation of recursive loops is known.
- a multiplexer loop such as, for example, the multiplexer loop of a decision feedback equalizer found in modern transceivers.
- Many of these approaches will not improve the performance of the digital circuit to which they are applied, and some of these approaches can even degrade circuit performance.
- the application of known pipelining and parallelism techniques to nested feedback loops or multiplexer loops in high speed digital communications systems will not necessarily result in improved performance.
- design techniques and digital logic circuits that can be used to build high-speed digital communication systems.
- design techniques and digital logic circuits are needed which can be used to build digital communications circuits that operate in excess of 2.5 Gb/s.
- Digital circuits and methods for designing digital circuits that determine output values based on a plurality of inputs values are provided. As described herein, the present invention can be used in a wide range of applications. The invention is particularly suited to high-speed digital communications systems, although the invention is not limited to just these systems.
- Digital circuits that operate at a data processing rate in excess of 1 gigabit per second are designed in accordance with an embodiment of the invention as follows.
- a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected.
- a clocking rate (C) is selected for the digital circuit, wherein a product (P), P being equal to B times C, is equal to at least 1 gigabit per second.
- An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed.
- This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero.
- the initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream.
- An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines.
- the unfolded circuit is retimed to achieve the selected clocking rate (C).
- the initial circuit is unfolded by a factor equal to the number of delays in the feedback loop. In another embodiment, the initial circuit is unfolded by a factor less than the number of delays in the feedback loop. In still another embodiment, the initial circuit is unfolded by a factor greater than the number of delays in the feedback loop.
- the initial circuit is unfolded to form at least two parallel processing circuits that are interconnected by a feedback loop. In another embodiment, the initial circuit is unfolded to form at least two parallel processing circuits that are not interconnected by a feedback loop.
- the initial circuit is formed to have an innermost nested feedback loop.
- This innermost nested feedback loop has N+1 delays.
- the initial circuit is formed using a multiplexer loop.
- a digital logic circuit according to the invention forms part of a transceiver circuit.
- the invention can be used, for example, in backplane, optical/fiber, twisted-pair, and coaxial cable transceivers.
- FIG. 1 illustrates an example 2-tap decision feedback equalizer circuit.
- FIG. 2 illustrates an example circuit of a reformulated version of the decision feedback equalizer circuit of FIG. 1 , where all four possible inputs are precomputed, and where an output is selected using a 4-to-1 multiplexer with two previous outputs acting as control signals.
- FIG. 3 illustrates how a 4-parallel embodiment decision feedback equalizer circuit is used in a backplane, fiber, or cable transceiver operating at high speed.
- FIG. 4 illustrates 64-to-1 multiplexer loop.
- FIG. 5 illustrates a circuit having a single feedback loop.
- FIG. 6 illustrates a circuit having three feedback loops.
- FIG. 7 illustrates a 4-unfolded multiplexer loop circuit obtained by unfolding the multiplexer loop of FIG. 4 by a factor of four.
- FIG. 8 illustrates two cut-sets that can be used to retime the circuit of FIG. 7 .
- FIG. 9 illustrates the retimed 4-unfolded multiplexer loop of FIG. 7 .
- FIG. 10 illustrates a 2-to-1 multiplexer loop circuit.
- FIG. 11 illustrates a circuit that can be formed by applying pipelining and look-ahead to the circuit of FIG. 10 .
- FIG. 12A illustrates a 4-to-1 multiplexer loop circuit.
- FIG. 12B illustrates a 2-unfolded multiplexer loop circuit obtained by unfolding the multiplexer loop of FIG. 12A by a factor of two.
- FIG. 12C illustrates a 3-unfolded multiplexer loop circuit obtained by unfolding the multiplexer loop of FIG. 12A by a factor of three.
- FIG. 12D illustrates an example digital processing circuit that includes a feedback loop having one delay.
- FIG. 12E illustrates an example 3-unfolded digital processing circuit obtained by unfolding the circuit of FIG. 12D by a factor of three.
- FIG. 12F illustrates an example digital processing circuit that includes a feedback loop having two delays.
- FIG. 12G illustrates an example 3-unfolded digital processing circuit obtained by unfolding the circuit of FIG. 12F by a factor of three.
- FIG. 12H illustrates an example 4-unfolded digital processing circuit obtained by unfolding the circuit of FIG. 12F by a factor of four.
- FIG. 13 illustrates a circuit developed by applying a first form of pipelining and look-ahead to the circuit of FIG. 12A .
- FIG. 14 illustrates a circuit developed by applying a second form of pipelining and look-ahead to the circuit of FIG. 12A .
- FIG. 15A illustrates a circuit according to an embodiment of the invention.
- FIG. 15B illustrates an example 2-unfolded circuit obtained by unfolding the circuit of FIG. 15A by a factor of two.
- FIG. 15C illustrates an example 3-unfolded circuit obtained by unfolding the circuit of FIG. 15A by a factor of three.
- FIGS. 15D-1 and 15 D- 2 illustrate an example 4-unfolded circuit obtained by unfolding the circuit of FIG. 15A by a factor of four.
- FIG. 15E illustrates a circuit having a 3-level look-ahead network according to an embodiment of the invention.
- FIG. 16 illustrates a 64-to-1 multiplexer loop that incorporates the circuit of FIG. 15A .
- FIG. 17 illustrates a critical path of a 4-unfolded multiplexer loop based on the circuit of FIG. 16 .
- FIG. 18 illustrates two cut-sets that can be used to retime the circuit of FIG. 17 .
- FIG. 19 illustrates the retimed circuit of FIG. 17 .
- FIG. 20 illustrates an 8-to 1 multiplexer loop.
- FIG. 21 illustrates a circuit formed by applying the look-ahead and pipelining techniques of the invention to the 8-to 1 multiplexer loop of FIG. 20 .
- FIG. 22 illustrates a flowchart of the steps of a method for pipelining multiplexer loops that form part of an integrated circuit according to an embodiment of the invention.
- FIG. 23 illustrates a serial representation of a 3-tap decision feedback equalizer.
- FIG. 24 illustrates a serial representation of a 3-tap decision feedback equalizer having 2-levels of look-ahead according to the invention.
- FIG. 25 illustrates a 2-level look-ahead network according to an embodiment of the invention.
- FIG. 26 illustrates a 4-unfolded comparator circuit with f i -latch and pipeline-registers.
- FIG. 27 illustrates a 6-bit compare circuit
- FIG. 28 illustrates a serializer/deserializer 4-tap decision feedback equalizer integrated circuit according to an embodiment of the invention.
- FIGS. 29A-B illustrate a flowchart of the steps of a method for designing a digital circuit according to an embodiment of the invention.
- FIG. 1 illustrates a circuit 100 having two feedback loops.
- Circuit 100 is a 2-tap decision feedback equalizer (DFE).
- DFE 2-tap decision feedback equalizer
- Circuit 100 has two delay devices 102 , 104 and a threshold device 106 .
- delay devices 102 , 104 are flip-flops. In other embodiments, other devices such as registers are used. As will be understood by persons skilled in the relevant arts, the output of these devices change in accordance with a clock signal. Thus, the performance or rate at which circuit 100 can process data is limited by a clock period of operation. For circuit 100 , the clock period of operation is limited by one multiply, two adds, and a thresholding (or compare) operation. However, for binary signaling, i.e., where a(n) is “0” or “1”; multiplication by “0” or “1” is typically not a factor.
- the rate at which data is processed in a digital communications system can be increased through the use of parallelism or unfolding.
- fast DFE implementations typically reformulate the DFE loop computation based on parallel branch delayed decision techniques where all possible outputs are computed and the correct output is selected by a multiplexer.
- the multiplexer is typically controlled by one or more previous outputs.
- the feedback loop is limited to a multiplexer delay only.
- a typical propagation delay of a 2-to-1 multiplexer built using 0.13 micron photolithography technology is about 0.2 nanoseconds (ns).
- FIG. 2 illustrates a circuit 200 formed by reformulating circuit 100 using a parallel branch delayed decision technique.
- Circuit 200 can process data at a higher rate than circuit 100 .
- circuit 200 has two delay devices 202 , 204 , four threshold devices 206 , 208 , 210 , 212 , and a 4-to-1 multiplexer 214 .
- the inputs to the four threshold devices 206 , 208 , 210 , 212 must be computed.
- the performance of circuit 200 is inherently limited by the operating performance of multiplexer 214 .
- an X-tap DFE can be reformulated and implemented using 2 X comparators and a 2 X -to-1 multiplexer.
- the speed is limited by the 2 X -to-1 multiplexer.
- the signal a(n) has “Y” possible values or levels, it can be represented using a word-length of “b” bits, where “b” equals
- PAM-Y modulated signals e.g., PAM-4 or PAM-5 modulated signals
- PAM-tap DFE can be reformulated and implemented using Y X comparators and a Y X -to-b multiplexer.
- FIG. 3 illustrates a circuit 300 that implements a serdes (serializer/deserializer) for a backplane application, which makes use of a 4-parallel embodiment of a DFE.
- circuit 300 has a DFE 302 , a precursor filter 304 , four analog-to-digital convertors (ADC) 306 a , 306 b , 306 c , 306 d , four programmable gain amplifiers (PGA) 308 a , 308 b , 308 c , 308 d , a timing recovery circuit 310 , and an automatic gain control circuit 312 .
- ADC analog-to-digital convertors
- PGA programmable gain amplifiers
- a 6-tap DFE can be implemented using 64 comparators and a 64-to-1 multiplexer loop in a serial implementation.
- a 64-to-1 multiplexer loop 400 is illustrated in FIG. 4 .
- 64-to-1 multiplexer loop 400 is implemented using sixty-three 2-to-1 multiplexers 402 .
- 64-to-1 multiplexer loop 400 requires 32 instances of 2-to-1 multiplexer 402 a , 16 instances of 2-to-1 multiplexer 402 b , 8 instances of 2-to-1 multiplexer 402 c , 4 instances of 2-to-1 multiplexer 402 d , 2 instances of 2-to-1 multiplexer 402 e , and 1 instance of 2-to-1 multiplexer 402 f.
- 2-to-1 multiplexer 402 f is highly loaded. Fan-out and a large capacitance typically reduce the expected performance of 64-to-1 multiplexer loop 400 .
- a typical computation time for multiplexer 402 f loaded as shown in FIG. 4 , is about 0.45 ns (i.e., more than twice the 0.2 ns that can be achieved if multiplexer 402 f were not heavily loaded).
- 64-to-1 multiplexer loop 400 has six delay devices 404 a , 404 b , 404 c , 404 d , 404 e , 404 f . These six delay devices form part of six nested feedback loops. As described herein, nested feedback loops limit the applicability of known design techniques used by engineers to build high-speed digital communications systems.
- loop means a directed path that begins and ends at the same node of a circuit.
- loop bound means a calculated time, wherein the loop bound of the j-th loop of a circuit is given by EQ. 1:
- T j W j EQ . ⁇ 1 T j is the loop computation time and W j is the number of delays in the loop. This point is further illustrated by the circuit in FIG. 5 .
- FIG. 5 illustrates a circuit 500 having a single loop (i.e., a feedback loop).
- This single loop contains two delays (shown in FIG. 5 as a single delay device 502 such as, for example, a 2-bit shift register or 2 flip-flops in series).
- Circuit 500 has an adder 504 and a multiplier 506 .
- critical loop means the loop of a circuit having the longest loop bound.
- a circuit may have more than just one critical loop.
- iteration bound means the loop bound of the critical loop of a circuit. This point is further illustrated by FIG. 6 .
- FIG. 6 illustrates a circuit 600 having three loops 602 , 604 , 606 .
- Loop 602 starts at node A, goes to node B, and returns to node A.
- Loop 602 contains a single delay 603 .
- Loop 604 starts at node A, goes to node B, goes to node C, and returns to node A.
- Loop 604 contains two delays 605 .
- Loop 606 starts at node B, goes to node C, goes to node D, and returns to node B.
- Loop 606 also contains two delays 607 .
- the computation time of node A is 10 ns.
- the computation time of node B is 2 ns.
- the computation time of node C is 3 ns.
- the computation time of node D is 5 ns.
- the iteration bound of circuit 600 is 12 ns (i.e., the maximum of 12 ns, 7.5 ns, and 5 ns).
- every feedback loop of 64-to-1 multiplexer loop 400 is a critical loop.
- the iteration bound of 64-to-1 multiplexer loop 400 is the computation time of a single 2-to-1 multiplexer 402 .
- the example starts by assuming that a maximum clocking rate of 500 MHz can be achieved, using an available manufacturing technology. Given a maximum achievable clocking rate of 500 MHz, the clocking period of the example circuit will be 2 ns. It will be assumed for purposes of the example that an iteration bound of less than 1.7 ns must be achieved in order to provide sufficient operating margin or the circuit design will be unacceptable.
- FIG. 7 illustrates a 4-unfolded multiplexer loop circuit 700 , which is obtained from the 64-to-1 multiplexer loop circuit 400 shown in FIG. 4 .
- Circuit 700 contains several 2-to-1 multiplexers 402 and several delays 404 .
- the critical path of circuit 700 is illustrated by a dashed line 702 .
- the critical path involves nine 2-to-1 multiplexers 402 .
- circuit 700 does not satisfy the design criterion of having an iteration bound of less than 1.7 ns.
- retiming may be used to reduce the number of 2-to-1 multiplexers 402 in the critical path.
- FIG. 8 illustrates two cut-sets 802 , 804 that can be used to reduce the number of 2-to-1 multiplexers 402 in the critical path of circuit 700 .
- FIG. 9 illustrates the retimed 4-unfolded loop of FIG. 8 .
- the critical path shown by a dashed line 902
- the critical path now involves just four 2-to-1 multiplexers 402 .
- the four multiplexers (F 0 , F 1 , F 2 , and F 3 ) in the critical path are heavily loaded.
- the known techniques of unfolding and retiming cannot be applied to the nested loops of 64-to-1 multiplexer loop 400 . Applying these known techniques has led to an unacceptable circuit design.
- FIGS. 10 and 11 Another known technique that can be used to improve the iteration bound of a circuit is pipelining combined with look-ahead. This technique is illustrated by FIGS. 10 and 11 .
- FIG. 10 illustrates a 2-to-1 multiplexer loop circuit 1000 .
- the output, a n , of circuit 1000 is given by EQ. 3:
- a n A n * a n - 1 + B n * a _ n - 1 EQ . ⁇ 3
- FIG. 11 illustrates a circuit 1100 that can be formed by applying pipelining and look-ahead to circuit 1000 .
- Circuit 1100 has a delay 1102 , a multiplexer 1104 , and a multiplexer 1106 in addition to the multiplexer 1002 of circuit 1000 .
- the output of circuit 1100 is given by EQ. 5, which is obtained by substituting previous iterations of EQ. 3 and EQ. 4 in EQ. 3.
- the known method for applying pipelining and look-ahead to circuit 1000 has improved the iteration bound by a factor of 2.
- the present invention fills this void.
- FIG. 12A illustrates a 4-to-1 multiplexer loop circuit 1200 .
- Circuit 1200 can also be thought of as forming the first two stages of any multiplexer loop that is 4-to-1 or larger.
- the first stage consists of multiplexer 1202 a .
- the second stage consists of multiplexers 1202 b , 1202 c .
- the output of circuit 1200 is given by the following equations:
- a n E n ⁇ a n - 1 + F n ⁇ a _ n - 1
- a _ n E _ n ⁇ a n - 1 + F _ n ⁇ a _ n - 1 EQ . ⁇ 6c
- circuit 1200 has three multiplexers 1202 a , 1202 b , 1202 c , and two delay devices 1204 a , 1204 b .
- multiplexer 1202 a has a computation time of 0.4 ns (i.e., it is highly loaded) and the other two multiplexers 1202 b , 1202 c , each have a computation time of 0.2 ns, the iteration bound of circuit 1200 is 0.4 ns.
- circuits such as, for example, multiplexer loop circuit 1200 can be unfolded. Unfolding circuit 1200 permits parallel processing of circuit inputs.
- FIG. 12B illustrates an example 2-unfolded circuit 1210 obtained by unfolding the multiplexer loop circuit 1200 by a factor of two.
- Circuit 1210 has two parallel processing pipelines 1212 and 1214 .
- unfolding circuit 1200 increases the loading of multiplexer 1202 a .
- unfolding circuit 1200 has increased the iteration bound (i.e., the iteration bound of circuit 1210 is greater than the iteration bound of circuit 1200 ) since the output of multiplexer 1216 is dependent upon the output of multiplexer 1202 a.
- FIG. 12C illustrates an example 3-unfolded circuit 1220 obtained by unfolding the multiplexer loop circuit 1200 by a factor of three.
- Circuit 1220 has three parallel processing pipelines 1222 , 1224 , and 1226 .
- FIG. 12D illustrates an example digital processing circuit 1230 .
- Circuit 1230 includes a processing element 1232 and a delay 1234 .
- Processing element 1232 can be any known processing element or network.
- Delay 1234 is part of a feedback loop that includes processing element 1232 .
- FIG. 12E illustrates an example 3-unfolded digital processing circuit 1240 obtained by unfolding circuit 1230 by a factor of three using a conventional unfolding technique.
- This conventional unfolding technique involves adding two additional processing elements 1242 and 1244 to the feedback loop that includes processing element 1232 and delay 1234 .
- this conventional unfolding technique has increased the loading of processing element 1232 .
- This conventional unfolding technique has also produced a circuit having an increased iteration period.
- FIG. 12F illustrates an example digital processing circuit 1250 that includes a feedback loop having two delays.
- Circuit 1250 is obtained by adding an additional delay 1252 to the feedback loop of circuit 1230 in accordance with a technique of the invention. As described herein, adding additional delays to a feedback loop in conjunction with circuit unfolding can reduce or eliminate the fan-out and iteration bound issues associated with conventional unfolding techniques.
- FIG. 12G illustrates an example 3-unfolded digital processing circuit 1260 obtained by unfolding circuit 1250 by a factor of three in accordance with a first unfolding technique of the invention.
- This unfolding technique involves adding two additional processing elements 1262 and 1264 to the feedback loop that includes processing element 1232 and delays 1234 and 1252 .
- this unfolding technique of the invention has reduced the loading of processing element 1232 , and it has resulted is a better iteration period.
- FIG. 12H illustrates an example 4-unfolded digital processing circuit 1270 obtained by unfolding circuit 1250 by a factor of four in accordance with a second unfolding technique of the invention.
- This unfolding technique results in two independent processing networks.
- One processing network comprises processing elements 1232 and 1264 .
- the other processing network comprises processing elements 1262 and 1272 .
- this unfolding technique of the invention has reduced the loading of processing element 1232 , and it has resulted in a better iteration bound.
- FIG. 13 illustrates a circuit 1300 developed by applying one form of pipelining and look-ahead to circuit 1200 . As described herein, this conventional form does not improve the performance of circuit 1200 . It is shown only so that it can be contrasted with the present invention.
- circuit 1300 is formed by adding three delays 1302 , 1304 a , 1304 b , and two multiplexers 1306 a , 1306 b to circuit 1200 .
- the output of circuit 1300 is given by EQs. 7a and 7b.
- EQ. 7a is obtained by substituting past iterations of EQ. 6c in itself.
- FIG. 14 illustrates a circuit 1400 developed by applying a second form of pipelining and look-ahead to circuit 1200 .
- This form also is not very useful for improving the performance of circuit 1200 .
- This form is also shown so that it can be contrasted with the present invention.
- the output of circuit 1400 is given by EQs. 8a and 8b.
- EQ. 8a is obtained by substituting past iterations of EQ. 6a and EQ. 6c in EQ. 6a.
- a n ⁇ ( A n ⁇ a n - 2 + B n ⁇ a _ n - 2 ) ⁇ ( E n - 1 ⁇ a n - 2 + F n - 1 ⁇ a _ n - 2 ) + ⁇ ( C n ⁇ a n - 2 + D n ⁇ a _ n - 2 ) ⁇ ( E _ n - 1 ⁇ a n - 2 + F _ n - 1 ⁇ a _ n - 2 ) EQ .
- a n ( A n ⁇ E n - 1 + C n ⁇ E _ n - 1 ) a n - 2 + ( B n ⁇ F n - 1 + D n ⁇ F _ n - 1 ) a _ n - 2 EQ . ⁇ 8b
- the loop bound of the inner nested loop is 0.2 ns.
- the loop bound of the outer loop is 0.3 ns. While this is an improvement over the form illustrated by FIG. 13 , it still does not resolve the decreased performance of the multiplexer loop.
- applying this form of pipelining and look-ahead results in an expected iteration bound of about 1.2 ns, which is less than the 1.7 ns criterion. But, for reasons described herein, this iteration bound may not be achievable.
- the iteration bound can be reduced even further than this by applying the pipelining and look-ahead techniques of the invention. In comparison, the invention significantly increases the clock speed or symbol speed that can be achieved.
- the pipelining and look-ahead of FIG. 15A solves the issue of degraded multiplexer loop performance described above. This is because the loop bound of every feedback loop of the multiplexer loop is improved rather than just improving the performance of one loop to the detriment of another loop.
- FIG. 15A illustrates a circuit 1500 , according to an embodiment of the invention, that is formed by adding a delay 1502 and four 2-to-1 multiplexers 1504 a , 1504 b , 1504 c , 1504 d to circuit 1200 .
- each of the 2-to-1 multiplexers has two input ports, one control port. and one output port.
- none of the 2-to-1 multiplexers 1504 a , 1504 b , 1504 c , 1504 d is included in a feedback loop.
- These multiplexers form part of a 1-level look-ahead network 1506 .
- the extra delay added to circuit 1200 forms a part of the innermost nested loop.
- circuit 1500 The output of circuit 1500 is given by the following equations:
- the iteration bound of circuit 1500 is 0.2 ns.
- the pipelining and look-ahead of the invention increases the performance of the nested loop without degrading the performance of the outer loop.
- the invention can be used to restore the performance of the multiplexer loop to an expected level of performance (e.g., 0.2 ns).
- FIG. 15B illustrates an example 2-unfolded circuit 1510 obtained by unfolding the circuit of FIG. 15A by a factor of two in accordance with the invention.
- Circuit 1510 comprises a look-ahead circuit 1512 and two parallel processing pipelines 1514 and 1516 in accordance with the invention.
- FIG. 15C illustrates an example 3-unfolded circuit 1520 obtained by unfolding the circuit of FIG. 15A by a factor of three in accordance with the invention.
- Circuit 1520 comprises a look-ahead circuit 1522 and three parallel processing pipelines 1524 , 1526 , and 1528 in accordance with the invention.
- FIGS. 15D-1 and 15 D- 2 illustrate an example 4-unfolded circuit 1530 obtained by unfolding the circuit of FIG. 15A by a factor of four in accordance with the invention.
- Circuit 1530 comprises a look-ahead circuit 1532 and four parallel processing pipelines 1534 , 1536 , 1538 , and 1540 in accordance with the invention.
- FIG. 15E illustrates a circuit 1550 having a 3-level look-ahead network 1556 according to an embodiment of the invention.
- Circuit 1550 is formed by adding a delay 1552 and 3-level look-ahead network 1556 to circuit 1200 .
- each of the 2-to-1 multiplexers has two input ports, one control port, and one output port.
- the extra delay added to circuit 1200 forms a part of the innermost nested loop.
- 3-level look-ahead network 1556 is formed using multiplexers and delays. 3-level look-ahead network 1556 transforms the four input values A n , B n , C n , and D n into four intermediate values O 1 , O 2 , O 3 , and O 4 . As will be understood by persons skilled in the relevant arts, other circuits can be used to implement a 3-level look-ahead network.
- the invention can be implemented in a manner that will achieve an objective not obtainable by circuits 1300 and 1400 .
- the invention can be implemented in a multiplexer loop such that the performance degradation caused by the heavy loading of multiplexer 1202 a is completely eliminated without increasing the loop bound of any loop. This is achieved by adding delay to the innermost nested feedback loop and by not adding any multiplexers within a loop of the multiplexer loop.
- a benefit of adding delay to the innermost feedback loop is that it improves the loop bound of every loop forming a part of the multiplexer loop.
- FIG. 16 illustrates a 64-to-1 multiplexer loop circuit 1600 that incorporates the embodiment of invention shown in FIG. 15A .
- circuit 1600 is formed from multiplexer loop 400 and circuit 1500 .
- the iteration bound of circuit 1600 is 0.25 ns.
- look-ahead network 1506 If look-ahead network 1506 is moved to a position between multiplexers 402 c and 402 d , the iteration bound of circuit is not changed (i.e, it remains at 0.25 ns). The number of multiplexers included in look-ahead network 1506 , however, must be increased from 4 to 8.
- look-ahead network 1506 moving look-ahead network 1506 to a position between multiplexers 402 b and 402 c or to a position between multiplexers 402 a and 402 b also will not change the iteration bound of circuit 1600 .
- the number of multiplexers included in look-ahead network 1506 will have be increased from 4 to 16, or 4 to 32, respectfully.
- look-ahead network 1506 If look-ahead network 1506 is moved to a location before multiplexer 402 a , the iteration bound of circuit 1600 is reduced. It is reduced to 0.2 ns, and every loop of circuit 1600 becomes a critical loop. This design requires increasing the number of multiplexers of look-ahead network 1506 from 4 to 64. Thus, as can be seen from FIG. 16 , it is advantageous to position look-ahead network 1506 in front of multiplexer 402 a.
- FIG. 17 illustrates a 4-unfolded circuit 1700 having a critical path 1702 .
- Critical path 1702 is illustrated by a dashed line.
- circuit 1700 is formed using circuit 1600 .
- Circuit 1700 contains several 2-to-1 multiplexers 402 and several delays 404 .
- FIG. 18 illustrates two cut-sets 1802 , 1804 that can be used to reduce the number of 2-to-1 multiplexers in the critical path of the circuit of FIG. 17 . This will reduce the computation time of the circuit.
- FIG. 19 illustrates the retimed circuit of FIG. 16 .
- This retimed circuit has two critical paths 1902 , 1904 .
- a clock period of operation of 1.2 ns can be achieved (i.e., 1.0 ns+0.2 ns).
- the invention is not limited to a particular amount of look-ahead or a particular number of inputs-to-outputs, such as the 4-to-1 ratio illustrated in FIG. 15A .
- FIG. 20 illustrates an 8-to-1 multiplexer loop 2000 .
- Multiplexer loop 2000 is formed from a plurality of 2-to-1 multiplexers 2002 and a plurality of delays 2004 , as shown in FIG. 20 .
- the output of multiplexer loop 2000 is given by the following equations:
- a ′′ ⁇ ( n ) A ′ ⁇ ( n ) ⁇ a ⁇ ( n - 2 ) + B ′ ⁇ ( n ) ⁇ a _ ⁇ ( n - 2 )
- a _ ′′ ⁇ ( n ) A _ ′ ⁇ ( n ) ⁇ a ⁇ ( n - 2 ) + B _ ′ ⁇ ( n ) ⁇ a _ ⁇ ( n
- FIG. 21 illustrates a circuit 2100 formed by applying the look-ahead and pipelining of the invention to circuit 2000 .
- delay 2004 a has been replaced by a delay 2102
- a look-ahead network 2104 has been added.
- the benefits of circuit 2100 over circuit 2000 are the same as those already described herein for other circuits according to the invention.
- circuit 2100 The output of circuit 2100 is described by the following equations:
- a ⁇ ( n ) ⁇ a ⁇ ( n - 1 ) [ a ⁇ ( n - 2 ) ⁇ ⁇ a ⁇ ( n - 3 ) ⁇ A n + a _ ⁇ ( n - 3 ) ⁇ B n ⁇ + a _ ⁇ ( n - 2 ) ⁇ ⁇ a ⁇ ( n - 3 ) ⁇ C n + ⁇ a _ ⁇ ( n - 3 ) ⁇ D n ⁇ ] + a _ ⁇ ( n - 1 ) [ ( a ⁇ ( n - 2 ) ⁇ ⁇ a ⁇ ( n - 3 ) ⁇ E n + a _ ⁇ ( n - 3 ) ⁇ F n ⁇ + ⁇ a _ ⁇ ( n - 2 ) ⁇ ⁇ a ⁇ ( n - 3 ) ⁇ G n + a
- FIG. 22 illustrates a flowchart of the steps of a method 2200 for pipelining multiplexer loops according to an embodiment invention. As described herein, pipelined multiplexer loops according to the invention can be used to form part of an integrated circuit.
- Method 2200 has three steps 2202 , 2204 , 2206 . Each of these steps will now be described and illustrated with an example application.
- a number of input values is selected.
- the selected number of inputs is provided to a pipelined multiplexer loop according to the invention during a clock period of operation of an integrated circuit.
- the number of selected inputs can be used to identify a particular multiplexer loop that is to be modified in accordance with the invention.
- step 2204 a number of look-ahead steps is selected.
- the number of look-ahead steps is independent of the number of input values selected in step 2202 .
- the selected level of look-ahead is implemented as a part of the pipelined multiplexer loop according to the invention.
- a pipelined multiplexer loop according to the invention is implemented using, for example, a backplane or an optical/fiber technology.
- the pipelined multiplexer loop is implemented using at least one digital logic circuit according to the invention.
- the pipelined multiplexer is also implemented so that it has the number of look-ahead steps selected in step 2204 .
- the digital logic circuit has an n-level look-ahead network that converts the number of input values selected in step 2202 to a plurality of intermediate values, wherein n represents the number of look-ahead steps selected in step 2204 .
- the digital logic circuit is formed from a plurality of multiplexers each having a first and a second input port, an output port, and a control port. At least some of these multiplexers are arranged to form the pipelined multiplexer loop.
- the pipelined multiplexer loop has at least a first and a second stage.
- the first stage consists of a first multiplexer.
- the second stage consists of a second and a third multiplexer.
- a first communications link couples the output port of the second multiplexer to the first input port of the first multiplexer.
- a second communications link couples the output port of the third multiplexer to the second input port of the first multiplexer.
- a first feedback loop having a first delay time, couples the output port of the first multiplexer to the control port of the first multiplexer.
- a second feedback loop having a second delay time, couples the output port of the first multiplexer to the control ports of the second and third multiplexers.
- the first delay time is an integer multiple of the second delay time and is equal to (n+1) times a clock period of operation of the integrated circuit.
- method 2200 can be used to design or improve the performance of a wide variety of circuits.
- FIGS. 23-28 illustrate how method 2200 is applied to design and/or improve the performance of a DFE.
- FIG. 23 illustrates a serial representation of an example of a circuit that can be used as part of a digital communications system to remove inter-symbol interference (i.e., a DFE).
- the DFE is formed using an 8-to-1 multiplexer loop 2302 (similar to the 8-to-1 multiplexer loop 2000 described above) and several comparators 2308 .
- the multiplexers 2304 of the multiplexer loop are similar to those described above, each having an expected computation time of 0.2 ns.
- the multiplexer loop has three delays 2306 a , 2306 b , 2306 c.
- the DFE circuit of FIG. 23 can be determined after selecting, in step 2202 of method 2200 , the number of input values that need to be provided to a pipelined multiplexer loop during a clock period of operation of an integrated circuit. As shown in FIG. 23 , eight values are input to multiplexer loop 2302 . These input values are the outputs of the eight comparators 2308 . The comparators 2308 compare an input signal y n to eight possible feedback signals f 0 . . . f 7 . The eight feedback signals are given by the following equations:
- FIG. 24 illustrates an embodiment of the 3-tap DFE of FIG. 23 having pipelining and 2-levels of look-ahead in accordance with the invention.
- the circuit of FIG. 24 can be formed from the circuit of FIG. 23 by replacing delay 2306 a with a delay 2402 , and by adding 2-level look-ahead network 2404 .
- the delay 2402 forms a part of every loop of the multiplexer loop.
- no additional multiplexers were added to the loops of the multiplexer loop.
- 2-level look-ahead network 2404 has been placed before each of the multiplexers that form part of the multiplexer loop shown in FIG. 23 .
- FIG. 25 illustrates a detailed view of 2-level look-ahead network 2404 .
- 2-level look-ahead network 2404 is formed using multiplexers and delays.
- 2-level look-ahead network 2404 transforms eight input values A n , B n , C n , D n , E n , F n , G n , and H n , into eight intermediate values O 1 , O 2 , O 3 , O 4 , O 5 , O 6 , O 7 , and O 8 .
- other circuits can be used to implement a 2-level look-ahead network.
- circuit according to the invention can be used to form part of a larger integrated circuit.
- circuits according to the invention are combined with comparator circuits to form an integrated circuit.
- FIG. 26 illustrates a 4-unfolded comparator circuit 2600 with f i -latch and pipeline-registers.
- Circuit 2600 is formed using comparators 2602 , data flip-flops (DFF) 2604 , and latches (LAT) 2608 .
- Circuit 2600 can be used, for example, with a 4-unfolded and retimed circuit formed from the circuit of FIG. 24 .
- the circuit of FIG. 24 can be unfolded and retimed in a manner similar to that described above for the circuit of FIG. 16 .
- FIG. 27 illustrates a 6-bit compare circuit 2700 .
- Circuit 2700 can be modified, when required, to form an n-bit compare circuit. The operation of circuit 2700 is described by the following equations:
- FIG. 28 illustrates a serializer/deserializer that makes use of a 4-tap decision feedback equalizer integrated circuit 2800 according to an embodiment of the invention.
- Circuit 2800 is implemented using circuits similar to those described herein.
- Integrated circuit 2800 is illustrative and not intended to limit the invention.
- FIGS. 29A-B illustrate a flowchart of the steps of method 2900 according to an embodiment of the invention.
- Method 2900 is used to design high speed parallel processing circuits such as the ones described herein.
- high speed parallel processing circuits in accordance with the invention are designed in accordance with method 2900 as follows.
- a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected.
- a clocking rate (C) is selected for the digital circuit, wherein a product (P), P being equal to B times C, is equal to at least 1 gigabit per second.
- An initial circuit capable of serially processing the bits of the bit-stream at a data processing rate less than P is formed.
- This initial circuit includes a feedback loop having N+1 delays. N is a whole number greater than zero.
- the initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream.
- An N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines.
- the N-step look-ahead network is formed by forming an initial look-ahead network in conjunction with the initial circuit and unfolding the initial look-ahead network as described herein by a factor B.
- the unfolded circuit is retimed to achieve the selected clocking rate (C).
- method 2900 involves six steps. These steps will now be described in more detail.
- step 2902 a number of bits (B) of a bit-stream to be processed in parallel by a digital circuit is selected.
- the number of bits selected for parallel processing determines the level of parallelism of the circuit.
- a clocking rate (C) is selected for the digital circuit, wherein a product (P), P being equal to B times C, is equal to at least 1 gigabit per second.
- the clock rate (C) is selected in conjunction with the value of B, selected in step 2902 , so that B times C equals a desired system rate.
- the clock rate (C) equals 625 MHz (i.e., P/B equals 625,000 cycles/sec).
- a clock period (T) for the circuit equals 1.6 nanoseconds (ns).
- an initial circuit capable of serially or sequentially processing the bits of the bit-stream at a data processing rate less than P is formed.
- This initial circuit includes a feedback loop having N+1 delays, wherein N is a whole number greater than zero.
- the initial circuit is formed to have an innermost nested feedback loop, wherein the innermost nested feedback loop has N+1 delays.
- the initial circuit is formed using a multiplexer loop such as one of the multiplexer loops described above.
- the invention is not limited, however, to using a multiplexer loop to form the initial circuit.
- the initial circuit formed in step 2906 is not a final or complete circuit in accordance with the invention. Thus, the initial circuit formed in step 2906 is not intended to be built or manufactured.
- the initial circuit is unfolded by a factor of B to form B parallel processing pipelines for the bits of the bit-stream.
- the initial circuit is unfolded by a factor equal to the number of delays in the feedback loop.
- the initial circuit is unfolded by a factor less than the number of delays in the feedback loop.
- the initial circuit is unfolded by a factor greater than the number of delays in the feedback loop.
- the initial circuit can be unfolded to form at least two parallel processing circuits that are interconnected by a feedback loop. In some embodiments, however, the initial circuit is unfolded to form at least two parallel processing circuits that are not interconnected by a feedback loop. (See, e.g., FIGS. 12G and 12H ).
- an N-step look-ahead network is formed to provide inputs to the B parallel processing pipelines.
- look-ahead networks similar to those described and shown herein are used.
- the N-step look-ahead network is formed by forming an initial look-ahead network in conjunction with the initial circuit and unfolding the initial look-ahead network as described herein by a factor B.
- the N-step look-ahead network is formed apart from the initial circuit.
- step 2912 the unfolded circuit is retimed to achieve the selected clocking rate (C). How to retime an unfolded circuit is described above.
- the selected clocking rate (C) or clock period (T) can not be achieved by retiming the unfolded circuit, one can increase the number of delays in the feedback loop of the initial circuit, in an iterative manner, so that the corresponding unfolded and retimed circuit will achieve the selected clocking rate (C) or clock period (T).
- the unfolded and retimed circuit of step 2912 in combination with the N-step look-ahead network of step 2910 comprise a digital circuit according to an embodiment invention.
- circuits having additional unfolding such as, for example, 16-unfolded circuits can also be implemented in accordance with the invention.
- the example embodiments described herein are not intended to limit the invention. Using the invention and various degrees of unfolding, it is possible to build circuits according to the invention that operate, for example, at data rates in excess of 3 Gb/s, 5 Gb/s, and 10 Gb/s.
- the invention can be used in a wide variety of digital circuits to improve performance.
- the invention is used to improve the performance of computer processing systems having one or more nested feedback loops or multiplexer loops.
- Computer processing systems typically include microprocessors or microcontrollers having one or more instruction decoders, arithmetic logic units and/or other specialized circuits that contain multiplexers in a feedback loop. These feedback loops limit operating speed or processing speed.
- the invention can be used to improve the operating speed or processing speed of such circuits, and thereby improve system performance.
- Other types of digital circuits that can benefit from the invention will become apparent to persons skilled in the relevant arts given the description herein.
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Abstract
Description
where Tj is the loop computation time and Wj is the number of delays in the loop. This point is further illustrated by the circuit in
y(n)=a*y(n−2)+x(n) EQ. 2
Assuming that the combined computation time of
where c3, c2, and c1 are the three tap coefficients of the DFE. As described above, the present invention can be applied to
Claims (21)
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US10/147,049 US7333580B2 (en) | 2002-01-28 | 2002-05-17 | Pipelined parallel processing of feedback loops in a digital circuit |
EP03001717A EP1355462A3 (en) | 2002-01-28 | 2003-01-27 | Pipelined parallel processing of feedback loops in a decision feedback equaliser |
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US10/055,910 US7239652B2 (en) | 2002-01-28 | 2002-01-28 | Pipelining of multiplexer loops in a digital circuit |
US10/147,049 US7333580B2 (en) | 2002-01-28 | 2002-05-17 | Pipelined parallel processing of feedback loops in a digital circuit |
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EP1355462A2 (en) | 2003-10-22 |
EP1355462A3 (en) | 2006-10-04 |
US20030142698A1 (en) | 2003-07-31 |
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