Programmable data encryption engine
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 US7283628B2 US7283628B2 US10170267 US17026702A US7283628B2 US 7283628 B2 US7283628 B2 US 7283628B2 US 10170267 US10170267 US 10170267 US 17026702 A US17026702 A US 17026702A US 7283628 B2 US7283628 B2 US 7283628B2
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 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
 H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for blockwise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
 H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
 H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
 H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Abstract
Description
This application claims priority of U.S. provisional applications, GF2ALU, Stein et al., Ser. No. 60/334,662, filed Nov. 30, 2001 (AD239J), PROGRAMMABLE GF2ALU LINEAR FEEDBACK SHIFT REGISTER—INCOMING DATA SELECTION, Stein et al., Ser. No. 60/341,737, filed Dec. 18, 2001 (AD300J), METHOD FOR DATA ENCRYPTION STANDARD (DES) USING GF2ALU AND 8 WAY PARALLEL LUT, Stein et al., Ser. No. 60/341,711, filed Dec. 18, 2001 (AD297J), and 8 WAY PARALLEL LOOK UP TABLE, Stein et al., Ser. No. 60/355,337, filed Feb. 7, 2002 (AD305J).
This invention relates to a programmable data encryption engine for performing the cipher function of the data encryption standard (DES) and also the input permutation and reverse input permutation.
An encryption engine for performing the American National Standard Institute (ANSI) data encryption standard (DES) algorithm encipher and deciphers blocks of data, typically 64 bits (bit packet) using a key. Deciphering is accomplished using the same key that was used for encrypting but with the schedule of addressing the key bits altered so that the deciphering is the reverse of the encryption process. A block to be encrypted is subjected to an initial permutation, IP, and then to a complex key—dependent computation, and finally to a permutation IP^{−1 }that is the inverse of the initial permutation. The keydependent computation can be simply defined in terms of a function, f, called the cipher function. For example, after the initial permutation IP, the 64 bit data block is split into to 32 bit data blocks LO and RO. The permuted input block is then input to the cipher function f, which operates on two blocks, one of 32 bits and one of 48 bits. In performing the f function RO is subject to expansion permutation E, resulting in a 48 bit block which is XORed with a 48 bit key, the result of which is condensed from 48 bits back to 32 bits using eight selection functions S_{1}S_{8}, then subjected to permutation P that provides the cipher 32 bit output. The output form the last cipher function is submitted to the reverse initial permutation IP^{−1}. These functions and permutations are normally done in hardware such as application specific integrated (ASIC) circuits which are inflexible: they are dedicated to the specific functions and permutations designed into them. Software implementation would be advantageous because it would allow easy adaptations to emerging standards. However, in software, the increase in cycle time measured in mega instructions per second [mips] is prohibitive. To permute a single bit in a conventional controller or digital signal processor (DSP) three instructions are needed: extracting the bit (AND), shifting the bit to the right position and deposit (OR). Thus, just to accomplish permutation E (48 bits) and permutation P (32 bits) will require 240 cycles, plus at least three instructions per lookup in the eight selection functions (S_{1}S_{8}) which will require an additional 24 cycles for a total of 264 cycles to process one cipher function. In DES there are sixteen f functions to be performed i.e. 16×264=4,224 [cycles/bit packet] and in triple DES there are fortyeight to be performed i.e. 48×264=12,672 [cycles/bit packet]. Given a 10 megabit data stream coming over the internet or other data source which results in 10×10^{6}/64=156250 [bit packets/second]. Thus, 4,224×156250=660 [Mips] for a DES, and 1980 [Mips] for 3DES. For faster data input systems, e.g., modems at 40 megabit/second the time required is 7920 [Mips] all well beyond current processor capabilities.
It is therefore an object of this invention to provide an improved data encryption engine for performing the cipher function of the data encryption standard (DES).
It is a further object of this invention to provide such an improved programmable data encryption engine for performing the cipher function of the data encryption standard (DES) implementable in software.
It is a further object of this invention to provide such an improved programmable data encryption engine for performing the cipher function of the data encryption standard (DES) which is much faster by two orders of magnitude.
It is a further object of this invention to provide such an improved programmable data encryption engine for performing the cipher function of the data encryption standard (DES) which is extremely flexible and can be reprogrammed for many different permutations and applications.
The invention results from the realization that a faster more adaptable, programmable software implemented data encryption engine for performing the data encryption standard (DES) algorithm can be achieved using a Galois field linear transformer (GFLT) system to implement each permutation and a parallel lookup table to implement the selection functions (SBox) to accomplish the DES cipher key and E permutations in just one cycle and the entire cipher function in just three cycles.
This invention features a programmable data encryption engine for performing the cipher function of the data encryption standard (DES) algorithm including a Galois field linear transformer (GFLT) system responsive to a first input data block to execute an E permutation to obtain an expanded data block and combine it with a key to obtain a second larger intermediate data block in one cycle. The invention also further features a parallel lookup table system which implements the unique data encryption standard selection function(s) and condenses the second larger intermediate data block to a third data block similar to the first input data block in a second cycle and submits it to the Galois field linear transformer system to execute a second permutation in the third cycle resulting in a data encryption standard cipher function of the first input data block.
In a preferred embodiment the Galois field linear transformer system may include a first Galois field linear transformer circuit responsive to the first input data block and a second Galois field linear transformer circuit responsive to the third data block from the parallel lookup system. Each Galois field linear transformer circuit may include a matrix responsive to a number of input bits in one or more bit streams and may have a plurality of outputs for providing the Galois field linear transformation of those bits. The matrix may include a plurality of cells, each cell may include an exclusive OR logic circuit. An AND logic circuit may have an output connected to the exclusive OR logic circuit and an input connected to one of said input bits, and a programmable storage device may provide an input to its associated AND logic circuit for setting the matrix to obtain a multicycle Galois field linear transformation of the inputs in a single cycle. The Galois field linear transformer system may include a reconfigurable input Galois field linear transformer circuit. The reconfigurable input Galois field linear transformer may include a Galois field linear transformer having a matrix of cells, a plurality of storage planes for storing control patterns representing a number of different functions, a storage plane selector circuit for selecting a said storage plane representing a said function for enabling the cells of the matrix which define that function, and a reconfigurable input circuit for delivering input data to the enabled cells to apply that function to the input data. The parallel lookup table system may include a memory, a plurality of lookup tables stored in the memory, a row index register for holding the values to be looked up in the the lookup tables, a column index register for storing a value representing the starting address of each lookup table stored in the memory, and an address translation circuit responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the functions of those values in each lookup table. There may be a key generator system for selectively providing a plurality of keys to the Galois field linear transformer system. The key generator system may include a key register for storing the keys. The key generator system may include a key generator circuit responsive to a master key for generating the keys. The key generator circuit may include a Galois field linear transformer circuit. The key generator circuit may be included in Galois field linear transformer system. The Galois field linear transformer system may be a reconfigurable input Galois field linear transformer circuit with a plurality of storage planes, one associated with each of the permutations. The Galois field linear transformer system may be a reconfigurable input Galois field linear transformer circuit and may include a storage plane for defining the key generator circuit. The Galois field linear transformer system may include a set of key selector cells for combining the key with the expanded data block. The key selector cell may include a gate circuit for transmitting a data signal, and a latch circuit for selectively enabling the gate circuit to pass the data signal. The latch circuit may include a flipflop circuit. The gate circuit may include a pair of AND gates and an OR gate. The gate circuit may include a two to one mux circuit. The Galois field linear transformer system may include a storage plane for defining the initial permutation and the reverse initial permutation of the data encryption standard algorithm.
Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which:
Aside from the preferred embodiment or embodiments disclosed below, this invention is capable of other embodiments and of being practiced or being carried out in various ways. Thus, it is to be understood that the invention is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings.
DES data encryption engine 10 performs the standard DES algorithm. Encryption engine 10 receives a 64 bit word from input circuit 12 and, after the encryption algorithm is applied, delivers a 64 bit word to output circuit 14. The DES algorithm is a standard endorsed by the American National Standard Institute (ANSD and as shown in
Each of the iterations 20 receives one half of the 64 bit word or a 32 bit word in the R registers 22 and the other 32 bit word in the L registers 24. Each iteration is exactly the same and will be explained with respect to the first iteration 26. There it can be seen that register R_{0 } 28 receives one 32 bit word. Register L_{0 } 30 receives the other 32 bit word. The 32 bit word in R_{0 }register 28 is combined with 48 bit key word 32 in a cipher function circuit 34. The output from cipher function circuit 34 is delivered to exclusive OR circuit 36 where it is combined with the 32 bit word in L_{0 }register 24. The output of this iteration is delivered to the input of the next iteration: the output from R_{0 }register 28 is delivered to L_{1 }register 38, the output from exclusive OR circuit 36 is delivered to R_{1 }register 40. This continues through the rest of the sixteen iterations, after which the two 32 bit words are combined and the reverse initial permutation, IP^{−}, is effected at 18. The initial permutation IP, the reverse permutation IP^{−}, the keywords KS, and the manipulations occurring in the cipher function circuits are all clearly defined by the ANSI DES standards.
A typical cipher function circuit 34,
In accordance with this invention a programmable data base encryption engine 34 a,
The use of the GFLT circuits in accordance with this invention allows the E permutation and expansion and its combination with the keyword to be performed in one cycle; the contraction form 48 bits to 32 bits accompanied by the SBoxes permutation in a second cycle and the P permutation to be accomplished in a third cycle. Previous software implementations require 250 cycles or more to do that and while hardwired circuits could operate more quickly, they are not reconfigurable.
GFLT circuit 62,
Each cell as exemplified by cell 130 of matrix 102,
The ability of the GFLT circuit or system of this invention to perform permutation E and to combine it in exclusive OR circuit 46 with the key word 32 in one cycle is effected by the inclusion of a column of key elements 150 alongside the right most column of matrix 102,
Byte muxes 108122 and key cells 150 are controlled by a GFLT control word in GFLT control register 160,
The encryption key enable (Encryptkeyena) bit 166,
An enlarged view of a small portion of matrix 102 and the associated key cells is shown in
The performance of the selection function S box permutation and contraction of the 48 bit words to the 32 bit words as explained with respect to
Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. The words “including”, “comprising”, “having”, and “with” as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the subject application are not to be taken as the only possible embodiments.
Other embodiments will occur to those skilled in the art and are within the following claims:
Claims (37)
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US10170267 US7283628B2 (en)  20011130  20020612  Programmable data encryption engine 
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US10170267 US7283628B2 (en)  20011130  20020612  Programmable data encryption engine 
JP2003550046A JP4732688B2 (en)  20011130  20021202  Galois fieldintegration / integrated addition and multiplyaccumulate 
CN 02826084 CN100480986C (en)  20011130  20021202  Galois field multiply/ multiplyadd/multiply accumulate 
DE2002637108 DE60237108D1 (en)  20011130  20021202  Galois field multiplication / multiplicationaddition / multiplicationaccumulation 
PCT/US2002/038501 WO2003048921A1 (en)  20011130  20021202  Galois field multiply/multiplyadd multiply accumulate 
EP20020804489 EP1456745B1 (en)  20011130  20021202  Galois field multiply/multiplyadd/multiplyaccumulate 
JP2011033194A JP5266354B2 (en)  20011130  20110218  Galois fieldintegration / integrated addition and multiplyaccumulate unit 
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Cited By (12)
Publication number  Priority date  Publication date  Assignee  Title 

US20080019504A1 (en) *  20060620  20080124  Wei Han  Key Generation For Advanced Encryption Standard (AES) Decryption And The Like 
US20090177870A1 (en) *  20080103  20090709  Fleischer Bruce M  Method and System for a WiringEfficient Permute Unit 
US20100040226A1 (en) *  20080813  20100218  Ideguchi Kota  Device, program and method for generating hash values 
US20120042046A1 (en) *  20090325  20120216  Waldeck Technology Llc  Mobile private assisted location tracking 
US8577598B2 (en)  20060414  20131105  Scenera Technologies, Llc  System and method for presenting a computed route 
US20140019776A1 (en) *  20120701  20140116  Jerzy Lewak  Methods of providing fast search, analysis, and data retrieval of encrypted data without decryption 
US8650409B1 (en) *  20040915  20140211  Altera Corporation  FPGA configuration data scrambling using input multiplexers 
US9037564B2 (en)  20110429  20150519  Stephen Lesavich  Method and system for electronic content storage and retrieval with galois fields on cloud computing networks 
US9137250B2 (en)  20110429  20150915  Stephen Lesavich  Method and system for electronic content storage and retrieval using galois fields and information entropy on cloud computing networks 
US9361479B2 (en)  20110429  20160607  Stephen Lesavich  Method and system for electronic content storage and retrieval using Galois fields and geometric shapes on cloud computing networks 
US9366542B2 (en)  20050923  20160614  Scenera Technologies, Llc  System and method for selecting and presenting a route to a user 
US9569771B2 (en)  20110429  20170214  Stephen Lesavich  Method and system for storage and retrieval of blockchain blocks using galois fields 
Families Citing this family (22)
Publication number  Priority date  Publication date  Assignee  Title 

US6766345B2 (en)  20011130  20040720  Analog Devices, Inc.  Galois field multiplier system 
US7082452B2 (en) *  20011130  20060725  Analog Devices, Inc.  Galois field multiply/multiplyadd/multiply accumulate 
US7895253B2 (en) *  20011130  20110222  Analog Devices, Inc.  Compound Galois field engine and Galois field divider and square root engine and method 
US7269615B2 (en) *  20011218  20070911  Analog Devices, Inc.  Reconfigurable input Galois field linear transformer system 
US7508937B2 (en) *  20011218  20090324  Analog Devices, Inc.  Programmable data encryption engine for advanced encryption standard algorithm 
US6941446B2 (en) *  20020121  20050906  Analog Devices, Inc.  Single instruction multiple data array cell 
US7000090B2 (en) *  20020121  20060214  Analog Devices, Inc.  Center focused single instruction multiple data (SIMD) array system 
US6865661B2 (en) *  20020121  20050308  Analog Devices, Inc.  Reconfigurable single instruction multiple data array 
US6829694B2 (en) *  20020207  20041207  Analog Devices, Inc.  Reconfigurable parallel look up table system 
US7177891B2 (en) *  20021009  20070213  Analog Devices, Inc.  Compact Galois field multiplier engine 
US20040086114A1 (en) *  20021106  20040506  Sun Microsystems, Inc.  System and method for implementing DES permutation functions 
US7693928B2 (en) *  20030408  20100406  Analog Devices, Inc.  Galois field linear transformer trellis system 
US7421076B2 (en) *  20030917  20080902  Analog Devices, Inc.  Advanced encryption standard (AES) engine with real time Sbox generation 
KR100800468B1 (en) *  20040129  20050805  삼성전자주식회사  Hardware cryptographic engine and method improving power consumption and operation speed 
US20140081699A1 (en) *  20040213  20140320  Fis Financial Compliance Solutions, Llc  Systems and methods for monitoring and detecting fraudulent uses of business applications 
US20060171532A1 (en) *  20050203  20060803  Sanyo Electric Co., Ltd  Encryption Processing Circuit 
US8024551B2 (en)  20051026  20110920  Analog Devices, Inc.  Pipelined digital signal processor 
US7728744B2 (en) *  20051026  20100601  Analog Devices, Inc.  Variable length decoder system and method 
US8285972B2 (en) *  20051026  20121009  Analog Devices, Inc.  Lookup table addressing system and method 
US7890565B2 (en) *  20070430  20110215  Lsi Corporation  Efficient hardware implementation of tweakable block cipher 
US8301990B2 (en) *  20070927  20121030  Analog Devices, Inc.  Programmable compute unit with internal register and bit FIFO for executing Viterbi code 
US8966279B2 (en) *  20101221  20150224  Apple Inc.  Securing the implementation of a cryptographic process using key expansion 
Citations (79)
Publication number  Priority date  Publication date  Assignee  Title 

US3303477A (en)  19631008  19670207  Telefunken Patent  Apparatus for forming effective memory addresses 
US3805037A (en)  19720222  19740416  J Ellison  N{40 th power galois linear gate 
US4322577A (en) *  19771221  19820330  Braendstroem Hugo  Cryptosystem 
US4685132A (en) *  19850730  19870804  Sperry Corporation  Bent sequence code generator 
EP0238810A2 (en)  19860327  19870930  HewlettPackard Company  Method and system for facilitating instruction processing of a digital computer 
US4847801A (en)  19871026  19890711  Cyclotomics, Inc.  Compact galois field multiplier 
US4852098A (en)  19861022  19890725  ThomsonCsf  Polynomial operator in galois fields and a digital signal processor comprising an operator of this type 
US4918638A (en) *  19861015  19900417  Matsushita Electric Industrial Co., Ltd.  Multiplier in a galois field 
US4975867A (en)  19870626  19901204  Digital Equipment Corporation  Apparatus for dividing elements of a Galois Field GF (2QM) 
US5062057A (en)  19881209  19911029  EMachines Incorporated  Computer display controller with reconfigurable frame buffer memory 
US5095525A (en)  19890626  19920310  Rockwell International Corporation  Memory transformation apparatus and method 
US5101338A (en)  19880427  19920331  Nec Corporation  Memory access control device which can be formed by a reduced number of lsi's 
US5214763A (en)  19900510  19930525  International Business Machines Corporation  Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism 
US5379243A (en)  19920831  19950103  Comstream Corporation  Method and apparatus for performing finite field division 
US5386523A (en)  19920110  19950131  Digital Equipment Corporation  Addressing scheme for accessing a portion of a large memory space 
US5446850A (en)  19910115  19950829  International Business Machines Corporation  Crosscacheline compounding algorithm for scism processors 
US5502665A (en) *  19931120  19960326  Goldstar Co., Ltd.  Galois field multiplier 
US5642367A (en)  19940207  19970624  Mitsubishi Semiconductor America, Inc.  Finite field polynomial processing module for error control coding 
US5689452A (en)  19941031  19971118  University Of New Mexico  Method and apparatus for performing arithmetic in large galois field GF(2n) 
US5696941A (en)  19940202  19971209  Samsung Electronics Co., Ltd.  Device for converting data using lookup tables 
US5754563A (en)  19950911  19980519  Ecc Technologies, Inc.  Byteparallel system for implementing reedsolomon errorcorrecting codes 
US5832290A (en)  19940613  19981103  HewlettPackard Co.  Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems 
US5890800A (en)  19961011  19990406  Sgs Thomson Microelectronics  Method and device for the division of elements of a Galois field 
JPH11163262A (en)  19971127  19990618  Hitachi Ltd  Programmable integrated circuit 
JPH11212451A (en)  19980122  19990806  Dainippon Printing Co Ltd  Criptographic device 
US5964826A (en)  19980113  19991012  National Science Council  Division circuits based on powersum circuit for finite field GF(2m) 
US5996066A (en)  19961010  19991130  Sun Microsystems, Inc.  Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions 
US5996057A (en)  19980417  19991130  Apple  Data processing system and method of permutation with replication within a vector register file 
US5999959A (en)  19980218  19991207  Quantum Corporation  Galois field multiplier 
US6038577A (en)  19980109  20000314  Dspc Israel Ltd.  Efficient way to produce a delayed version of a maximum length sequence using a division circuit 
JP2000091435A (en)  19980911  20000331  Fuji Xerox Co Ltd  Electronic data processing system 
US6049815A (en)  19961230  20000411  Certicom Corp.  Method and apparatus for finite field multiplication 
GB2343281A (en)  19981030  20000503  Nec Corp  Programmable logic base cell and array 
US6067609A (en)  19980409  20000523  Teranex, Inc.  Pattern generation and shift plane operations for a mesh connected computer 
US6121791A (en)  19970613  20000919  Malleable Technologies, Inc.  Programmable logic datapath that may be used in a field programmable device 
US6138208A (en)  19980413  20001024  International Business Machines Corporation  Multiple level cache memory with overlapped L1 and L2 memory access 
US6141786A (en) *  19980604  20001031  Intenational Business Machines Corporation  Method and apparatus for performing arithmetic operations on Galois fields and their extensions 
JP2001034167A (en)  19990723  20010209  Toshiba Corp  Arithmetic unit and cryptogram processor 
US6199086B1 (en)  19971224  20010306  Motorola, Inc.  Circuit and method for decompressing compressed elliptic curve points 
US6199087B1 (en)  19980625  20010306  HewlettPackard Company  Apparatus and method for efficient arithmetic in finite fields through alternative representation 
US6199088B1 (en)  19980630  20010306  Quantum Corp.  Circuit for determining multiplicative inverses in certain galois fields 
US6208163B1 (en) *  19990225  20010327  Xilinx, Inc.  FPGA configurable logic block with multipurpose logic/memory circuit 
JP2001084242A (en)  19990910  20010330  Hitachi Ltd  Variable operation processor 
US6223320B1 (en)  19980210  20010424  International Business Machines Corporation  Efficient CRC generation utilizing parallel table lookup operations 
US6230179B1 (en)  19970418  20010508  Motorola, Inc.  Finite field multiplier with intrinsic modular reduction 
US6246768B1 (en)  19980506  20010612  Penta Security Systems, Inc.  Data encryption system for encrypting plaintext data 
US6279023B1 (en)  19971229  20010821  Maxtor Corporation  System for computing the multiplicative inverse of an element of a Galois field without using tables 
US6285607B1 (en)  19980327  20010904  Memory Corporation Plc  Memory system 
US6298136B1 (en) *  19960520  20011002  U.S. Philips Corporation  Cryptographic method and apparatus for nonlinearly merging a data block and a key 
US6317763B1 (en)  19961219  20011113  Vlsi Technology, Inc.  Circuits, barrel shifters, and methods of manipulating a bit pattern 
US20020003876A1 (en) *  20000608  20020110  YoungWon Lim  Encryption apparatus using data encryption standard algorithm 
US6343305B1 (en)  19990914  20020129  The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University  Methods and apparatus for multiplication in a galois field GF (2m), encoders and decoders using same 
US20020021802A1 (en) *  20000712  20020221  Hirofumi Muratani  Encryption apparatus, decryption appatatus, expanded key generating apparatus and method therefor, and recording medium 
US20020041685A1 (en)  20000922  20020411  Mcloone Maire Patricia  Data encryption apparatus 
US6377969B1 (en) *  19990423  20020423  General Dynamics Government Systems Corporation  Method for multiplication in Galois fields using programmable circuits 
US20020051537A1 (en) *  20000913  20020502  Rogaway Phillip W.  Method and apparatus for realizing a parallelizable variableinputlength pseudorandom function 
US6384713B1 (en)  20000421  20020507  Marvell International, Ltd.  Serial comparator 
US6389088B1 (en)  19970417  20020514  Itt Manufacturing Enterprises, Inc.  Synchronization and tracking in a digital communication system 
US6415030B2 (en) *  19950905  20020702  Mitsubishi Denki Kabushiki Kaisha  Data transformation apparatus and data transformation method 
US6434662B1 (en)  19991102  20020813  Juniper Networks, Inc.  System and method for searching an associative memory utilizing first and second hash functions 
EP1246389A1 (en)  20010327  20021002  Amphion Semiconductor Limited  Apparatus for selectably encrypting or decrypting data 
US20020147825A1 (en)  20010410  20021010  Yosef Stein  Parallel bit correlator 
US20020156823A1 (en)  20010228  20021024  LihJyh Weng  System for performing mulitplication and division in GF(2 2m) 
US20020159599A1 (en) *  20000309  20021031  Mitsuru Matsui  Block encryption device using auxiliary conversion 
US6480845B1 (en)  20000614  20021112  Bull Hn Information Systems Inc.  Method and data processing system for emulating virtual memory working spaces 
US20030039355A1 (en)  20010511  20030227  Mccanny John Vincent  Computer useable product for generating data encryption/decryption apparatus 
US6539477B1 (en)  20000303  20030325  Chameleon Systems, Inc.  System and method for control synthesis using a reachable states lookup table 
US20030105791A1 (en)  20011130  20030605  Yosef Stein  Galois field multiplier system 
US20030110196A1 (en)  20011130  20030612  Yosef Stein  Galois field multiply/ multiplyadd/multiply accumulate 
US20030115234A1 (en)  20011218  20030619  Yosef Stein  Reconfigurable input Galois field linear transformer system 
US6587864B2 (en)  20011130  20030701  Analog Devices, Inc.  Galois field linear transformer 
US20030133568A1 (en)  20011218  20030717  Yosef Stein  Programmable data encryption engine for advanced encryption standard algorithm 
US20030140213A1 (en)  20020121  20030724  Yosef Stein  Center focused single instruction multiple data (SIMD) array system 
US20030140211A1 (en)  20020121  20030724  Yosef Stein  Reconfigurable single instruction multiple data array 
US20030140212A1 (en)  20020121  20030724  Yosef Stein  Single instruction multiple data array cell 
US20030149857A1 (en)  20020207  20030807  Yosef Stein  Reconfigurable parallel look up table system 
US6766344B2 (en) *  20010508  20040720  International Business Machines Corporation  Processing Galois Field arithmetic 
US20040210618A1 (en)  20030408  20041021  Yosef Stein  Galois field linear transformer trellis system 
US20050058285A1 (en)  20030917  20050317  Yosef Stein  Advanced encryption standard (AES) engine with real time Sbox generation 
Family Cites Families (1)
Publication number  Priority date  Publication date  Assignee  Title 

DE1905101C3 (en) *  19690201  19780622  Bayer Ag, 5090 Leverkusen 
Patent Citations (83)
Publication number  Priority date  Publication date  Assignee  Title 

US3303477A (en)  19631008  19670207  Telefunken Patent  Apparatus for forming effective memory addresses 
US3805037A (en)  19720222  19740416  J Ellison  N{40 th power galois linear gate 
US4322577A (en) *  19771221  19820330  Braendstroem Hugo  Cryptosystem 
US4685132A (en) *  19850730  19870804  Sperry Corporation  Bent sequence code generator 
US4722050A (en)  19860327  19880126  HewlettPackard Company  Method and apparatus for facilitating instruction processing of a digital computer 
EP0238810A2 (en)  19860327  19870930  HewlettPackard Company  Method and system for facilitating instruction processing of a digital computer 
US4918638A (en) *  19861015  19900417  Matsushita Electric Industrial Co., Ltd.  Multiplier in a galois field 
US4852098A (en)  19861022  19890725  ThomsonCsf  Polynomial operator in galois fields and a digital signal processor comprising an operator of this type 
US4975867A (en)  19870626  19901204  Digital Equipment Corporation  Apparatus for dividing elements of a Galois Field GF (2QM) 
US4847801A (en)  19871026  19890711  Cyclotomics, Inc.  Compact galois field multiplier 
US5101338A (en)  19880427  19920331  Nec Corporation  Memory access control device which can be formed by a reduced number of lsi's 
US5062057A (en)  19881209  19911029  EMachines Incorporated  Computer display controller with reconfigurable frame buffer memory 
US5095525A (en)  19890626  19920310  Rockwell International Corporation  Memory transformation apparatus and method 
US5214763A (en)  19900510  19930525  International Business Machines Corporation  Digital computer system capable of processing two or more instructions in parallel and having a coche and instruction compounding mechanism 
US5446850A (en)  19910115  19950829  International Business Machines Corporation  Crosscacheline compounding algorithm for scism processors 
US5386523A (en)  19920110  19950131  Digital Equipment Corporation  Addressing scheme for accessing a portion of a large memory space 
US5379243A (en)  19920831  19950103  Comstream Corporation  Method and apparatus for performing finite field division 
US5502665A (en) *  19931120  19960326  Goldstar Co., Ltd.  Galois field multiplier 
US5696941A (en)  19940202  19971209  Samsung Electronics Co., Ltd.  Device for converting data using lookup tables 
US5642367A (en)  19940207  19970624  Mitsubishi Semiconductor America, Inc.  Finite field polynomial processing module for error control coding 
US5832290A (en)  19940613  19981103  HewlettPackard Co.  Apparatus, systems and method for improving memory bandwidth utilization in vector processing systems 
US5689452A (en)  19941031  19971118  University Of New Mexico  Method and apparatus for performing arithmetic in large galois field GF(2n) 
US6415030B2 (en) *  19950905  20020702  Mitsubishi Denki Kabushiki Kaisha  Data transformation apparatus and data transformation method 
US5754563A (en)  19950911  19980519  Ecc Technologies, Inc.  Byteparallel system for implementing reedsolomon errorcorrecting codes 
US6298136B1 (en) *  19960520  20011002  U.S. Philips Corporation  Cryptographic method and apparatus for nonlinearly merging a data block and a key 
US5996066A (en)  19961010  19991130  Sun Microsystems, Inc.  Partitioned multiply and add/subtract instruction for CPU with integrated graphics functions 
US5890800A (en)  19961011  19990406  Sgs Thomson Microelectronics  Method and device for the division of elements of a Galois field 
US6317763B1 (en)  19961219  20011113  Vlsi Technology, Inc.  Circuits, barrel shifters, and methods of manipulating a bit pattern 
US6049815A (en)  19961230  20000411  Certicom Corp.  Method and apparatus for finite field multiplication 
US6389088B1 (en)  19970417  20020514  Itt Manufacturing Enterprises, Inc.  Synchronization and tracking in a digital communication system 
US6230179B1 (en)  19970418  20010508  Motorola, Inc.  Finite field multiplier with intrinsic modular reduction 
US6349318B1 (en)  19970418  20020219  Certicom Corp.  Arithmetic processor for finite field and module integer arithmetic operations 
US6121791A (en)  19970613  20000919  Malleable Technologies, Inc.  Programmable logic datapath that may be used in a field programmable device 
JPH11163262A (en)  19971127  19990618  Hitachi Ltd  Programmable integrated circuit 
US6199086B1 (en)  19971224  20010306  Motorola, Inc.  Circuit and method for decompressing compressed elliptic curve points 
US6279023B1 (en)  19971229  20010821  Maxtor Corporation  System for computing the multiplicative inverse of an element of a Galois field without using tables 
US6038577A (en)  19980109  20000314  Dspc Israel Ltd.  Efficient way to produce a delayed version of a maximum length sequence using a division circuit 
US5964826A (en)  19980113  19991012  National Science Council  Division circuits based on powersum circuit for finite field GF(2m) 
JPH11212451A (en)  19980122  19990806  Dainippon Printing Co Ltd  Criptographic device 
US6223320B1 (en)  19980210  20010424  International Business Machines Corporation  Efficient CRC generation utilizing parallel table lookup operations 
US5999959A (en)  19980218  19991207  Quantum Corporation  Galois field multiplier 
US6285607B1 (en)  19980327  20010904  Memory Corporation Plc  Memory system 
US6067609A (en)  19980409  20000523  Teranex, Inc.  Pattern generation and shift plane operations for a mesh connected computer 
US6138208A (en)  19980413  20001024  International Business Machines Corporation  Multiple level cache memory with overlapped L1 and L2 memory access 
US5996057A (en)  19980417  19991130  Apple  Data processing system and method of permutation with replication within a vector register file 
US6246768B1 (en)  19980506  20010612  Penta Security Systems, Inc.  Data encryption system for encrypting plaintext data 
US6141786A (en) *  19980604  20001031  Intenational Business Machines Corporation  Method and apparatus for performing arithmetic operations on Galois fields and their extensions 
US6199087B1 (en)  19980625  20010306  HewlettPackard Company  Apparatus and method for efficient arithmetic in finite fields through alternative representation 
US6199088B1 (en)  19980630  20010306  Quantum Corp.  Circuit for determining multiplicative inverses in certain galois fields 
JP2000091435A (en)  19980911  20000331  Fuji Xerox Co Ltd  Electronic data processing system 
GB2343281A (en)  19981030  20000503  Nec Corp  Programmable logic base cell and array 
US6208163B1 (en) *  19990225  20010327  Xilinx, Inc.  FPGA configurable logic block with multipurpose logic/memory circuit 
US6377969B1 (en) *  19990423  20020423  General Dynamics Government Systems Corporation  Method for multiplication in Galois fields using programmable circuits 
JP2001034167A (en)  19990723  20010209  Toshiba Corp  Arithmetic unit and cryptogram processor 
JP2001084242A (en)  19990910  20010330  Hitachi Ltd  Variable operation processor 
US6343305B1 (en)  19990914  20020129  The State Of Oregon Acting By And Through The State Board Of Higher Education On Behalf Of Oregon State University  Methods and apparatus for multiplication in a galois field GF (2m), encoders and decoders using same 
US6434662B1 (en)  19991102  20020813  Juniper Networks, Inc.  System and method for searching an associative memory utilizing first and second hash functions 
US6539477B1 (en)  20000303  20030325  Chameleon Systems, Inc.  System and method for control synthesis using a reachable states lookup table 
US20020159599A1 (en) *  20000309  20021031  Mitsuru Matsui  Block encryption device using auxiliary conversion 
US6384713B1 (en)  20000421  20020507  Marvell International, Ltd.  Serial comparator 
US20020003876A1 (en) *  20000608  20020110  YoungWon Lim  Encryption apparatus using data encryption standard algorithm 
US6480845B1 (en)  20000614  20021112  Bull Hn Information Systems Inc.  Method and data processing system for emulating virtual memory working spaces 
US20020021802A1 (en) *  20000712  20020221  Hirofumi Muratani  Encryption apparatus, decryption appatatus, expanded key generating apparatus and method therefor, and recording medium 
US20020051537A1 (en) *  20000913  20020502  Rogaway Phillip W.  Method and apparatus for realizing a parallelizable variableinputlength pseudorandom function 
US20020041685A1 (en)  20000922  20020411  Mcloone Maire Patricia  Data encryption apparatus 
US20020156823A1 (en)  20010228  20021024  LihJyh Weng  System for performing mulitplication and division in GF(2 2m) 
US6779011B2 (en)  20010228  20040817  Maxtor Corporation  System for performing multiplication and division in GF(22M) 
US20030053623A1 (en) *  20010327  20030320  Mccanny John Vincent  Apparatus for selectably encrypting or decrypting data 
EP1246389A1 (en)  20010327  20021002  Amphion Semiconductor Limited  Apparatus for selectably encrypting or decrypting data 
US20020147825A1 (en)  20010410  20021010  Yosef Stein  Parallel bit correlator 
US6766344B2 (en) *  20010508  20040720  International Business Machines Corporation  Processing Galois Field arithmetic 
US20030039355A1 (en)  20010511  20030227  Mccanny John Vincent  Computer useable product for generating data encryption/decryption apparatus 
US20030105791A1 (en)  20011130  20030605  Yosef Stein  Galois field multiplier system 
US20030110196A1 (en)  20011130  20030612  Yosef Stein  Galois field multiply/ multiplyadd/multiply accumulate 
US6587864B2 (en)  20011130  20030701  Analog Devices, Inc.  Galois field linear transformer 
US20030133568A1 (en)  20011218  20030717  Yosef Stein  Programmable data encryption engine for advanced encryption standard algorithm 
US20030115234A1 (en)  20011218  20030619  Yosef Stein  Reconfigurable input Galois field linear transformer system 
US20030140212A1 (en)  20020121  20030724  Yosef Stein  Single instruction multiple data array cell 
US20030140211A1 (en)  20020121  20030724  Yosef Stein  Reconfigurable single instruction multiple data array 
US20030140213A1 (en)  20020121  20030724  Yosef Stein  Center focused single instruction multiple data (SIMD) array system 
US20030149857A1 (en)  20020207  20030807  Yosef Stein  Reconfigurable parallel look up table system 
US20040210618A1 (en)  20030408  20041021  Yosef Stein  Galois field linear transformer trellis system 
US20050058285A1 (en)  20030917  20050317  Yosef Stein  Advanced encryption standard (AES) engine with real time Sbox generation 
NonPatent Citations (13)
Title 

elixent Application Note JPEG Codec (Dec. 9, 2002) <http://www.elixent.com/assets/jpegcoder.pdf> (elixentBristol, UK). 
elixent, Changing the Electronic Landscape (2001) <http://www.elixent.com> (elixentBristol, UK). 
Horng et al., IEEE, Fast Inverters and Dividers for Finite Field FG(2m), 1994 pp. 206211. 
Huang et al., HighSpeed Easily Testable GaloisField Inverter, Sep. 2000, IEEE Transactions on Circuits and SystemsII: Analog and Digital Signal Processing, vol. 48, No. 9, pp. 909918. 
Máire McLoone and J.V. McCanny, High Performance SingleChip FPGA Rijndael Algorithm Implementations, CHES 2001 Proc, LNCS 2162, 6576 (C.K. Koç et al. eds. May 16, 2001). 
McCanny et al., Foreign applicaiton (GB 0107592.8) for U.S. Appl. No. 2003/0053623, Mar. 27, 2001. * 
McCanny et al., Foreign application (GB 0108392.2) for U.S. Appl. No. 2003/0053623, Apr. 4, 2001. * 
PACT Informationstechnologie GmbH, The XPP White Paper Release 2.1 (Mar. 27, 2002) <http://www.pactcorp.com/xneu/download/xpp<SUB></SUB>white<SUB></SUB>paper.pdf> (PACT XPPSanta Clara, CA). 
Popovici et al., IEEE, Electronics Letters, Division Algorithm over GF(2m), Sep. 17, 1998, pp. 18431844. 
U.S. Appl. No. 10/395,620, filed Mar. 24, 2003, Stein et al. 
U.S. Appl. No. 10/440,330, filed May 16, 2003, Stein et al. 
V. Baumgarte et al., PACT XPPA SelfReconfigurable Data Processing Architecture (Jun. 2001) <http://www.pactcorp.com/xneu/download/ersa01.pdf> (PACT XPPSanta Clara, CA). 
Viktor Fischer, Realization of the Round 2 AES Candidates Using Altera FPGA, (Jan. 26, 2001) <http://esrc.nist.gov/CryptoToolkit/aes/roun2/conf3/papers/24vfischer.pdf> (MicronicKosice, Slovakia). 
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US9366542B2 (en)  20050923  20160614  Scenera Technologies, Llc  System and method for selecting and presenting a route to a user 
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US20080019504A1 (en) *  20060620  20080124  Wei Han  Key Generation For Advanced Encryption Standard (AES) Decryption And The Like 
US7702100B2 (en) *  20060620  20100420  Lattice Semiconductor Corporation  Key generation for advanced encryption standard (AES) Decryption and the like 
US8069195B2 (en) *  20080103  20111129  International Business Machines Corporation  Method and system for a wiringefficient permute unit 
US20090177870A1 (en) *  20080103  20090709  Fleischer Bruce M  Method and System for a WiringEfficient Permute Unit 
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US9082077B2 (en) *  20090325  20150714  Waldeck Technology, Llc  Mobile private assisted location tracking 
US20120042046A1 (en) *  20090325  20120216  Waldeck Technology Llc  Mobile private assisted location tracking 
US9140566B1 (en)  20090325  20150922  Waldeck Technology, Llc  Passive crowdsourced map updates and alternative route recommendations 
US9569771B2 (en)  20110429  20170214  Stephen Lesavich  Method and system for storage and retrieval of blockchain blocks using galois fields 
US9137250B2 (en)  20110429  20150915  Stephen Lesavich  Method and system for electronic content storage and retrieval using galois fields and information entropy on cloud computing networks 
US9361479B2 (en)  20110429  20160607  Stephen Lesavich  Method and system for electronic content storage and retrieval using Galois fields and geometric shapes on cloud computing networks 
US9037564B2 (en)  20110429  20150519  Stephen Lesavich  Method and system for electronic content storage and retrieval with galois fields on cloud computing networks 
US20140019776A1 (en) *  20120701  20140116  Jerzy Lewak  Methods of providing fast search, analysis, and data retrieval of encrypted data without decryption 
US8959365B2 (en) *  20120701  20150217  Speedtrack, Inc.  Methods of providing fast search, analysis, and data retrieval of encrypted data without decryption 
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