US7283628B2  Programmable data encryption engine  Google Patents
Programmable data encryption engineInfo
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 US7283628B2 US7283628B2 US10170267 US17026702A US7283628B2 US 7283628 B2 US7283628 B2 US 7283628B2 US 10170267 US10170267 US 10170267 US 17026702 A US17026702 A US 17026702A US 7283628 B2 US7283628 B2 US 7283628B2
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 data encryption
 field linear
 encryption engine
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 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication
 H04L9/06—Cryptographic mechanisms or cryptographic arrangements for secret or secure communication the encryption apparatus using shift registers or memories for blockwise or stream coding, e.g. DES systems or RC4; Hash functions; Pseudorandom sequence generators
 H04L9/0618—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation
 H04L9/0625—Block ciphers, i.e. encrypting groups of characters of a plain text message using fixed encryption transformation with splitting of the data block into left and right halves, e.g. Feistel based algorithms, DES, FEAL, IDEA or KASUMI

 H—ELECTRICITY
 H04—ELECTRIC COMMUNICATION TECHNIQUE
 H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
 H04L2209/00—Additional information or applications relating to cryptographic mechanisms or cryptographic arrangements for secret or secure communication H04L9/00
 H04L2209/12—Details relating to cryptographic hardware or logic circuitry
Abstract
Description
This application claims priority of U.S. provisional applications, GF2ALU, Stein et al., Ser. No. 60/334,662, filed Nov. 30, 2001 (AD239J), PROGRAMMABLE GF2ALU LINEAR FEEDBACK SHIFT REGISTER—INCOMING DATA SELECTION, Stein et al., Ser. No. 60/341,737, filed Dec. 18, 2001 (AD300J), METHOD FOR DATA ENCRYPTION STANDARD (DES) USING GF2ALU AND 8 WAY PARALLEL LUT, Stein et al., Ser. No. 60/341,711, filed Dec. 18, 2001 (AD297J), and 8 WAY PARALLEL LOOK UP TABLE, Stein et al., Ser. No. 60/355,337, filed Feb. 7, 2002 (AD305J).
This invention relates to a programmable data encryption engine for performing the cipher function of the data encryption standard (DES) and also the input permutation and reverse input permutation.
An encryption engine for performing the American National Standard Institute (ANSI) data encryption standard (DES) algorithm encipher and deciphers blocks of data, typically 64 bits (bit packet) using a key. Deciphering is accomplished using the same key that was used for encrypting but with the schedule of addressing the key bits altered so that the deciphering is the reverse of the encryption process. A block to be encrypted is subjected to an initial permutation, IP, and then to a complex key—dependent computation, and finally to a permutation IP^{−1 }that is the inverse of the initial permutation. The keydependent computation can be simply defined in terms of a function, f, called the cipher function. For example, after the initial permutation IP, the 64 bit data block is split into to 32 bit data blocks LO and RO. The permuted input block is then input to the cipher function f, which operates on two blocks, one of 32 bits and one of 48 bits. In performing the f function RO is subject to expansion permutation E, resulting in a 48 bit block which is XORed with a 48 bit key, the result of which is condensed from 48 bits back to 32 bits using eight selection functions S_{1}S_{8}, then subjected to permutation P that provides the cipher 32 bit output. The output form the last cipher function is submitted to the reverse initial permutation IP^{−1}. These functions and permutations are normally done in hardware such as application specific integrated (ASIC) circuits which are inflexible: they are dedicated to the specific functions and permutations designed into them. Software implementation would be advantageous because it would allow easy adaptations to emerging standards. However, in software, the increase in cycle time measured in mega instructions per second [mips] is prohibitive. To permute a single bit in a conventional controller or digital signal processor (DSP) three instructions are needed: extracting the bit (AND), shifting the bit to the right position and deposit (OR). Thus, just to accomplish permutation E (48 bits) and permutation P (32 bits) will require 240 cycles, plus at least three instructions per lookup in the eight selection functions (S_{1}S_{8}) which will require an additional 24 cycles for a total of 264 cycles to process one cipher function. In DES there are sixteen f functions to be performed i.e. 16×264=4,224 [cycles/bit packet] and in triple DES there are fortyeight to be performed i.e. 48×264=12,672 [cycles/bit packet]. Given a 10 megabit data stream coming over the internet or other data source which results in 10×10^{6}/64=156250 [bit packets/second]. Thus, 4,224×156250=660 [Mips] for a DES, and 1980 [Mips] for 3DES. For faster data input systems, e.g., modems at 40 megabit/second the time required is 7920 [Mips] all well beyond current processor capabilities.
It is therefore an object of this invention to provide an improved data encryption engine for performing the cipher function of the data encryption standard (DES).
It is a further object of this invention to provide such an improved programmable data encryption engine for performing the cipher function of the data encryption standard (DES) implementable in software.
It is a further object of this invention to provide such an improved programmable data encryption engine for performing the cipher function of the data encryption standard (DES) which is much faster by two orders of magnitude.
It is a further object of this invention to provide such an improved programmable data encryption engine for performing the cipher function of the data encryption standard (DES) which is extremely flexible and can be reprogrammed for many different permutations and applications.
The invention results from the realization that a faster more adaptable, programmable software implemented data encryption engine for performing the data encryption standard (DES) algorithm can be achieved using a Galois field linear transformer (GFLT) system to implement each permutation and a parallel lookup table to implement the selection functions (SBox) to accomplish the DES cipher key and E permutations in just one cycle and the entire cipher function in just three cycles.
This invention features a programmable data encryption engine for performing the cipher function of the data encryption standard (DES) algorithm including a Galois field linear transformer (GFLT) system responsive to a first input data block to execute an E permutation to obtain an expanded data block and combine it with a key to obtain a second larger intermediate data block in one cycle. The invention also further features a parallel lookup table system which implements the unique data encryption standard selection function(s) and condenses the second larger intermediate data block to a third data block similar to the first input data block in a second cycle and submits it to the Galois field linear transformer system to execute a second permutation in the third cycle resulting in a data encryption standard cipher function of the first input data block.
In a preferred embodiment the Galois field linear transformer system may include a first Galois field linear transformer circuit responsive to the first input data block and a second Galois field linear transformer circuit responsive to the third data block from the parallel lookup system. Each Galois field linear transformer circuit may include a matrix responsive to a number of input bits in one or more bit streams and may have a plurality of outputs for providing the Galois field linear transformation of those bits. The matrix may include a plurality of cells, each cell may include an exclusive OR logic circuit. An AND logic circuit may have an output connected to the exclusive OR logic circuit and an input connected to one of said input bits, and a programmable storage device may provide an input to its associated AND logic circuit for setting the matrix to obtain a multicycle Galois field linear transformation of the inputs in a single cycle. The Galois field linear transformer system may include a reconfigurable input Galois field linear transformer circuit. The reconfigurable input Galois field linear transformer may include a Galois field linear transformer having a matrix of cells, a plurality of storage planes for storing control patterns representing a number of different functions, a storage plane selector circuit for selecting a said storage plane representing a said function for enabling the cells of the matrix which define that function, and a reconfigurable input circuit for delivering input data to the enabled cells to apply that function to the input data. The parallel lookup table system may include a memory, a plurality of lookup tables stored in the memory, a row index register for holding the values to be looked up in the the lookup tables, a column index register for storing a value representing the starting address of each lookup table stored in the memory, and an address translation circuit responsive to the column index register and the row index register to simultaneously generate an address for each value in the row index register to locate in parallel the functions of those values in each lookup table. There may be a key generator system for selectively providing a plurality of keys to the Galois field linear transformer system. The key generator system may include a key register for storing the keys. The key generator system may include a key generator circuit responsive to a master key for generating the keys. The key generator circuit may include a Galois field linear transformer circuit. The key generator circuit may be included in Galois field linear transformer system. The Galois field linear transformer system may be a reconfigurable input Galois field linear transformer circuit with a plurality of storage planes, one associated with each of the permutations. The Galois field linear transformer system may be a reconfigurable input Galois field linear transformer circuit and may include a storage plane for defining the key generator circuit. The Galois field linear transformer system may include a set of key selector cells for combining the key with the expanded data block. The key selector cell may include a gate circuit for transmitting a data signal, and a latch circuit for selectively enabling the gate circuit to pass the data signal. The latch circuit may include a flipflop circuit. The gate circuit may include a pair of AND gates and an OR gate. The gate circuit may include a two to one mux circuit. The Galois field linear transformer system may include a storage plane for defining the initial permutation and the reverse initial permutation of the data encryption standard algorithm.
Other objects, features and advantages will occur to those skilled in the art from the following description of a preferred embodiment and the accompanying drawings, in which:
Aside from the preferred embodiment or embodiments disclosed below, this invention is capable of other embodiments and of being practiced or being carried out in various ways. Thus, it is to be understood that the invention is not limited in its application to the details of construction and the arrangements of components set forth in the following description or illustrated in the drawings.
DES data encryption engine 10 performs the standard DES algorithm. Encryption engine 10 receives a 64 bit word from input circuit 12 and, after the encryption algorithm is applied, delivers a 64 bit word to output circuit 14. The DES algorithm is a standard endorsed by the American National Standard Institute (ANSD and as shown in
Each of the iterations 20 receives one half of the 64 bit word or a 32 bit word in the R registers 22 and the other 32 bit word in the L registers 24. Each iteration is exactly the same and will be explained with respect to the first iteration 26. There it can be seen that register R_{0 } 28 receives one 32 bit word. Register L_{0 } 30 receives the other 32 bit word. The 32 bit word in R_{0 }register 28 is combined with 48 bit key word 32 in a cipher function circuit 34. The output from cipher function circuit 34 is delivered to exclusive OR circuit 36 where it is combined with the 32 bit word in L_{0 }register 24. The output of this iteration is delivered to the input of the next iteration: the output from R_{0 }register 28 is delivered to L_{1 }register 38, the output from exclusive OR circuit 36 is delivered to R_{1 }register 40. This continues through the rest of the sixteen iterations, after which the two 32 bit words are combined and the reverse initial permutation, IP^{−}, is effected at 18. The initial permutation IP, the reverse permutation IP^{−}, the keywords KS, and the manipulations occurring in the cipher function circuits are all clearly defined by the ANSI DES standards.
A typical cipher function circuit 34,
In accordance with this invention a programmable data base encryption engine 34 a,
The use of the GFLT circuits in accordance with this invention allows the E permutation and expansion and its combination with the keyword to be performed in one cycle; the contraction form 48 bits to 32 bits accompanied by the SBoxes permutation in a second cycle and the P permutation to be accomplished in a third cycle. Previous software implementations require 250 cycles or more to do that and while hardwired circuits could operate more quickly, they are not reconfigurable.
GFLT circuit 62,
Each cell as exemplified by cell 130 of matrix 102,
The ability of the GFLT circuit or system of this invention to perform permutation E and to combine it in exclusive OR circuit 46 with the key word 32 in one cycle is effected by the inclusion of a column of key elements 150 alongside the right most column of matrix 102,
Byte muxes 108122 and key cells 150 are controlled by a GFLT control word in GFLT control register 160,
The encryption key enable (Encryptkeyena) bit 166,
An enlarged view of a small portion of matrix 102 and the associated key cells is shown in
The performance of the selection function S box permutation and contraction of the 48 bit words to the 32 bit words as explained with respect to
Although specific features of the invention are shown in some drawings and not in others, this is for convenience only as each feature may be combined with any or all of the other features in accordance with the invention. The words “including”, “comprising”, “having”, and “with” as used herein are to be interpreted broadly and comprehensively and are not limited to any physical interconnection. Moreover, any embodiments disclosed in the subject application are not to be taken as the only possible embodiments.
Other embodiments will occur to those skilled in the art and are within the following claims:
Claims (37)
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US10170267 US7283628B2 (en)  20011130  20020612  Programmable data encryption engine 
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US10170267 US7283628B2 (en)  20011130  20020612  Programmable data encryption engine 
JP2003550046A JP4732688B2 (en)  20011130  20021202  Galois fieldintegration / integrated addition and multiplyaccumulate 
CN 02826084 CN100480986C (en)  20011130  20021202  Galois field multiply/ multiplyadd/multiply accumulate 
DE2002637108 DE60237108D1 (en)  20011130  20021202  Galois field multiplication / multiplicationaddition / multiplicationaccumulation 
PCT/US2002/038501 WO2003048921A1 (en)  20011130  20021202  Galois field multiply/multiplyadd multiply accumulate 
EP20020804489 EP1456745B1 (en)  20011130  20021202  Galois field multiply/multiplyadd/multiplyaccumulate 
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