US7269712B2 - Thread selection for fetching instructions for pipeline multi-threaded processor - Google Patents

Thread selection for fetching instructions for pipeline multi-threaded processor Download PDF

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Publication number
US7269712B2
US7269712B2 US10/754,550 US75455004A US7269712B2 US 7269712 B2 US7269712 B2 US 7269712B2 US 75455004 A US75455004 A US 75455004A US 7269712 B2 US7269712 B2 US 7269712B2
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instruction
threads
processing
thread
instructions
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US20040193854A1 (en
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Jang-Ho Cho
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3838—Dependency mechanisms, e.g. register scoreboarding
    • G06F9/384—Register renaming

Definitions

  • Simultaneous multithreading allows a plurality of threads to simultaneously exist for a clock cycle and instructions of each of the plurality of threads to be simultaneously executed.
  • a thread may be generally defined as a distinct point of control within a process, a distinct execution path through a process, or a distinct program.
  • the CPU switches between these threads, allocating system resources to each thread in turn, in order to improve the rate of instruction throughput.
  • the higher rate of instruction throughput is achieved by providing higher utilization of the various functional units by taking advantage of the independence of the instructions from the various threads.
  • simultaneous multithreading instructions from multiple threads are executed during each cycle, dynamically sharing system resources and further improving instruction throughput. Namely, SMT allows instructions to be executed even during a waste period of a thread to reduce the effect of the waste period, which results in improved performance of the CPU.
  • a SMT processor typically includes a fetch unit fetching a next instruction or group of instructions for one or more threads from an instruction cache; an instruction decoder decoding the cached instructions to obtain the operation type and logical address or addresses associated with the operation type of each cached instruction; a register renamer converting the logical address or addresses into real address or addresses of registers in an execution unit; an instruction queue storing the decoded instructions and real addresses; and an execution unit for executing instructions taken from the instruction queue.
  • the execution unit includes function units for performing the function or operation of an instruction taken from the instruction queue and includes registers for storing the operands to perform the function and for storing results from performing the operation.
  • the registers store this information in accordance with the real address or addresses generated by the register renamer.
  • the instructions from the different threads are stored in the instruction queue unit 150
  • the instructions are held in the instruction queue unit 150 until issued to the execution unit 160 .
  • the instructions are issued out-of-order to the appropriate function unit 165 .
  • the function units 165 are blocks, such as an adder, a multiplier, a shifter, an accumulator, as non-limiting examples, which perform basic operations.
  • the registers 163 may also include, as non-limiting examples, a register to be used as an operand in the execution of the issued instruction, a temporary storage register used during an operation, a destination register to store operation results, etc.
US10/754,550 2003-01-27 2004-01-12 Thread selection for fetching instructions for pipeline multi-threaded processor Active 2024-10-01 US7269712B2 (en)

Applications Claiming Priority (2)

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KR10-2003-0005236A KR100498482B1 (ko) 2003-01-27 2003-01-27 명령어수에 수행 주기 회수를 가중치로 사용하여 쓰레드를페치하는 동시 다중 쓰레딩 프로세서 및 그 방법
KR2003-5236 2003-01-27

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US20040193854A1 US20040193854A1 (en) 2004-09-30
US7269712B2 true US7269712B2 (en) 2007-09-11

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Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060179280A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Multithreading processor including thread scheduler based on instruction stall likelihood prediction
US20060179284A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
US20060179194A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
US20060179283A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Return data selector employing barrel-incrementer-based round-robin apparatus
US20060179281A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US20060179276A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor
US20060179274A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Instruction/skid buffers in a multithreading microprocessor
US20060206692A1 (en) * 2005-02-04 2006-09-14 Mips Technologies, Inc. Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor
US20080069130A1 (en) * 2006-09-16 2008-03-20 Mips Technologies, Inc. Transaction selector employing transaction queue group priorities in multi-port switch
US20080069128A1 (en) * 2006-09-16 2008-03-20 Mips Technologies, Inc. Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch
US7613904B2 (en) 2005-02-04 2009-11-03 Mips Technologies, Inc. Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler
US7752627B2 (en) 2005-02-04 2010-07-06 Mips Technologies, Inc. Leaky-bucket thread scheduler in a multithreading microprocessor
US7773621B2 (en) 2006-09-16 2010-08-10 Mips Technologies, Inc. Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch
US7961745B2 (en) 2006-09-16 2011-06-14 Mips Technologies, Inc. Bifurcated transaction selector supporting dynamic priorities in multi-port switch
US20110276784A1 (en) * 2010-05-10 2011-11-10 Telefonaktiebolaget L M Ericsson (Publ) Hierarchical multithreaded processing
US8285973B2 (en) 2008-08-04 2012-10-09 International Business Machines Corporation Thread completion rate controlled scheduling
US20170139716A1 (en) * 2015-11-18 2017-05-18 Arm Limited Handling stalling event for multiple thread pipeline, and triggering action based on information access delay
US10983799B1 (en) 2017-12-19 2021-04-20 Apple Inc. Selection of instructions to issue in a processor
US11422821B1 (en) 2018-09-04 2022-08-23 Apple Inc. Age tracking for independent pipelines

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7000233B2 (en) * 2003-04-21 2006-02-14 International Business Machines Corporation Simultaneous multithread processor with result data delay path to adjust pipeline length for input to respective thread
KR100788500B1 (ko) * 2006-07-14 2007-12-24 엠텍비젼 주식회사 다단 파이프라인 구조의 정점 처리 장치 및 그 방법
KR100853457B1 (ko) * 2006-12-04 2008-08-21 한국전자통신연구원 고속의 대량 데이터를 수신하기 위한 데이터 수신 모듈의처리 방법
US8578387B1 (en) * 2007-07-31 2013-11-05 Nvidia Corporation Dynamic load balancing of instructions for execution by heterogeneous processing engines
US9304775B1 (en) 2007-11-05 2016-04-05 Nvidia Corporation Dispatching of instructions for execution by heterogeneous processing engines
KR101041777B1 (ko) * 2009-06-08 2011-06-17 엠텍비젼 주식회사 멀티 스레드 처리 방법 및 이를 사용하는 프로세서 디바이스
JP5573038B2 (ja) * 2009-07-23 2014-08-20 日本電気株式会社 マルチスレッドプロセッサ及びプログラム
GB2489708B (en) * 2011-04-05 2020-04-15 Advanced Risc Mach Ltd Thread selection for multithreaded processing
KR101892273B1 (ko) 2011-10-12 2018-08-28 삼성전자주식회사 스레드 프로그레스 트래킹 방법 및 장치
JP5803972B2 (ja) * 2013-04-18 2015-11-04 株式会社デンソー マルチコアプロセッサ
US9898348B2 (en) 2014-10-22 2018-02-20 International Business Machines Corporation Resource mapping in multi-threaded central processor units
CN115408153B (zh) * 2022-08-26 2023-06-30 海光信息技术股份有限公司 多线程处理器的指令分发方法、装置和存储介质

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"Front-End Policies for Improved Issue Efficiency in SMT Processors"; Ali El-Moursy and David Albonesi; 2002; IEEE. *
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Cited By (37)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7657891B2 (en) 2005-02-04 2010-02-02 Mips Technologies, Inc. Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
US7506140B2 (en) 2005-02-04 2009-03-17 Mips Technologies, Inc. Return data selector employing barrel-incrementer-based round-robin apparatus
US20060179194A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
US20060179280A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Multithreading processor including thread scheduler based on instruction stall likelihood prediction
US20060179281A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US20060179276A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor
US20060179274A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Instruction/skid buffers in a multithreading microprocessor
US20060206692A1 (en) * 2005-02-04 2006-09-14 Mips Technologies, Inc. Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor
US20070089112A1 (en) * 2005-02-04 2007-04-19 Mips Technologies, Inc. Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
US20070113053A1 (en) * 2005-02-04 2007-05-17 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US7657883B2 (en) 2005-02-04 2010-02-02 Mips Technologies, Inc. Instruction dispatch scheduler employing round-robin apparatus supporting multiple thread priorities for use in multithreading microprocessor
US8151268B2 (en) 2005-02-04 2012-04-03 Mips Technologies, Inc. Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
US7490230B2 (en) 2005-02-04 2009-02-10 Mips Technologies, Inc. Fetch director employing barrel-incrementer-based round-robin apparatus for use in multithreading microprocessor
US7853777B2 (en) 2005-02-04 2010-12-14 Mips Technologies, Inc. Instruction/skid buffers in a multithreading microprocessor that store dispatched instructions to avoid re-fetching flushed instructions
US7509447B2 (en) 2005-02-04 2009-03-24 Mips Technologies, Inc. Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
US20090249351A1 (en) * 2005-02-04 2009-10-01 Mips Technologies, Inc. Round-Robin Apparatus and Instruction Dispatch Scheduler Employing Same For Use In Multithreading Microprocessor
US7613904B2 (en) 2005-02-04 2009-11-03 Mips Technologies, Inc. Interfacing external thread prioritizing policy enforcing logic with customer modifiable register to processor internal scheduler
US7631130B2 (en) 2005-02-04 2009-12-08 Mips Technologies, Inc Barrel-incrementer-based round-robin apparatus and instruction dispatch scheduler employing same for use in multithreading microprocessor
US20060179283A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Return data selector employing barrel-incrementer-based round-robin apparatus
US8078840B2 (en) 2005-02-04 2011-12-13 Mips Technologies, Inc. Thread instruction fetch based on prioritized selection from plural round-robin outputs for different thread states
US7664936B2 (en) 2005-02-04 2010-02-16 Mips Technologies, Inc. Prioritizing thread selection partly based on stall likelihood providing status information of instruction operand register usage at pipeline stages
US7660969B2 (en) 2005-02-04 2010-02-09 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US7681014B2 (en) * 2005-02-04 2010-03-16 Mips Technologies, Inc. Multithreading instruction scheduler employing thread group priorities
US7752627B2 (en) 2005-02-04 2010-07-06 Mips Technologies, Inc. Leaky-bucket thread scheduler in a multithreading microprocessor
US20060179284A1 (en) * 2005-02-04 2006-08-10 Mips Technologies, Inc. Multithreading microprocessor with optimized thread scheduler for increasing pipeline utilization efficiency
US7990989B2 (en) 2006-09-16 2011-08-02 Mips Technologies, Inc. Transaction selector employing transaction queue group priorities in multi-port switch
US7773621B2 (en) 2006-09-16 2010-08-10 Mips Technologies, Inc. Transaction selector employing round-robin apparatus supporting dynamic priorities in multi-port switch
US7961745B2 (en) 2006-09-16 2011-06-14 Mips Technologies, Inc. Bifurcated transaction selector supporting dynamic priorities in multi-port switch
US7760748B2 (en) 2006-09-16 2010-07-20 Mips Technologies, Inc. Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch
US20080069128A1 (en) * 2006-09-16 2008-03-20 Mips Technologies, Inc. Transaction selector employing barrel-incrementer-based round-robin apparatus supporting dynamic priorities in multi-port switch
US20080069130A1 (en) * 2006-09-16 2008-03-20 Mips Technologies, Inc. Transaction selector employing transaction queue group priorities in multi-port switch
US8285973B2 (en) 2008-08-04 2012-10-09 International Business Machines Corporation Thread completion rate controlled scheduling
US20110276784A1 (en) * 2010-05-10 2011-11-10 Telefonaktiebolaget L M Ericsson (Publ) Hierarchical multithreaded processing
US20170139716A1 (en) * 2015-11-18 2017-05-18 Arm Limited Handling stalling event for multiple thread pipeline, and triggering action based on information access delay
US10552160B2 (en) 2015-11-18 2020-02-04 Arm Limited Handling stalling event for multiple thread pipeline, and triggering action based on information access delay
US10983799B1 (en) 2017-12-19 2021-04-20 Apple Inc. Selection of instructions to issue in a processor
US11422821B1 (en) 2018-09-04 2022-08-23 Apple Inc. Age tracking for independent pipelines

Also Published As

Publication number Publication date
JP2004227587A (ja) 2004-08-12
JP4476636B2 (ja) 2010-06-09
KR20040068721A (ko) 2004-08-02
KR100498482B1 (ko) 2005-07-01
US20040193854A1 (en) 2004-09-30

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