US7248530B2 - Integrated semiconductor memory device - Google Patents
Integrated semiconductor memory device Download PDFInfo
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- US7248530B2 US7248530B2 US11/261,912 US26191205A US7248530B2 US 7248530 B2 US7248530 B2 US 7248530B2 US 26191205 A US26191205 A US 26191205A US 7248530 B2 US7248530 B2 US 7248530B2
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/409—Read-write [R-W] circuits
- G11C11/4094—Bit-line management or control circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1087—Data input latches
Definitions
- the invention relates to an integrated semiconductor memory device whose data and address terminals are driven via feed lines.
- Integrated semiconductor memories such as DRAM (Dynamic Random Access Memory) semiconductor memories, for example, are arranged on a circuit board, for example a motherboard of a computer, and are driven by a memory controller for the purpose of storing or reading out information items.
- the output terminals of the memory controller are generally connected to the address and data terminals of the integrated semiconductor product according to a specified standard, for example the JEDEC (Joint Electronic Device Engineering Council) standard.
- JEDEC Joint Electronic Device Engineering Council
- FIG. 1 shows a memory module including three integrated semiconductor memories 100 , 200 and 300 , the data terminals 1 ′, 2 ′, 3 ′ and 4 ′ of which are driven in each case by a memory controller 400 .
- the memory controller 400 completely shields the memory products 100 , 200 and 300 from the module-side driving. Consequently, for an access to memory cells of the memory products, the latter cannot be driven directly externally, but rather only via the memory controller 400 connected upstream. For this purpose, the latter is driven in a manner dependent on a read or write access at a control terminal S, at an address terminal A and in the case of a write access at a data terminal D by data.
- the memory controller 400 then drives the memory products connected to it via feed lines by means of a standard access protocol.
- the memory controller 400 has a total of twelve data terminals arranged in three identical groups. Each of the three groups of data terminals includes the data terminals 1 , 2 , 3 and 4 . According to the standard specified in the example of FIG. 1 , the data terminals of the memory controller 400 are intended to be linearly connected in each case to the data terminals of the individual integrated semiconductor memories. This means that the data terminals 1 of the memory controller 400 are intended to be connected to a respective one of the data terminals 1 ′ of the semiconductor products.
- a respective one of the data terminals 2 of the memory controller is intended to be connected to a respective one of the data terminals 2 ′ of the semiconductor memories
- a respective one of the data terminals 3 of the memory controller is intended to be connected to a respective one of the data terminals 3 ′ of the memory products
- a respective one of the data terminals 4 of the memory controller is intended to be connected to a respective one of the data terminals 4 ′ of the semiconductor memories.
- the data terminals of the semiconductor memory 300 are driven in interchanged fashion by the memory controller 400 in the example of FIG. 1 .
- one of the data terminals 1 of the memory controller 400 is connected to the data terminal 2 ′ thereof.
- one of the data terminals 2 of the memory controller 400 instead of being connected to the data terminal 2 ′ of the memory product 300 , is connected to the data terminal 1 ′ of the semiconductor memory 300 .
- the data terminals 3 ′ and 4 ′ of the memory product 300 are also driven in interchanged fashion by the memory controller 400 .
- FIG. 2 shows an enlarged illustration of one of the three groups of data terminals 1 , 2 , 3 and 4 of the memory controller 400 , which are connected to the data terminals 1 ′, 2 ′, 3 ′ and 4 ′ of the memory product 300 via lines L on a circuit board.
- the actual memory chip 30 is situated within the housing of the memory product 300 .
- the contacts of the memory chip 30 to the outside world, the so-called pads PD, are connected via bonding wires B to the data terminals, the so-called pins of the memory product 300 .
- Each pad of the memory chip 30 is connected to a register 1 ′′, 2 ′′, 3 ′′ and 4 ′′ of a register circuit R on the memory chip.
- a memory cell comprises a storage capacitor SC, which can be connected to a connected bit line BL via a selection transistor AT.
- the meaning of the individual pins 1 ′, 2 ′, 3 ′ and 4 ′ is given by the product pad definition.
- the information present at the pin 1 ′ is stored via the pad connected to the bonding wire in the register 1 ′′ of the memory product.
- the information items present at the pins 2 ′, 3 ′ and 4 ′ are stored within the product via the corresponding pads in the registers 2 ′′, 3 ′′ and 4 ′′.
- a programmable logic circuit is arranged between the pads and further circuit components of the memory chip which are driven by signals applied to the pads.
- U.S. Pat. No. 6,665,782 describes a circuit group including a transmitting unit, for example a camera, and a receiving unit, for example a memory unit for storing digital photographs from the camera.
- a transmitting unit for example a camera
- a receiving unit for example a memory unit for storing digital photographs from the camera.
- terminals of the camera chip within the transmitting unit are connected via a programmable logic circuit to external output terminals of the transmitting unit. External input terminals of the receiving unit are thus driven with interchanged signals by the transmitting unit.
- a further programmable logic circuit is situated between the external input terminals of the receiving unit and terminals of the memory chip of the receiving unit. If the scrambling scheme used in the transmitting unit is known, the programmable logic circuit of the receiving unit can be programmed complementarily with respect to the programmable logic circuit of the transmitting unit in order to resolve the scrambling.
- the actual test program is adapted to the respective module circuit board depending on scrambling of the data and/or address terminals on the module. Depending on the module type, it is thus possible to predefine an adapted line scrambling which is drawn up and maintained for the test run. Furthermore, modern test systems have a logical data scrambler which, in address-dependent fashion, chooses the polarity of the information to be written.
- test programs Since the test programs have to be repeatedly rewritten depending on the scrambling used on the circuit board, the method is very time-consuming. If each memory product on a module is wired differently with the memory controller, a dedicated test program has to be used for each memory product and the same test has to be repeated multiply on a module depending on the number of memory products present. The associated outlay for ensuring a high test severity results in increased test costs. If, on the other hand, the individual adaptation of the test programs depending on the line scrambling used on a module test circuit board is dispensed with, individual memory products cannot be tested at all. The consequence is a deficient or not adapted and deterministic test severity.
- module self-test engines In addition to the generation of data topologies within a tester, memory modules often also have special circuits, so-called module self-test engines, which can generate corresponding data topologies for testing. On account of the simple and space-saving construction of these circuits, however, the test engines are usually unable to resolve the scrambling. In this case, products whose data and/or address line wiring between the corresponding terminals of the memory controller and of the semiconductor product deviates from the predefined standard cannot be tested at all or can only be tested inadequately.
- the document DE 101 31 277 A1 describes a semiconductor memory device having an address decoder device.
- an applied physical address specifying a physical position of a memory cell in a memory cell array is decoded into an electrical address of the memory cell to be addressed. If physical and electrical address diverge in the case of the semiconductor memory device, then an external test system can directly input the physical address of the memory cell to be addressed into an address input device of the semiconductor memory device. The “address scrambling” is thus effected directly by the address decoder device on the semiconductor memory device.
- a data decoder device may also be provided on the semiconductor memory device.
- said data decoder device performs a “data scrambling” if “normal” memory cells, in which a logic “0” is stored for example by means of a negatively charged state and “inverted” memory cells, in which a logic “0” is stored for example by means of a positively charged state, are present.
- An object of the present invention is to provide an integrated semiconductor memory device in which signals which drive terminals of the integrated semiconductor memory in a manner that deviates from a definition are fed to a circuit component of the integrated semiconductor memory in a manner corresponding to the definition.
- Another object of the present invention is to provide a method in which signals which drive terminals of an integrated semiconductor memory in a manner that deviates from a definition are fed to a circuit component of the integrated semiconductor memory in a manner corresponding to the definition.
- an integrated semiconductor memory comprises external terminals to which an input signal can be applied in each case, a register circuit with registers, where each register is provided to store a respective one of the input signals.
- the integrated semiconductor memory furthermore comprises a programming circuit with programmable switching units, via which, in a manner dependent on a respective programming state of the programmable switching units, a respective one of the external terminals can be connected to a respective one of the registers of the register circuit.
- the programming circuit is configured such that the programming state of one of the programmable switching units of the programming circuit is programmed by a respective programming signal being applied to the external terminals the programming signal applied to one of the external terminals having a first state and the programming signals respectively applied to the other of the external terminals having a second state.
- An integrated semiconductor memory designed in this way makes it possible to feed input signals according to a definition, for example a JEDEC standard, to registers of the integrated semiconductor memory independently of the order in which the input signals are fed to the external terminals of the integrated semiconductor memory.
- the programming circuit ensures that input signals which are applied to the external terminals of the integrated semiconductor memory by a tester, for example, are fed to the registers of the register circuit in accordance with the definition as defined, even if the external terminals are driven by the input signals in a manner counter to the definition, that is to say counter to a predefined standard. Consequently, a test system need not be reprogrammed in wiring-specific fashion for storing a data topology.
- the tester On the output side, the tester generates at its data and/or address terminals data and/or address vectors which merely need to be adapted to the defect mechanism to be tested. Consequently, a reprogramming of the data and/or address vectors depending on the wiring of the semiconductor memory is not necessary.
- the programming circuit which is connected between the external terminals of the integrated semiconductor memory and the registers of the register circuit, can be programmed in a simple manner for resolving the line scrambling.
- the programming signal having a first level is applied to a respective one of the external terminals and the programming signal having a second level is applied to the other programming terminals. Consequently, the interchange scheme with which the external terminals are driven by a transmitting unit, for example a tester or else a memory controller, does not need to be known for the memory-internal resolution of the line scrambling.
- the programming circuit includes a plurality of input terminals and a plurality of output terminals.
- a respective one of the external terminals can be connected to a respective one of the input terminals of the programming circuit.
- a respective one of the output terminals of the programming circuit can be connected to a respective one of the registers of the register circuit.
- a respective one of the input terminals of the programming circuit can be connected to a respective one of the output terminals of the programming circuit.
- first controllable switches and second controllable switches are provided.
- a respective one of the external terminals can be connected to a respective one of the input terminals of the programming circuit via a respective one of the first controllable switches.
- a respective one of the output terminals of the programming circuit can be connected to a respective one of the registers of the register circuit via a respective one of the controllable switches.
- the programmable switching units in each case can include a controllable switch, via which one of the input terminals of the programming circuit can be connected to one of the output terminals of the programming circuit.
- the programmable switching units are connected to a terminal for application of a control voltage.
- the programmable switching units in each case have a further controllable switch.
- the control voltage can be fed via the respective further controllable switch of the programmable switching units to a respective control terminal of the controllable switch of the programmable switching units.
- the programmable switching units in each case contain a programmable element.
- the respective programmable element of the programmable switching units is connected, on the output side, to a respective control terminal of the further controllable switch of the programmable switching units.
- the respective programmable element of the programmable switching unit is further configured such that, in the programmed state, it controls the respective further controllable switch of the programmable switching units into the on state, so that the control voltage is fed to the respective control terminal of the controllable switch of the programmable switching units and controls the respective controllable switch of the programmable switching units into the on state.
- the respective programmable element of the programmable switching units is further configured such that, in the non-programmed state, it turns off the respective further controllable switch of the programmable switching units, so that the control voltage is isolated from the respective control terminal of the controllable switch of the programmable switching units and the respective controllable switch of the programmable switching units is thus turned off.
- the programmable elements can be formed in each case as fuse elements.
- the programmable elements are preferably formed in each case as a bistable multivibrator.
- the bistable multivibrators are arranged in rows and columns.
- the bistable multivibrators of a row are connected up as shift registers.
- the integrated semiconductor memory device includes third controllable switches.
- a respective one of the shift registers can be connected, on the input side, to a respective one of the registers of the register circuit via a respective one of the third controllable switches.
- the integrated semiconductor memory preferably includes fourth controllable switches.
- a respective one of the external terminals can be connected to a respective one of the registers of the register circuit via a respective one of the fourth controllable switches.
- the third and fourth controllable switches are controlled into the on state.
- the programming circuit is subsequently programmed by unit vectors of programming signals being applied alternately to the external terminals.
- the programming signal having a first state is applied in each case to one of the external terminals and the programming signal having a second state is applied to the rest of the external terminals.
- the method is repeated until the first programming state has been applied once to each of the external terminals.
- the programming circuit is then programmed and makes it possible for an unknown line scrambling to be resolved internally.
- the third and fourth controllable switches are turned off again and instead the first and second controllable switches are controlled into the on state, so that the external terminals are connected to the registers of the register circuit via the programmable switching units of the programming circuit.
- a programmed switching unit connects an external terminal to one of the registers of the register circuit. Signals that are applied to the external terminals are buffer-stored in the register circuit before they are forwarded from there to further circuit components of the integrated semiconductor memory.
- the external terminals can be in each case formed as address terminals or as data terminals.
- a method for operating an integrated semiconductor memory device in accordance with the invention comprises providing an integrated semiconductor memory device including external terminals to which an input signal can be applied in each case, a register circuit with registers, a respective one of the registers being provided for storing a respective one of the input signals, a programming circuit with programmable switching units, via which, in a manner dependent on a respective programming state of the programmable switching units, a respective one of the external terminals can be connected to a respective one of the registers of the register circuit.
- the programming circuit is configured such that the programming state of one of the programmable switching units of the programming circuit is programmed by a respective programming signal being applied to the external terminals, the programming signal applied to one of the external terminals having a first state and the programming signals respectively applied to the other of the external terminals having a second state.
- the method involves programming a number of programmable switching units, which corresponds to the number of external terminals, by carrying out a programming step. In this programming step, the programming signal having a first state is applied to one of the external terminals and the programming signal having a second state is applied to the rest of the external terminals.
- the programming step specified is repeated, in which, upon each repetition of the programming step, the programming signal having the first state is applied to another of the external terminals and the programming signal having the second state is applied to the rest of the external terminals until the programming signal having the first state has been applied precisely once to each of the external terminals.
- the programming of the programmable switching units is effected in the context of an initialization of the programming circuit.
- So-called unit data/address vectors are transmitted from the controller side on the feed lines to the data and/or address terminals of the integrated semiconductor memory.
- a logic “0” is communicated on all the feed lines apart from one.
- a logic “1” is transmitted, by contrast, on one of the feed lines.
- the unit vectors are collected in an address register or in a data register in the semi-conductor memory. From the address or data register, the unit vectors are forwarded to the programmable switching units for the stepwise programming thereof. If one of the programmable switching units is driven with a logic “1”, then it is in the programmed state.
- each of the external terminals of the programming circuit can be connected to each of the registers of the register circuit in a manner that reverses the interchanged driving of the external terminals.
- the integrated semiconductor memory device is operable in a first or second operating state.
- a respective one of the external terminals is connected to one of the registers of the register circuit in the first operating state of the integrated semiconductor memory with bridging of the programming circuit.
- a respective one of the external terminals is connected via a respective one of the programmable switching units of the programming circuit to a respective one of the registers of the register circuit.
- FIG. 1 shows a memory module with different wiring of feed lines to data terminals between a memory controller and semiconductor memory products.
- FIG. 2 shows an enlarged illustration of a memory product whose data lines are driven by a memory controller with a wiring that deviates from a standard.
- FIG. 3 shows a circuit arrangement for carrying out a “rescrambling” according to the invention.
- FIG. 4A shows an embodiment of a programmable programming circuit according to the invention.
- FIG. 4B shows an embodiment of a programmable switching unit according to the invention.
- FIGS. 5A-5D show a programming of a programming circuit according to the invention.
- FIG. 3 shows the data terminals 1 , 2 , 3 and 4 of the memory controller 400 , which are connected via data lines L to the data terminals 1 ′, 2 ′, 3 ′ and 4 ′ of the memory module 300 .
- the data pins 1 ′, 2 ′, 3 ′ and 4 ′ are connected via controllable switches 14 to the registers 1 ′′, 2 ′′, 3 ′′ and 4 ′′ of the register circuit R.
- the register circuit R is connected to the memory cell array SZF of FIG. 2 , where the memory cell array is not illustrated in FIG. 3 .
- the input signal ES 1 generated at the controller terminal 1 for the memory product is fed to the data pin 2 ′ and, via one of the controllable switches 14 , to the register 2 ′′ of the register circuit R.
- the input signal ES 2 generated at the data output 2 of the memory controller 400 is fed to the data pin 1 ′ and, via one of the controllable switches 14 , to the register 1 ′′ of the register circuit R.
- the input signal ES 3 generated at the controller output is fed to the data pin 4 ′ and, via one of the controllable switches 14 , to the register 4 ′′ of the register circuit R.
- the input signal ES 4 generated at the data output 4 of the memory controller 400 is fed to the data pin 3 ′ and thus to the register 3 ′′ of the register circuit R.
- the input signal ES 1 be fed to the data terminal 1 ′ and, respectively, to the register 1 ′′
- the input signal ES 2 be fed to the data terminal 2 ′ and, respectively, to the register 2 ′′
- the input signal ES 3 be fed to the data terminal 3 ′ and, respectively, to the register 3 ′′
- the input signal ES 4 be fed to the data terminal 4 ′ and, respectively, to the register 4 ′′.
- the feeding of the input signals ES 1 , . . . , ES 4 deviates, however, from the required feeding to the data terminals 1 ′, . . . , 4 ′ and, respectively, to the registers 1 ′′, . . . , 4 ′′.
- the register circuit R is connected to a programming circuit 15 via a controllable switch 13 .
- the programming circuit 15 includes programmable switching units P 11 , . . . , P 44 arranged in matrix-type fashion within the programming circuit 15 .
- the input signal that is buffer-stored in the register 1 ′′ can be fed via one of the controllable switches 13 to a programming terminal N 1 and thus to the programmable switching units P 11 , P 21 , P 31 and P 41 .
- the input signal that is buffer-stored in the register 2 ′′ can be fed via one of the controllable switches 13 to a programming terminal N 2 and thus to the programmable switching units P 12 , P 22 , P 32 and P 42 .
- the input signal that is buffer-stored in the register 3 ′′ can be fed via one of the controllable switches 13 to a programming terminal N 3 and thus to the programmable switching units P 13 , P 23 , P 33 and P 43 .
- the input signal that is buffer-stored in the register 4 ′′ can be fed via one of the controllable switches 13 to a programming terminal N 4 and thus to the programmable switching units P 14 , P 24 , P 34 and P 44 .
- the programming circuit 15 has, in addition to the programming terminals N 1 , N 2 , N 3 and N 4 , input terminals E 1 , E 2 , E 3 and E 4 , which can be connected to the data pins 1 ′, 2 ′, 3 ′ and 4 ′ via controllable switches 11 . If the controllable switches 14 are turned off and in contrast the controllable switches 11 are controlled into the on state, then the input signals present at the data pins 1 ′, 2 ′, 3 ′ and 4 ′ are fed via the programmable switching units to output terminals A 1 , A 2 , A 3 and A 4 of the programming circuit 15 .
- the output terminals A 1 , A 2 , A 3 and A 4 are connected via controllable switches 12 to the registers 1 ′′, 2 ′′, 3 ′′ and 4 ′′ of the register circuit R.
- the input signals can thus be written directly to the registers of the register circuit R via the controllable switches 14 or, with switches 14 controlled into the off state and switches 11 and 12 controlled into the on state, be fed to the registers of the register circuit R via the programmable switching units.
- the programmable switching unit P 11 in the programmed state, connects the input terminal E 1 , the programmable switching unit P 12 , in the programmed state, connects the input terminal E 2 , the programmable switching unit P 13 , in the programmed state, connects the input terminal E 3 and the programmable switching unit P 14 , in the programmed state, connects the input terminal E 4 to the output terminal A 1 of the programming circuit.
- the programmable switching unit P 21 in the programmed state, connects the input terminal E 1 , the programmable switching unit P 22 , in the programmed state, connects the input terminal E 2 , the programmable switching unit P 23 , in the programmed state, connects the input terminal E 3 and the programmable switching unit P 24 , in the programmed state, connects the input terminal E 4 to the output terminal A 2 of the programming circuit.
- the programmable switching unit P 31 in the programmed state, connects the input terminal E 1 , the programmable switching unit P 32 , in the programmed state, connects the input terminal E 2 , the programmable switching unit P 33 , in the programmed state, connects the input terminal E 3 and the programmable switching unit P 34 , in the programmed state, connects the input terminal E 4 to the output terminal A 3 of the programming circuit 15 .
- the programmable switching unit P 41 in the programmed state, connects the input terminal E 1 , the programmable switching unit P 42 , in the programmed state, connects the input terminal E 2 , the programmable switching unit P 43 , in the programmed state, connects the input terminal E 3 and the programmable switching unit P 44 , in the programmed state, connects the input terminal E 4 to the output terminal A 4 of the programming circuit 15 .
- the programmable switching units P 11 , P 21 , P 31 and P 41 can in each case be programmed by a programming signal at the programming terminal N 1 .
- the programmable switching units P 12 , P 22 , P 32 and P 42 can in each case be programmed by a programming signal at the programming terminal N 2 .
- the programmable switching units P 13 , P 23 , P 33 and P 43 can in each case be programmed by a programming signal at the programming terminal N 3 .
- the programmable switching units P 14 , P 24 , P 34 and P 44 can in each case be programmed by a programming signal at the programming terminal N 4 .
- FIG. 4A shows the matrix-type arrangement of the programmable switching units P 11 , . . . , P 44 of the programming circuit 15 .
- the programmable switching units each have programmable switches PS.
- the programmable switch In a programmed state of the programmable switch PS, the programmable switch in each case connects one of the input terminals E 1 , . . . , E 4 of the programming circuit to one of the output terminals A 1 , . . . , A 4 of the programming circuit.
- each of the programmable switching units is connected to a terminal AV for application of a voltage potential VPP.
- the voltage potential VPP is for example a voltage which is also used for driving the word lines of the memory cell array in order to control the selection transistors of the memory cells into the on state.
- FIG. 4B illustrates the programmable switching unit P 44 with the programmable switch PS in enlarged fashion.
- the programmable switching unit P 44 furthermore includes a programmable element F, which is designed as a multivibrator in the exemplary embodiment.
- the set inputs of the multivibrator are connected to the programming terminal N 4 .
- the multivibrator F is connected to a further multivibrator within the programmable switching unit P 34 .
- the multivibrators of the programmable switching units P 44 , P 34 , P 24 and P 14 thus form a shift register SR 4 .
- the state stored in one of the multivibrators of the shift register SR 4 is shifted in the shift register SR 4 by one position into the next multivibrator of the shift register SR 4 .
- the multivibrators that are programmable via the programming terminal N 4 also form a shift register SR 3
- the multivibrators that are programmable via the programming terminal N 2 also form a shift register SR 2
- the multivibrators that are programmable via the programming terminal N 1 also form a shift register SR 1 .
- the programmable switching unit P 44 has an input terminal EP, which is connected to the input terminal E 4 , and an output terminal AP, which is connected to the output terminal A 4 of the programming circuit 15 .
- the input terminal EP is connected to the output terminal AP of the programmable switching unit via a switching transistor T 1 .
- a control terminal ST 1 of the switching transistor T 1 is connected via a switching transistor T 2 to the terminal AV for application of the control voltage VPP.
- a control terminal ST 2 of the switching transistor T 2 is controlled by the multivibrator F on the output side.
- the multivibrator F is set with a state “1”. Upon the next clock signal CLK, the state “1” is advanced into the programmable switching unit P 34 .
- the multivibrator F generates on the output side a high signal level that controls the switching transistor T 2 into the on state, so that the control terminal ST 1 of the switching transistor T 1 is driven by the control voltage VPP.
- the control voltage VPP has a high potential level that also controls the switching transistor T 1 into the on state. Consequently, the input terminal E 4 of the programming circuit 15 is connected to the output terminal A 4 .
- the functioning of the programming circuit 15 will be explained in more detail below with reference to FIGS. 5A , 5 B, 5 C and 5 D.
- the method can be applied in parallel to the memory products arranged on the memory module. For the sake of simplicity, the method is described below on the basis of the integrated semiconductor memory 300 .
- the memory product 300 is driven by the memory controller 400 with a control signal, for example the mode register set command, which is applied to the address terminals of the semiconductor product in order to set a bit in a mode register of the memory product.
- a control signal for example the mode register set command
- a control circuit of the memory product 300 thereupon switches the controllable switches 13 and 14 into the on state, whereas the controllable switches 11 and 12 remain turned off.
- the data pins 1 ′, 2 ′, 3 ′ and 4 ′ of the memory product 300 are thus driven by the input signal levels 0, 1, 0, 0.
- These values are stored in the registers 1 ′′, 2 ′′, 3 ′′ and 4 ′′ likewise in the order 0, 1, 0, 0.
- the subsequent step for initializing the programming circuit 15 is illustrated in FIG. 5B .
- the data pins 1 ′, 2 ′, 3 ′ and 4 ′ of the memory product 300 are thus driven by the signal levels 1, 0, 0, 0.
- the registers 1 ′′, 2 ′′, 3 ′′ and 4 ′′ of the register circuit R are programmed with the states 1, 0, 0, 0.
- the states stored in the programmable switching units P 41 , P 42 , P 43 and P 44 are advanced into the column S 3 .
- the data pins 1 ′, 2 ′, 3 ′ and 4 ′ of the semiconductor products 300 are thus driven by the signal levels 0, 0, 0, 1 on account of the line scrambling illustrated in FIG. 3 .
- These states are in turn buffer-stored in the same order in the registers of the register circuit by means of the linear connection between the data pins and the registers of the register circuit.
- the states stored in the column S 3 are advanced into the column S 2 and the states stored in the column S 4 up to that point are transferred into the column S 3 .
- the data pins 1 ′, 2 ′, 3 ′, 4 ′ of the memory product 300 are thus driven by the signals 0, 0, 1, 0 which are buffer-stored in the registers 1 ′′, 2 ′′, 3 ′′ and 4 ′′ of the register circuit.
- the programming circuit 15 therefore, only the programmable switching units P 12 , P 21 , P 34 and P 43 are in a programmed state.
- the switching transistors T 1 and T 2 of the programmable switching units are switched into the on state. Consequently, the input terminal E 2 is connected to the output terminal A 1 via the programmed switching unit P 12 .
- the input terminal E 1 is connected to the output terminal A 2 via the programmed switching unit P 21 .
- the input terminal E 4 is connected to the output terminal A 3 via the programmed switching unit P 34 , and the input terminal E 3 is connected to the output terminal A 4 via the programmed switching unit P 43 .
- the controllable switches 13 and 14 are turned off and the controllable switches 11 and 12 are controlled into the on state. Consequently, a signal present at the data pin 1 ′ is fed to the register 2 ′′, a signal present at the data pin 2 ′ is fed to the register 1 ′′, a signal present at the data pin 3 ′ is fed to the register 4 ′′, and a signal present at the data pin 4 ′ is fed to the register 3 ′′.
- the signals generated by the memory controller at its data terminals 1 , 2 , 3 and 4 are stored in the registers 1 ′′, 2 ′′, 3 ′′ and 4 ′′ of the register circuit R.
- the programming circuit 15 ensures that, independently of the line scrambling used, the signal generated at the data terminal 1 of the memory controller 400 is always stored in the register 1 ′′ of the register circuit, the signal generated at the data terminal 2 of the memory controller 400 is stored in the register 2 ′′ of the register circuit, the signal generated at the data terminal 3 of the memory controller 400 is stored in the register 3 ′′ of the register circuit, and the signal generated at the data terminal 4 of the memory controller is stored in the register 4 ′′ of the register circuit of the memory products 100 , 200 and 300 .
- a register within the memory controller 400 which allocates data signals to the respective data terminals of each group of data terminals thus only needs to be programmed once and is therefore independent of the respective line scrambling of a memory product connected to the memory controller 400 .
- the programming circuit 15 for discovering the line scrambling of data lines has been explained with reference to the figures illustrated, it can also be used for discovering the line scrambling of address lines. In both cases, the programming circuit 15 is to be connected between the data/address pins and the downstream register of the memory product.
- the programming circuit 15 is preferably arranged on the semiconductor memory. However, it may also be used within the memory controller or within a tester.
- Programming circuits corresponding to the number of memory products driven are contained on the memory controller or in the tester. As a result, a product-specific rescrambling matrix is stored within the memory controller or the tester.
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
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Abstract
Description
List of |
1, 2, 3, 4 | Data terminals of the |
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1′, 2′, 3′, 4′ | Data terminals of the |
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1″, 2″, 3″, 4″ | Registers of the |
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100, 200, 300 | |
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1000 | |
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11, 12, 13, 14 | Controllable switches | ||
15 | |
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30 | |
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400 | Memory controller | ||
A | Address terminal | ||
AT | Selection transistor | ||
AV | Terminal for control voltage | ||
B | Bonding wire | ||
BL | Bit line | ||
CLK | Clock signal | ||
D | Data terminal | ||
ES | Input signal | ||
F | Multivibrator | ||
L | Conductor track | ||
N | Programming terminal | ||
P | Programmable switching unit | ||
PD | Pad | ||
S | Control terminal | ||
SC | Storage capacitor | ||
SR | Shift register | ||
ST | Control terminal | ||
SZ | Memory cell | ||
SZF | Memory cell array | ||
T | Switching transistor | ||
VPP | Control voltage | ||
WL | Word line | ||
Claims (15)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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DE102004052589 | 2004-10-29 | ||
DE102004052589.7 | 2004-10-29 |
Publications (2)
Publication Number | Publication Date |
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US20060109705A1 US20060109705A1 (en) | 2006-05-25 |
US7248530B2 true US7248530B2 (en) | 2007-07-24 |
Family
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Application Number | Title | Priority Date | Filing Date |
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US11/261,912 Expired - Fee Related US7248530B2 (en) | 2004-10-29 | 2005-10-31 | Integrated semiconductor memory device |
Country Status (1)
Country | Link |
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US (1) | US7248530B2 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060073804A1 (en) * | 2004-10-04 | 2006-04-06 | Hiroshi Tanaka | Semiconductor integrated circuit and a software radio device |
US9336401B2 (en) | 2014-01-20 | 2016-05-10 | International Business Machines Corporation | Implementing enhanced security with storing data in DRAMs |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4915779B2 (en) * | 2006-06-02 | 2012-04-11 | 株式会社メガチップス | Connection method between devices and connection device |
DE102006043669A1 (en) * | 2006-09-18 | 2008-03-27 | Qimonda Ag | Control module for controlling at least one semiconductor memory module of a semiconductor memory module |
JP4498370B2 (en) * | 2007-02-14 | 2010-07-07 | 株式会社東芝 | Data writing method |
TW200901042A (en) * | 2007-06-23 | 2009-01-01 | Jmicron Technology Corp | Storage device and circuit element switching method thereof |
Citations (4)
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US6057705A (en) | 1998-05-28 | 2000-05-02 | Microchip Technology Incorporated | Programmable pin designation for semiconductor devices |
US6665782B2 (en) | 2001-08-16 | 2003-12-16 | International Business Machines Corporation | Method and apparatus for preventing unauthorized access of memory devices |
US6738891B2 (en) * | 2000-02-25 | 2004-05-18 | Nec Corporation | Array type processor with state transition controller identifying switch configuration and processing element instruction address |
US6826111B2 (en) | 2001-06-28 | 2004-11-30 | Infineon Technologies Ag | On chip scrambling |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6826611B1 (en) * | 2000-09-30 | 2004-11-30 | Fluke Corporation | Apparatus and method for automatically obtaining a valid IP configuration in a local area network |
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2005
- 2005-10-31 US US11/261,912 patent/US7248530B2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6057705A (en) | 1998-05-28 | 2000-05-02 | Microchip Technology Incorporated | Programmable pin designation for semiconductor devices |
US6738891B2 (en) * | 2000-02-25 | 2004-05-18 | Nec Corporation | Array type processor with state transition controller identifying switch configuration and processing element instruction address |
US6826111B2 (en) | 2001-06-28 | 2004-11-30 | Infineon Technologies Ag | On chip scrambling |
US6665782B2 (en) | 2001-08-16 | 2003-12-16 | International Business Machines Corporation | Method and apparatus for preventing unauthorized access of memory devices |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20060073804A1 (en) * | 2004-10-04 | 2006-04-06 | Hiroshi Tanaka | Semiconductor integrated circuit and a software radio device |
US7756505B2 (en) * | 2004-10-04 | 2010-07-13 | Hitachi, Ltd. | Semiconductor integrated circuit and a software radio device |
US9336401B2 (en) | 2014-01-20 | 2016-05-10 | International Business Machines Corporation | Implementing enhanced security with storing data in DRAMs |
US9342700B2 (en) | 2014-01-20 | 2016-05-17 | International Business Machines Corporation | Implementing enhanced security with storing data in DRAMs |
Also Published As
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US20060109705A1 (en) | 2006-05-25 |
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