US7135395B2 - Bonding pad structure to minimize IMD cracking - Google Patents

Bonding pad structure to minimize IMD cracking Download PDF

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US7135395B2
US7135395B2 US10/916,797 US91679704A US7135395B2 US 7135395 B2 US7135395 B2 US 7135395B2 US 91679704 A US91679704 A US 91679704A US 7135395 B2 US7135395 B2 US 7135395B2
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trenches
dielectric layer
forming
bonding
metal
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Chung Liu
Yuan-Lung Liu
Ruey-Yun Shiue
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05094—Disposition of the additional element of a plurality of vias at the center of the internal layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05095—Disposition of the additional element of a plurality of vias at the periphery of the internal layers
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05075—Plural internal layers
    • H01L2224/0508—Plural internal layers being stacked
    • H01L2224/05085—Plural internal layers being stacked with additional elements, e.g. vias arrays, interposed between the stacked layers
    • H01L2224/05089—Disposition of the additional element
    • H01L2224/05093—Disposition of the additional element of a plurality of vias
    • H01L2224/05096—Uniform arrangement, i.e. array
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    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
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    • H01L2924/01023—Vanadium [V]
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    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
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    • H01L2924/01074—Tungsten [W]
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    • H01L2924/049—Nitrides composed of metals from groups of the periodic table
    • H01L2924/0504—14th Group
    • H01L2924/05042—Si3N4
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Definitions

  • the present invention relates generally to semiconductor integrated circuit processing and more particularly to contact pad structures that resist intermetal dielectric cracking.
  • Bonding pads are the interfaces between the integrated circuits contained in semiconductor chips and the chip package. A large number of bonding pads is required to transmit power, ground and impute/output signals to the chip devices. It is thus important that the bonding pad yield be sufficiently high to ensure a high per chip yield.
  • the general bonding pad structure consists of metal layers, emanating from the terminals of the chip devices, separated by intermetal dielectric (IMD) layers that are often silicon oxide.
  • IMD intermetal dielectric
  • Metal vias, W is often used, pass through the IMD layers connecting the metal layers. Wires are bonded to a bonding metal pattern and to the chip package forming electrical connections between the chip and the package.
  • a passivation layer covers the surface, except over the bonding sites, to seal the chip from contaminants and for scratch protection.
  • One mode of failure of the bonding pad relates to the peeling of the wire from the metal pattern due to forces exerted especially during the bonding process. This has been addressed in U.S. Pat. No. 6,002,179 to Chan et al., who teach a bonding pad structure with increased peeling resistance and in U.S. Pat. No. 5,731,243 to Peng et al., who show a cleaning method to ensure contamination free bonding. Another failure mode that has been observed relates to bonding pad peel back, where forces during wire bonding may cause a delaminating of one or more of the underlying layers. Bonding pad structures that resist bond pad peeling have been disclosed in U.S. Pat. No. 6,025,277 to Chen et al. and in U.S. Pat. No. 5,707,894 to Hsiao.
  • FIGS. 1 a , 1 b , and 1 c there is shown conventional via hole arrays. Regions 10 are IMD oxide layers, and regions 12 are metal filled via holes passing through the IMD. Cracks that are observed in the IMD are similar to that depicted in FIG. 2 . These are cracks that propagate along the IMD layer avoiding the metal of the vias. Once a small crack is initiated it will, under stresses prevalent in the layer during processing, grow extensively. Approaches to alleviate this cracking of the IMD focus on producing IMD layers with low residual stress. Composite silicon oxide layers serve this purpose and are used, such as HDP plus PETEOS layers. However, even with composite silicon oxide layers to reduce stress, the IMD layer is not strong enough to withstand stresses encountered during chip packaging and IMD cracking is still observed.
  • a novel mesh pad structure is proposed that will increase the bonding pad strength and eliminate extensive cracking of the IMD. Instead of traditional via holes, via trenches are formed through the IMD, dividing the remaining IMD into small cells. After the trenches are filled with metal the metal trenches enclose the cells. This increases the strength of the bonding pad so that IMD cracking is less likely to occur. Furthermore, even in the unlikely event of the initiation of an IMD crack, the crack will propagate no further than the metal trench.
  • a method is disclosed of forming a bonding pad that is immune to IMD cracking.
  • a partially processed semiconductor wafer is provided having one to all but one metal levels completed.
  • a blanket dielectric layer is formed over the metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells.
  • the trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patterns, after which a passivation layer is formed.
  • FIGS. 1 a , 1 b and 1 c Prior Art, show conventional via patterns.
  • FIG. 2 depicts a crack in the IMD of a conventional bonding pad.
  • FIG. 3 shows the basic pattern of the mesh via trenches.
  • FIG. 4 shows a mesh via trench structure without trench intersection.
  • FIG. 5 shows a mesh via trench structure with a brick-laying pattern.
  • FIG. 6 shows a mesh via trench structure with a modified brick-laying pattern.
  • FIG. 3 illustrates the basic pattern of the novel mesh pad structure.
  • the IMD, 10 is separated into cells by perpendicular arrays of metal filled via trenches.
  • the array 14 is denoted the vertical array and the array 16 the horizontal array.
  • the strength of the IMD-via trench structure is higher than that of the traditional IMD-via hole structures, such as those depicted in FIGS. 1 a , 1 b and 1 c .
  • initiation of cracks in the IMD will occur less frequently for the mesh pad structure than for traditional structures utilizing via holes, such as those depicted in FIGS. 1 a , 1 b and 1 c .
  • the crack could only propagate as far as the metal filled trench which border the IMD cells.
  • the crack size is limited to be less than about the cell diagonal.
  • the crack can propagate over large distances avoiding metal filled via holes. The reduced damage in the case of a mesh pad structure is manifested in substantial improvement of the quality and reliability of the bonding pad.
  • Basic elements of a bonding pad structure consist of metal layers, emanating from the terminals of the chip devices, separated by IMD layers. Also there is an IMD layer separating the uppermost metal layer from a bonding metal pattern that is formed over this IMD layer and there are metal connectors passing through the IMD layers connecting the metal layers to the bonding metal pattern. Wires are bonded to the bonding metal pattern and to the chip package forming electrical connections between the chip and the package.
  • a passivation layer covers the surface, except over the bonding sites, to seal the chip from contaminants and for scratch protection.
  • a mesh via trench pattern can be used between any two levels of metal. However, its crack resistance properties are mostly utilized when used between the uppermost metal layer and the bonding metal pattern.
  • a blanket dielectric, layer is first formed over the uppermost metal layer, using techniques well known to those skilled in the art. This dielectric layer is often silicon oxide.
  • Composite layers are useful in relieving internal stress in the dielectric, stress that contributes to cracking in the dielectric layer, and preferred embodiments of the invention utilize such layers.
  • Composite dielectric layers that are used to relieve internal stress include dual oxide layers, where, for instance, one of the layers is formed using HDP and the other using PETEOS, for example, 7000 Angstroms can be deposited using HDP and 17000 Angstroms using PETEOS.
  • trench widths of between about 0.1 and 0.5 micrometers and for trench lengths between about 0.1 and 100 micrometers, which also provides the cell dimension
  • the IMD strength is significantly increased, and crack sizes are limited to less than about the cell diagonal.
  • a via trench layout according to preferred embodiments of the invention in which trenches do not intersect is shown in FIG. 4 . This form of layout will be referred to as the nonintersecting layout.
  • Arrays of horizontal, 16 , and vertical, 14 , trenches nearly divide the IMD layer, 10 , into cells though they do not intersect.
  • Trench widths are between about 0.1 and 0.5 micrometers and the trench lengths are between about 0.1 and 100 micrometers for trenches in both the vertical and horizontal arrays.
  • FIG. 5 Another trench layout according to preferred embodiments of the invention is referred to as the bricklaying layout and is depicted in FIG. 5 .
  • the trenches, 14 and 16 do actually divide the IMD layer, 10 , into closed cells.
  • T-shaped overlap at positions, 18 are also present.
  • Void formation still occurs during metal filling of the trenches at overlaps such at positions 18 , however this is at a reduced frequency as compared with crossing intersections.
  • Trench widths are between about 0.1 and 0.5 micrometers and the trench separation is between about 0.1 and 10 micrometers for horizontal trenches and between about 0.1 and 10 micrometers for vertical trenches.
  • a trench layout denoted as the modified bricklaying layout and shown in FIG. 6 , is utilized in other preferred embodiments of the invention. Except for overlap region, 20 , the trench layout and dimensions for the modified bricklaying layout are similar to the trench layout and dimension for the bricklayer layout.
  • the overlap region, 20 for the modified bricklaying layout is reduced from that of the overlap region, 18 , for the bricklaying layout and results in a reduction in voiding. Modified bricklaying overlaps between 0.1 and 1 micrometer of the bricklaying overlap achieve significant reductions in voiding, yet provide complete enclosure of the IMD in the cells.
  • W plug processes which are well known to those versed in the art.
  • Other embodiments of the invention utilize alternative plug processes, such as Al plug, Cu plug, or silicide plug processes.
  • CMP chemical/mechanical polishing
  • Bonding metal patterns are then deposited, according to procedures well known to those versed in the art. Wires are bonded to bonding metal patterns and a passivation layer is formed, using processes, for both, that well known to those versed in the art.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processes semiconductor wafer is provided having all metal levels completed. A blanket dielectric layer is formed over the uppermost metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patters, after which a passivation layer is formed.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a continuation of currently pending U.S. non-provisional patent application Ser. No. 09/945,432, filed Sep. 4, 2001 now U.S. Pat. No.6,875,682, by Liu et al., titled “Novel Mesh Pad Structure to Eliminate IMD Crack on Pad,” the entire contents of which application is incorporated by reference herein.
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates generally to semiconductor integrated circuit processing and more particularly to contact pad structures that resist intermetal dielectric cracking.
(2) Description of Prior Art
Bonding pads are the interfaces between the integrated circuits contained in semiconductor chips and the chip package. A large number of bonding pads is required to transmit power, ground and impute/output signals to the chip devices. It is thus important that the bonding pad yield be sufficiently high to ensure a high per chip yield.
The general bonding pad structure consists of metal layers, emanating from the terminals of the chip devices, separated by intermetal dielectric (IMD) layers that are often silicon oxide. Metal vias, W is often used, pass through the IMD layers connecting the metal layers. Wires are bonded to a bonding metal pattern and to the chip package forming electrical connections between the chip and the package. A passivation layer covers the surface, except over the bonding sites, to seal the chip from contaminants and for scratch protection.
One mode of failure of the bonding pad relates to the peeling of the wire from the metal pattern due to forces exerted especially during the bonding process. This has been addressed in U.S. Pat. No. 6,002,179 to Chan et al., who teach a bonding pad structure with increased peeling resistance and in U.S. Pat. No. 5,731,243 to Peng et al., who show a cleaning method to ensure contamination free bonding. Another failure mode that has been observed relates to bonding pad peel back, where forces during wire bonding may cause a delaminating of one or more of the underlying layers. Bonding pad structures that resist bond pad peeling have been disclosed in U.S. Pat. No. 6,025,277 to Chen et al. and in U.S. Pat. No. 5,707,894 to Hsiao.
Another failure mode involves cracking of the IMD. Referring to FIGS. 1 a, 1 b, and 1 c, there is shown conventional via hole arrays. Regions 10 are IMD oxide layers, and regions 12 are metal filled via holes passing through the IMD. Cracks that are observed in the IMD are similar to that depicted in FIG. 2. These are cracks that propagate along the IMD layer avoiding the metal of the vias. Once a small crack is initiated it will, under stresses prevalent in the layer during processing, grow extensively. Approaches to alleviate this cracking of the IMD focus on producing IMD layers with low residual stress. Composite silicon oxide layers serve this purpose and are used, such as HDP plus PETEOS layers. However, even with composite silicon oxide layers to reduce stress, the IMD layer is not strong enough to withstand stresses encountered during chip packaging and IMD cracking is still observed.
SUMMARY OF THE INVENTION
It is a primary objective of the invention to provide a bonding pad structure that is immune to IMD cracking, withstanding even the stresses encountered during chip packaging. A novel mesh pad structure is proposed that will increase the bonding pad strength and eliminate extensive cracking of the IMD. Instead of traditional via holes, via trenches are formed through the IMD, dividing the remaining IMD into small cells. After the trenches are filled with metal the metal trenches enclose the cells. This increases the strength of the bonding pad so that IMD cracking is less likely to occur. Furthermore, even in the unlikely event of the initiation of an IMD crack, the crack will propagate no further than the metal trench.
A method is disclosed of forming a bonding pad that is immune to IMD cracking. A partially processed semiconductor wafer is provided having one to all but one metal levels completed. A blanket dielectric layer is formed over the metal level. Patterning and etching said dielectric layer horizontal and vertical arrays of trenches are formed passing through the dielectric layer and separating the dielectric layer into cells. The trenches are filled with a conducting material and, after performing CMP, bonding metal patterns are deposited. Wires are bonded onto said bonding metal patterns, after which a passivation layer is formed.
BRIEF DESCRIPTION OF THE DRAWINGS
In the accompanying drawing forming a material part of this description, there is shown:
FIGS. 1 a, 1 b and 1 c, Prior Art, show conventional via patterns.
FIG. 2 depicts a crack in the IMD of a conventional bonding pad.
FIG. 3 shows the basic pattern of the mesh via trenches.
FIG. 4 shows a mesh via trench structure without trench intersection.
FIG. 5 shows a mesh via trench structure with a brick-laying pattern.
FIG. 6 shows a mesh via trench structure with a modified brick-laying pattern.
 DESCRIPTION OF THE PREFERRED EMBODIMENTS
FIG. 3 illustrates the basic pattern of the novel mesh pad structure. The IMD, 10, is separated into cells by perpendicular arrays of metal filled via trenches. The array 14 is denoted the vertical array and the array 16 the horizontal array. The strength of the IMD-via trench structure is higher than that of the traditional IMD-via hole structures, such as those depicted in FIGS. 1 a, 1 b and 1 c. Thus, initiation of cracks in the IMD will occur less frequently for the mesh pad structure than for traditional structures utilizing via holes, such as those depicted in FIGS. 1 a, 1 b and 1 c. Furthermore, even in the remote possibility of initiation of a crack in the IMD of a mesh pad structure, the crack could only propagate as far as the metal filled trench which border the IMD cells. Thus the crack size is limited to be less than about the cell diagonal. In the case of traditional via hole pad structures, such as those depicted in FIGS. 1 a, 1 b and 1 c, the crack can propagate over large distances avoiding metal filled via holes. The reduced damage in the case of a mesh pad structure is manifested in substantial improvement of the quality and reliability of the bonding pad.
Basic elements of a bonding pad structure consist of metal layers, emanating from the terminals of the chip devices, separated by IMD layers. Also there is an IMD layer separating the uppermost metal layer from a bonding metal pattern that is formed over this IMD layer and there are metal connectors passing through the IMD layers connecting the metal layers to the bonding metal pattern. Wires are bonded to the bonding metal pattern and to the chip package forming electrical connections between the chip and the package. A passivation layer covers the surface, except over the bonding sites, to seal the chip from contaminants and for scratch protection.
A mesh via trench pattern can be used between any two levels of metal. However, its crack resistance properties are mostly utilized when used between the uppermost metal layer and the bonding metal pattern. To form the via trench pattern, a blanket dielectric, layer is first formed over the uppermost metal layer, using techniques well known to those skilled in the art. This dielectric layer is often silicon oxide. Composite layers are useful in relieving internal stress in the dielectric, stress that contributes to cracking in the dielectric layer, and preferred embodiments of the invention utilize such layers. Composite dielectric layers that are used to relieve internal stress include dual oxide layers, where, for instance, one of the layers is formed using HDP and the other using PETEOS, for example, 7000 Angstroms can be deposited using HDP and 17000 Angstroms using PETEOS.
However, composite dielectric layers do not protect the IMD layers from cracking as a result of stresses arising during chip packaging. This protection is achieved by the novel mesh pad structures of the embodiments of the invention. In contrast to the traditional bonding pad, in which via holes through the IMD layer are used to provide electrical connection between the metal layers, in a mesh pad structure electrical connection is achieved by via trenches. Via trenches are formed using the same well known processes as via holes, except that the shapes of the openings are rectangular-like. Via trench layouts are designed to separate the IMD into small cells, which, when the trenches are filled with metal, are essentially surrounded by metal filled trenches. For trench widths of between about 0.1 and 0.5 micrometers and for trench lengths between about 0.1 and 100 micrometers, which also provides the cell dimension, the IMD strength is significantly increased, and crack sizes are limited to less than about the cell diagonal. A via trench layout according to preferred embodiments of the invention in which trenches do not intersect is shown in FIG. 4. This form of layout will be referred to as the nonintersecting layout. Arrays of horizontal, 16, and vertical, 14, trenches nearly divide the IMD layer, 10, into cells though they do not intersect. Trench widths are between about 0.1 and 0.5 micrometers and the trench lengths are between about 0.1 and 100 micrometers for trenches in both the vertical and horizontal arrays. In this layout there is a separation between a trench and its perpendicular neighbors. An advantage of nonintersecting via trenches is that there is a tendency toward void formation when filling an intersection with metal and nonintersecting via trenches avoids this void formation. In this layout the trenches do not fully surround the IMD. However, if the ratio between the spacing of perpendicular trenches, 24, to the spacing of parallel trenches, 26, is kept small, less then about ⅕, cracks will not propagate much beyond a cell before being stopped by a trench. A spacing of perpendicular trenches greater then about 0.1 micrometers is required, however, to avoid overlap. Another trench layout according to preferred embodiments of the invention is referred to as the bricklaying layout and is depicted in FIG. 5. Here the trenches, 14 and 16, do actually divide the IMD layer, 10, into closed cells. However, even though the vertical and horizontal trench arrays do not completely cross each other, there is, T-shaped overlap at positions, 18. Void formation still occurs during metal filling of the trenches at overlaps such at positions 18, however this is at a reduced frequency as compared with crossing intersections. Trench widths are between about 0.1 and 0.5 micrometers and the trench separation is between about 0.1 and 10 micrometers for horizontal trenches and between about 0.1 and 10 micrometers for vertical trenches. To further reduce the tendency for void formation at the overlaps, a trench layout, denoted as the modified bricklaying layout and shown in FIG. 6, is utilized in other preferred embodiments of the invention. Except for overlap region, 20, the trench layout and dimensions for the modified bricklaying layout are similar to the trench layout and dimension for the bricklayer layout. The overlap region, 20, for the modified bricklaying layout is reduced from that of the overlap region, 18, for the bricklaying layout and results in a reduction in voiding. Modified bricklaying overlaps between 0.1 and 1 micrometer of the bricklaying overlap achieve significant reductions in voiding, yet provide complete enclosure of the IMD in the cells.
Filling of the via trenches with conductive material is accomplished, in preferred embodiments of the invention, using W plug processes, which are well known to those versed in the art. Other embodiments of the invention utilize alternative plug processes, such as Al plug, Cu plug, or silicide plug processes. Following the metal filling of the trenches, chemical/mechanical polishing (CMP), a process well known to practitioners of the art, is used to planarize the surface. Bonding metal patterns are then deposited, according to procedures well known to those versed in the art. Wires are bonded to bonding metal patterns and a passivation layer is formed, using processes, for both, that well known to those versed in the art.
While the invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made without departing from the spirit and scope of the invention.

Claims (15)

1. A method of forming a bonding pad, comprising:
providing a partially processed semiconductor wafer having all metal levels completed;
forming a blanket dielectric layer over an uppermost metal level;
patterning and etching said dielectric layer to form horizontal and vertical arrays of trenches passing through said dielectric layer;
filling said trenches with a conducting material;
planarizing said conducting material to obtain a top surface;
forming bonding metal patterns over said top surface; and
forming a passivation layer over said top surface and said bonding metal patterns;
wherein said vertical array of trenches comprises a first plurality of trenches each having a first length and a first width, the first being greater than the first width; said horizontal arrays of trenches comprises a second plurality of trenches each having a second length and a second width, the second length being greater than the second width; and wherein none of said first plurality of trenches intersects with any of said second plurality of trenches.
2. The method of claim 1, wherein the separation between neighboring horizontal trenches and neighboring vertical trenches is between 0.1 and 10 micrometers.
3. The method of claim 2, wherein the ratio between the spacing of perpendicular trenches to the spacing of parallel trenches is less than about ⅕.
4. The method of claim 3, wherein the spacing of perpendicular trenches is greater than about 0.1 micrometers.
5. The method of claim 1, wherein the lengths of each of the plurality of trenches of said vertical array of trenches are oriented substantially perpendicular to the lengths of each of the plurality of trenches of said horizontal array of trenches.
6. A method of forming a bonding pad, comprising:
providing a partially processed semiconductor wafer having all metal levels completed;
forming a blanket dielectric layer over the uppermost metal level;
patterning and etching said dielectric layer to form horizontal and vertical arrays of trenches passing through said dielectric layer according to a brick laying layout or a modified brick laying layout;
filling said trenches with a conducting material;
planarizing said to obtain a top surface;
forming bonding metal patterns over said top surface;
bonding wires onto said bonding metal patterns; and
forming a passivation layer over said top surface and said bonding layer patterns.
7. The method of claim 6 wherein said dielectric layer is composed of materials from the group: silicon oxide, silicon nitride, silicon oxynitride.
8. The method of claim 6 wherein said dielectric layer is a composite of dielectric layers.
9. The method of claim 6 wherein the filling of said trenches with a conducting material is accomplished using a plug process.
10. The method of claim 6 wherein the filling of said trenches with a conducting material is accomplished using a W plug process.
11. The method of claim 6 wherein the filling of said trenches with a conducting material is accomplished using a plug process from the group: Al plug, Cu plug and silicide plug.
12. The method of claim 6 wherein the width of said trenches is between 0.1 and 0.5 micrometers.
13. The method of claim 6 wherein the separation between neighboring horizontal trenches is between 0.1 and 10 micrometers and neighboring vertical trenches is between 0.1 and 10 micrometers.
14. The method of claim 6 wherein the overlap area in said modified bricklaying layout is between 0.1 and 1 micrometer of the overlap area of said bricklaying layout.
15. A method comprising:
providing a semiconductor wafer having an upper metal layer;
forming a blanket dielectric layer over the upper metal level;
forming a conductive pattern in the blanket dielectric layer, said conductive pattern comprising horizontal and vertical arrays of trenches passing through said dielectric layer and having a bricklaying layout, said trenches being at least partially filled with a conducting material; and
forming a bonding metal pattern on said conductive pattern.
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060125118A1 (en) * 2004-12-10 2006-06-15 Elpida Memory, Inc. Semiconductor device having a bonding pad structure including an annular contact

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100652395B1 (en) * 2005-01-12 2006-12-01 삼성전자주식회사 Semiconductor device having reduced die-warpage and method of manufacturing the same
US7741716B1 (en) 2005-11-08 2010-06-22 Altera Corporation Integrated circuit bond pad structures
KR100763709B1 (en) * 2005-12-28 2007-10-04 동부일렉트로닉스 주식회사 Method for forming pad of semiconductor device
US7679180B2 (en) * 2006-11-07 2010-03-16 Taiwan Semiconductor Manufacturing Co., Ltd. Bond pad design to minimize dielectric cracking
US20130154099A1 (en) 2011-12-16 2013-06-20 Semiconductor Components Industries, Llc Pad over interconnect pad structure design
CN103579033B (en) * 2012-07-26 2016-08-03 中芯国际集成电路制造(上海)有限公司 A kind of weld pad for wafer acceptability test
JP6064628B2 (en) * 2013-01-29 2017-01-25 富士通株式会社 Semiconductor device
US9536848B2 (en) * 2014-10-16 2017-01-03 Globalfoundries Inc. Bond pad structure for low temperature flip chip bonding
US9984987B2 (en) 2016-08-05 2018-05-29 Nanya Technology Corporation Semiconductor structure and manufacturing method thereof
KR102484394B1 (en) * 2017-12-06 2023-01-03 삼성전자주식회사 Semiconductor devices

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731243A (en) 1995-09-05 1998-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cleaning residue on a semiconductor wafer bonding pad
US6002179A (en) 1997-09-15 1999-12-14 Winbond Electronics Corporation Bonding pad structure for integrated circuit (I)
US6025277A (en) 1997-05-07 2000-02-15 United Microelectronics Corp. Method and structure for preventing bonding pad peel back
US6232662B1 (en) 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US6236114B1 (en) 1999-05-06 2001-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding pad structure
US6313540B1 (en) 1998-12-25 2001-11-06 Nec Corporation Electrode structure of semiconductor element
US6465895B1 (en) 2001-04-05 2002-10-15 Samsung Electronics Co., Ltd. Bonding pad structures for semiconductor devices and fabrication methods thereof

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5707894A (en) 1995-10-27 1998-01-13 United Microelectronics Corporation Bonding pad structure and method thereof
US6249055B1 (en) * 1998-02-03 2001-06-19 Advanced Micro Devices, Inc. Self-encapsulated copper metallization
US6396158B1 (en) * 1999-06-29 2002-05-28 Motorola Inc. Semiconductor device and a process for designing a mask
US6326301B1 (en) * 1999-07-13 2001-12-04 Motorola, Inc. Method for forming a dual inlaid copper interconnect structure

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731243A (en) 1995-09-05 1998-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method of cleaning residue on a semiconductor wafer bonding pad
US6025277A (en) 1997-05-07 2000-02-15 United Microelectronics Corp. Method and structure for preventing bonding pad peel back
US6002179A (en) 1997-09-15 1999-12-14 Winbond Electronics Corporation Bonding pad structure for integrated circuit (I)
US6232662B1 (en) 1998-07-14 2001-05-15 Texas Instruments Incorporated System and method for bonding over active integrated circuits
US6313540B1 (en) 1998-12-25 2001-11-06 Nec Corporation Electrode structure of semiconductor element
US6236114B1 (en) 1999-05-06 2001-05-22 Taiwan Semiconductor Manufacturing Co., Ltd. Bonding pad structure
US6465895B1 (en) 2001-04-05 2002-10-15 Samsung Electronics Co., Ltd. Bonding pad structures for semiconductor devices and fabrication methods thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060125118A1 (en) * 2004-12-10 2006-06-15 Elpida Memory, Inc. Semiconductor device having a bonding pad structure including an annular contact
US7863705B2 (en) * 2004-12-10 2011-01-04 Elpida Memory, Inc. Semiconductor device having a bonding pad structure including an annular contact

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