US7038506B2 - Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system - Google Patents

Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system Download PDF

Info

Publication number
US7038506B2
US7038506B2 US10806938 US80693804A US7038506B2 US 7038506 B2 US7038506 B2 US 7038506B2 US 10806938 US10806938 US 10806938 US 80693804 A US80693804 A US 80693804A US 7038506 B2 US7038506 B2 US 7038506B2
Authority
US
Grant status
Grant
Patent type
Prior art keywords
clock
signal
main
system
generated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
US10806938
Other versions
US20050212571A1 (en )
Inventor
Ranjan Om
Fabio Carlucci
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Pvt Ltd
STMicroelectronics SRL
Original Assignee
STMicroelectronics Pvt Ltd
STMicroelectronics SRL
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 – G06F13/00 and G06F21/00
    • G06F1/24Resetting means

Abstract

A digital logic system includes a reset input for receiving a reset signal, and a clock input for receiving an externally generated main clock signal. An ancillary clock generator generates an ancillary clock signal. A clock selection multiplexer has a first input for receiving the externally generated main clock signal, a second input for receiving the internally generated ancillary clock signal, and an output for providing the externally generated main clock signal or the internally generated ancillary clock signal to a functional circuit. A resettable edge-triggered shift register has a first input for receiving the externally generated main clock signal, a second input for receiving the reset signal, and an output connected to the clock selection multiplexer for deselecting the internally generated ancillary clock signal and selecting the externally generated main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.

Description

FIELD OF THE INVENTION

The present invention relates to digital logic systems including a reset signal generator for resetting a system at power-up and/or during operation, and a clock generator for generating a main clock signal that is distributed to functional circuits of the system.

BACKGROUND OF THE INVENTION

Initialization of digital logic systems at power-up or at certain occurrences during operation is a critical phase. Automotive applications as well as many other micro-controller based supervising and diagnostic systems must ensure the highest level of safety, including diagnostic capabilities even under harsh environmental conditions. To ensure that the system is able to recover from a malfunction and perform appropriate corrective actions under any circumstances, it becomes important that the system be able to correctly exit from a system reset phase.

Apart from ensuring the correct generation of the reset signal, it is fundamentally important to timely provide the necessary clock signal to all the functional circuits of the system. Because of these requirements in practically any safety type system, many approaches have been developed. Most of these approaches are based on the availability of multiple clock inputs to the system. The system can switch from a failing clock source to a correctly working one, either under microprocessor control or by appropriate hardware functioning independently and/or cooperatively with the application software running on the system.

One known approach is described in U.S. Pat. No. 5,510,741 Childs, in which a reset and clock circuit provides a valid power-up reset signal prior to distribution of a clock signal for placing the system in a known state. Another reset and clock circuit maintains distribution of the clock signal for a predetermined time interval following a drop of the power supply voltage.

Notwithstanding the efforts so far expended there is still a need for a relatively straightforward and cost effective implementation capable of preventing corruption or loss of data that may occur because of glitches or other imperfections of the externally generated main clock signal being distributed to the functional circuits of the system. This is during the critical exiting from a system reset phase, and the resumption of normal operation of the system, whether it follows a power-up or an execution of a recovery routine from a malfunction.

SUMMARY OF THE INVENTION

In view of the foregoing background, an object of the present invention is to provide a straightforward and effective approach for automatically selecting for distribution to the functional circuits of a digital logic system an internally generated ancillary clock signal by temporarily deselecting the externally generated main clock signal at any reset, and thereafter switching back to distribute the externally generated main clock signal after having verified a certain number of main clock edges following a reset signal.

To complete the reset phase and ensure that system is gracefully put into a safe state in case of an external clock failure across a reset event, the stability of an internal clock generator is to be ensured. In other words, the internal clock generator should be stable enough (after relaxation) to be able to allow the system to run diagnostics and signal the failure of the system clock.

The maximum frequency of the internally generated ancillary clock should remain lower than a safe value for assuring that no part of the device may malfunction when fed with the internally generated clock. This is assured by employing an internal clock having a frequency lower than the frequency of the externally generated main system clock.

By including an on-chip (internal) ancillary clock generator having a sufficient short-term frequency stability to ensure a stable clock frequency for the normal duration of a reset phase, and by automatically selecting an internally generated ancillary clock in lieu of the externally generated main clock for a programmable interval of time, corresponding to a certain number of main clock edges to be correctly monitored before reverting to distribute the main clock signal throughout the system, the probability of corruption or loss of data during the critical phase of completing the reset and resuming normal operation may be made practically negligible.

The added ancillary internal clock generator may be a straightforward ring/RC oscillator that is slightly affected in its functionality by the external environmental conditions and thermo-mechanical stresses. Though unsuitable to ensure a long-term stability such as provided by a quartz crystal stabilized external main clock generator, the ancillary internal ring/RC oscillator does not suffer from thermo-mechanical stresses and other abruptly changing environmental conditions that, by contrast, are likely to severely effect short term stability of the main external clock generator.

According to the present invention, during the critical phases of reset and of resuming normal operation, whether at power up or at any other moment of operation of the system, initialization errors following a reset that may arise from accidental concurrent imprecisions of the externally generated main clock signal are effectively prevented.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram of a digital logic system including an ancillary clock generator and a clock selection device in accordance with the present invention; and

FIG. 2 is a more detailed block diagram of the digital logic system illustrated in FIG. 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, the integrated digital logic system is formed in an IC chip identified by the partial dotted line contour. As shown, a main external clock signal that may be generated by a dedicated crystal oscillator is fed to the integrated system. Moreover, the system receives appropriate reset commands generated by dedicated circuitry according to common practices in the art.

According to the present invention, an ancillary internal clock generator (OSCILLATOR), for example, in the form of a ring/RC oscillator having sufficient short-term frequency stability with respect to the normal duration of a reset phase, is integrated on the system chip. Its output is coupled to one input node of a selection multiplexer, to a second input node of which is fed the externally generated main clock signal.

The selected clock is made available at the output of the multiplexer and is distributed to the functional circuits of the system (SYSTEM CLOCK). Automatic selection of the ancillary internally generated clock signal is implemented upon the arrival of a system reset pulse to the resettable shift register (FF-DELAY), which is fed with the externally generated main clock.

The edge triggered resettable shift register (FF-DELAY) deselects the internally generated ancillary clock, which is automatically selected at the arrival of the system reset pulse, and selects the externally generated main clock after detecting a programmable number of main clock edges following the reset pulse.

Moreover, the shift register (FF-DELAY) acts as a filter for glitches that may be present in the external clock signal. Glitches on the external clock are potentially dangerous since they can force the delay block (FF-DELAY), i.e., the mux selector, to change state, and consequently, prematurely and unduly switch the clock to a still unstable external source. The deeper (i.e., the larger the number of stages of the shift register) the multiplexer selecting shift register (FF-DELAY) is designed, the more robust the structure is against glitches based upon the hypothesis that a glitch may determine a spurious extra clock cycle. Theoretically, a glitch can even be so short to induce incorrect states in the logic circuitry it reaches (like a timing violation). To contrast this, the shift register may be designed to minimize such an effect.

For example, the external clock can be applied to a single toggle-type flip-flop whose output is then fed in lieu of the external clock to the rest (input) of the edge-triggered resettable shift register (counter). In this way a glitch may be able to corrupt only the first flip-flop but the effect of this anomaly would be significantly reduced at the output of the shift register, thus preventing spurious selections in the multiplexer.

The result is that the system switches to the externally generated main clock only after correct activity of the external main clock generator has been verified. This prevents the occurrence of corruptions due to glitches or imprecisions that could accidentally occur on the externally generated main clock signal during the critical reset phase.

The ancillary internal clock generator has sufficient short-term frequency stability covering the expected duration of a reset phase, and differently from the external main clock generator, is much less likely to be affected by external environmental conditions and thermo-mechanical stresses. The number of external clock edges to be counted before returning to distribute the externally generated main clock signal can be programmed according to needs and according to the stability characteristics of the ancillary internal clock generator.

A sample embodiment of the present invention in a common microcontroller system is schematically illustrated in FIG. 2. The clock signal generated by the device is input to a circuit CLOCK & RESET DISTRIBUTION that distributes the recovered clock and the reset signal to all the functional blocks of the microcontroller system.

Claims (20)

1. A digital logic system comprising:
a reset input for receiving a reset signal;
a clock input for receiving an externally generated main clock signal;
an ancillary clock generator for generating an ancillary clock signal independent of the externally generated main clock signal and having short term frequency stability in relation to an expected duration of a system reset phase;
at least one functional circuits;
a clock selection multiplexer having a first input for receiving the externally generated main clock signal, a second input for receiving the ancillary clock signal, and an output for providing the externally generated main clock signal or the ancillary clock signal to said at least one functional circuit; and
a resettable edge-triggered shift register having a first input for receiving the externally generated main clock signal, a second input for receiving the reset signal, and an output connected to said clock selection multiplexer for deselecting the ancillary clock signal and selecting the externally generated main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.
2. A digital logic system according to claim 1, wherein said ancillary clock generator comprises a ring/RC oscillator.
3. A digital logic system according to claim 1, wherein said resettable edge-triggered shift register comprises a plurality of stages for preventing glitches that may be present on the externally generated main clock signal.
4. A digital logic system according to claim 1, further comprising a toggle flip-flop between the first input of said resettable edge-triggered shift register and the clock input.
5. A digital logic system according to claim 1, wherein a frequency of the ancillary clock signal is less than a frequency of the main clock signal.
6. A digital logic system comprising:
a reset input for receiving a reset signal;
a clock input for receiving an externally generated main clock signal;
an ancillary clock generator for generating an ancillary clock signal independent of the externally generated main clock signal;
a clock selection multiplexer having a first input for receiving the externally generated main clock signal, a second input for receiving the ancillary clock signal, and an output for providing the externally generated main clock signal or the ancillary clock signal; and
a shift register having a first input for receiving the externally generated main clock signal, a second input for receiving the reset signal, and an output connected to said clock selection multiplexer for deselecting the ancillary clock signal and selecting the externally generated main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.
7. A digital logic system according to claim 6, wherein said ancillary clock generator comprises a ring/RC oscillator.
8. A digital logic system according to claim 6, wherein said shift register comprises a plurality of stages.
9. A digital logic system according to claim 6, further comprising a toggle flip-flop between the first input of said shift register and the clock input.
10. A digital logic system according to claim 6, wherein a frequency of the ancillary clock signal is less than a frequency of the main clock signal.
11. A digital system comprising:
a reset circuit for generating a reset signal;
a main clock generator for generating a main clock signal;
an ancillary clock generator for generating an ancillary clock signal independent of the externally generated main clock signal;
at least one functional circuit;
a clock selection multiplexer having a first input for receiving the main clock signal, a second input for receiving the ancillary clock signal, and an output for providing the main clock signal or the ancillary clock signal to said at least one functional circuit; and
a resettable edge-triggered shift register having a first input for receiving the main clock signal, a second input for receiving the reset signal, and an output connected to said clock selection multiplexer for deselecting the ancillary clock signal and selecting the main clock signal after detecting a certain number of edges of the main clock signal following the reset signal.
12. A digital system according to claim 11, wherein said ancillary clock generator comprises a ring/RC oscillator.
13. A digital system according to claim 11, wherein said shift register comprises a plurality of stages.
14. A digital system according to claim 11, further comprising a toggle flip-flop between the first input of said shift register and said main clock generator.
15. A digital system according to claim 11, wherein a frequency ol the ancillary clock signal is less than a frequency of the main clock signal.
16. A method for resetting a digital logic system comprising a reset input for receiving a reset signal and a clock input for receiving an externally generated main clock signal, the method comprising:
generating an ancillary clock signal independent of the externally generated main clock signal;
providing the externally generated main clock signal and the ancillary clock signal to respective first and second inputs of a clock selection multiplexer, and providing at an output of the clock selection multiplexer the externally generated main clock signal or the ancillary clock signal to at least one functional circuit; and
providing the externally generated main clock signal and the reset signal to respective first and second inputs of a resettable edge-triggered shift register, and an output of the resettable edge-triggered shift register being connected to the clock selection multiplexer for deselecting the ancillary clock signal and selecting the externally generated main clock signal after the resettable edge-triggered shift register detects a certain number of edges of the main clock signal following the reset signal.
17. A method according to claim 16, wherein the ancillary clock generator comprises a ring/RC oscillator.
18. A method according to claim 16, wherein the resettable edge-triggered shift register comprises a plurality of stages.
19. A method according to claim 16, wherein the digital logic system further comprises a toggle flip-flop between the first input of the resettable edge-triggered shift register and the clock input.
20. A method according to claim 16, wherein a frequency of the ancillary clock signal is less than a frequency of the main clock signal.
US10806938 2004-03-23 2004-03-23 Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system Active US7038506B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10806938 US7038506B2 (en) 2004-03-23 2004-03-23 Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10806938 US7038506B2 (en) 2004-03-23 2004-03-23 Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system

Publications (2)

Publication Number Publication Date
US20050212571A1 true US20050212571A1 (en) 2005-09-29
US7038506B2 true US7038506B2 (en) 2006-05-02

Family

ID=34989080

Family Applications (1)

Application Number Title Priority Date Filing Date
US10806938 Active US7038506B2 (en) 2004-03-23 2004-03-23 Automatic selection of an on-chip ancillary internal clock generator upon resetting a digital system

Country Status (1)

Country Link
US (1) US7038506B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080313487A1 (en) * 2007-06-12 2008-12-18 Yoshinori Mochizuki Processing device and clock control method
US20110102027A1 (en) * 2009-09-18 2011-05-05 Renesas Electronics Corporation Semiconductor integrated device and control method thereof
US8890588B2 (en) * 2013-03-28 2014-11-18 Texas Instruments Incorporated Circuits and methods for asymmetric aging prevention
US9509318B2 (en) 2015-03-13 2016-11-29 Qualcomm Incorporated Apparatuses, methods, and systems for glitch-free clock switching

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7724894B2 (en) * 2006-03-06 2010-05-25 General Instrument Corporation Maintaining line voltage during reset
US8775854B2 (en) * 2009-11-13 2014-07-08 Marvell World Trade Ltd. Clock turn-on strategy for power management

Citations (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5025387A (en) * 1988-09-06 1991-06-18 Motorola, Inc. Power saving arrangement for a clocked digital circuit
US5218704A (en) * 1989-10-30 1993-06-08 Texas Instruments Real-time power conservation for portable computers
US5510741A (en) 1995-08-30 1996-04-23 National Semiconductor Corporation Reset and clock circuit for providing valid power up reset signal prior to distribution of clock signal
US5517109A (en) * 1992-11-03 1996-05-14 Thomson Consumer Electronics, Inc. Apparatus within an integrated circuit for automatically detecting a test mode of operation of the integrated circuit and selecting a test clock signal
US5652536A (en) * 1995-09-25 1997-07-29 Cirrus Logic, Inc. Non-glitch clock switching circuit
US5801561A (en) * 1995-05-01 1998-09-01 Intel Corporation Power-on initializing circuit
US5877636A (en) * 1996-10-18 1999-03-02 Samsung Electronics Co., Ltd. Synchronous multiplexer for clock signals
US5912570A (en) * 1997-01-08 1999-06-15 Nokia Mobile Phones Limited Application specific integrated circuit (ASIC) having improved reset deactivation
US6147537A (en) * 1997-11-10 2000-11-14 Nec Corporation Reset circuit for flipflop
US6292038B1 (en) * 1998-12-23 2001-09-18 Intel Corporation Smooth clock switching for power managed PCI adapters
US6473852B1 (en) * 1998-10-30 2002-10-29 Fairchild Semiconductor Corporation Method and circuit for performing automatic power on reset of an integrated circuit
US6487668B2 (en) * 1994-06-20 2002-11-26 C. Douglass Thomas Thermal and power management to computer systems
US6771100B2 (en) * 2001-06-29 2004-08-03 Renesas Technology Corp. Clock control circuit
US6806755B1 (en) * 2001-04-23 2004-10-19 Quantum 3D Technique for glitchless switching of asynchronous clocks
US6809556B1 (en) * 2003-09-04 2004-10-26 Texas Instruments Incorporated Self-compensating glitch free clock switch
US6891409B2 (en) * 2002-07-16 2005-05-10 Fujitsu Limited Semiconductor device

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5025387A (en) * 1988-09-06 1991-06-18 Motorola, Inc. Power saving arrangement for a clocked digital circuit
US5218704A (en) * 1989-10-30 1993-06-08 Texas Instruments Real-time power conservation for portable computers
US5930516A (en) * 1989-10-30 1999-07-27 Texas Instruments Incorporated Real time power conservation for computers
US5517109A (en) * 1992-11-03 1996-05-14 Thomson Consumer Electronics, Inc. Apparatus within an integrated circuit for automatically detecting a test mode of operation of the integrated circuit and selecting a test clock signal
US6487668B2 (en) * 1994-06-20 2002-11-26 C. Douglass Thomas Thermal and power management to computer systems
US5801561A (en) * 1995-05-01 1998-09-01 Intel Corporation Power-on initializing circuit
US5510741A (en) 1995-08-30 1996-04-23 National Semiconductor Corporation Reset and clock circuit for providing valid power up reset signal prior to distribution of clock signal
US5652536A (en) * 1995-09-25 1997-07-29 Cirrus Logic, Inc. Non-glitch clock switching circuit
US5877636A (en) * 1996-10-18 1999-03-02 Samsung Electronics Co., Ltd. Synchronous multiplexer for clock signals
US5912570A (en) * 1997-01-08 1999-06-15 Nokia Mobile Phones Limited Application specific integrated circuit (ASIC) having improved reset deactivation
US6147537A (en) * 1997-11-10 2000-11-14 Nec Corporation Reset circuit for flipflop
US6473852B1 (en) * 1998-10-30 2002-10-29 Fairchild Semiconductor Corporation Method and circuit for performing automatic power on reset of an integrated circuit
US6292038B1 (en) * 1998-12-23 2001-09-18 Intel Corporation Smooth clock switching for power managed PCI adapters
US6806755B1 (en) * 2001-04-23 2004-10-19 Quantum 3D Technique for glitchless switching of asynchronous clocks
US6771100B2 (en) * 2001-06-29 2004-08-03 Renesas Technology Corp. Clock control circuit
US6891409B2 (en) * 2002-07-16 2005-05-10 Fujitsu Limited Semiconductor device
US6809556B1 (en) * 2003-09-04 2004-10-26 Texas Instruments Incorporated Self-compensating glitch free clock switch

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080313487A1 (en) * 2007-06-12 2008-12-18 Yoshinori Mochizuki Processing device and clock control method
US8015428B2 (en) * 2007-06-12 2011-09-06 Renesas Electronics Corporation Processing device and clock control method
US20110102027A1 (en) * 2009-09-18 2011-05-05 Renesas Electronics Corporation Semiconductor integrated device and control method thereof
US8154325B2 (en) * 2009-09-18 2012-04-10 Renesas Electronics Corporation Semiconductor integrated device and control method thereof
US8890588B2 (en) * 2013-03-28 2014-11-18 Texas Instruments Incorporated Circuits and methods for asymmetric aging prevention
US9509318B2 (en) 2015-03-13 2016-11-29 Qualcomm Incorporated Apparatuses, methods, and systems for glitch-free clock switching

Also Published As

Publication number Publication date Type
US20050212571A1 (en) 2005-09-29 application

Similar Documents

Publication Publication Date Title
US7310759B1 (en) Techniques for mitigating, detecting, and correcting single event upset effects in systems using SRAM-based field programmable gate arrays
US6194969B1 (en) System and method for providing master and slave phase-aligned clocks
US5754833A (en) Method and apparatus for providing synchronous data transmission between digital devices operating at frequencies having a P/Q integer ratio
US5612643A (en) Semiconductor integrated circuit which prevents malfunctions caused by noise
US4796211A (en) Watchdog timer having a reset detection circuit
US5811998A (en) State machine phase lock loop
US5359232A (en) Clock multiplication circuit and method
US20060220716A1 (en) Electronic circuitry protected against transient disturbances and method for simulating disturbances
US7320091B2 (en) Error recovery within processing stages of an integrated circuit
US4254492A (en) Redundant clock system utilizing nonsynchronous oscillators
US5862373A (en) Pad cells for a 2/N mode clocking scheme
US6782068B1 (en) PLL lockout watchdog
US6553496B1 (en) Integration of security modules on an integrated circuit
US6341355B1 (en) Automatic clock switcher
US5867453A (en) Self-setup non-overlap clock generator
US5802132A (en) Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
US5371764A (en) Method and apparatus for providing an uninterrupted clock signal in a data processing system
US5159217A (en) Brownout and power-up reset signal generator
US6141774A (en) Peripheral device with access control
US6938183B2 (en) Fault tolerant processing architecture
US4920540A (en) Fault-tolerant digital timing apparatus and method
US7401273B2 (en) Recovery from errors in a data processing apparatus
US20090115468A1 (en) Integrated Circuit and Method for Operating an Integrated Circuit
US5537655A (en) Synchronized fault tolerant reset
US6385274B1 (en) Watchdog timer for resetting microcomputer before runaway

Legal Events

Date Code Title Description
AS Assignment

Owner name: STMICROELECTRONICS S.R.L., ITALY

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OM, RANJAN;CARLUCCI, FABIO;REEL/FRAME:015522/0469;SIGNING DATES FROM 20040512 TO 20040519

Owner name: STMICROELECTRONICS PVT. LTD., INDIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:OM, RANJAN;CARLUCCI, FABIO;REEL/FRAME:015522/0469;SIGNING DATES FROM 20040512 TO 20040519

CC Certificate of correction
FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

MAFP

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553)

Year of fee payment: 12