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US7033891B2 - Trench gate laterally diffused MOSFET devices and methods for making such devices - Google Patents

Trench gate laterally diffused MOSFET devices and methods for making such devices Download PDF

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US7033891B2
US7033891B2 US10269126 US26912602A US7033891B2 US 7033891 B2 US7033891 B2 US 7033891B2 US 10269126 US10269126 US 10269126 US 26912602 A US26912602 A US 26912602A US 7033891 B2 US7033891 B2 US 7033891B2
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trench
gate
layer
drain
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Peter H. Wilson
Steven Sapp
Neill Thornton
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Fairchild Semiconductor Corp
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    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7834Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a non-planar structure, e.g. the gate or the source or the drain being non-planar
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66613Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66659Lateral single gate silicon transistors with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
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    • H01L29/76Unipolar devices, e.g. field effect transistors
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    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7831Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
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    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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    • H01L29/0843Source or drain regions of field-effect devices
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    • H01L29/4175Source or drain electrodes for field effect devices for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
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    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356Disposition, e.g. buried gate electrode
    • H01L29/4236Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
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    • H01L29/42312Gate electrodes for field effect devices
    • H01L29/42316Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform

Abstract

A MOSFET device for RF applications that uses a trench gate in place of the lateral gate used in lateral MOSFET devices is described. The trench gate in the devices of the invention is provided with a single, short channel for high frequency gain. The device of the invention is also provided with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Such features allow these devices to maintain the advantages of the LDMOS structure (better linearity), thereby increasing the RF power gain. The trench gate LDMOS of the invention also reduces the hot carrier effects when compared to regular LDMOS devices by reducing the peak electric field and impact ionization. Thus, the devices of the invention will have a better breakdown capability.

Description

FIELD OF THE INVENTION

The invention generally relates to methods for fabricating integrated circuits (ICs) and semiconductor devices and the resulting structures. More particularly, the invention relates to metal oxide semiconductor field effect transistor (MOSFET) devices and methods for making such devices. Even more particularly, the invention relates to trench gate laterally-diffused MOSFET devices and methods for making such devices.

BACKGROUND OF THE INVENTION

In IC fabrication, devices such as transistors may be formed on a semiconductor wafer or substrate, which is typically made of silicon. MOSFET devices are widely used in numerous electronic apparatus, including automotive electronics, disk drives and power supplies. Generally, these apparatus function as switches and are used to connect a power supply to a load.

One of the applications in which MOSFET devices have been used is for radio frequency (RF) applications. Such “RF” MOSFET devices generally utilize standard lateral transistors. See, for example, the lateral MOSFET device described in U.S. Pat. No. 5,949,104, as well as the device illustrate in FIG. 1. Such lateral MOSFET devices often have a diffused source that allows a backside contact for improved thermal and parasitic reductions.

Recent advances in lateral (or laterally-diffused) MOSFET (LDMOS) devices have improved the performance and cost characteristics of lateral MOSFET devices when compared to vertical MOSFET devices for RF power amplifiers in base stations applications. Such RF LDMOS devices have been particularly useful for wireless base station applications. The RF vertical (or vertically-diffused) VDMOS structure unfortunately suffers from certain limitations relative to the LDMOS such as high output capacitance (which decreases efficiency), decreased power gain, narrowing of the usable bandwidth, and source inductance that decreases the operating efficiency.

It has been proposed to use a trench gate in place of the lateral gate so often used in RF MOSFET devices. See, for example, U.S. Pat. No. 6,400,003. The proposed structure in that patent, unfortunately suffers from several setbacks. First, the trench gate has a dual diffused channel on both sides of the trench gate. Second, the drain region extends entirely around the body portion.

SUMMARY OF THE INVENTION

The invention provides a MOSFET device for RF applications that uses a trench gate in place of the lateral gate used in lateral MOSFET devices. The trench gate in the devices of the invention is provided with a single, short channel for high frequency gain. The device of the invention is also provided with an asymmetric oxide in the trench gate, as well as LDD regions that lower the gate-drain capacitance for improved RF performance. Such features allow these devices to maintain the advantages of the LDMOS structure (better linearity), thereby increasing the RF power gain. The trench gate LDMOS of the invention also reduces the hot carrier effects when compared to regular LDMOS devices by reducing the peak electric field and impact ionization. Thus, the devices of the invention will have a better breakdown capability.

The invention includes a MOSFET device comprising a trench gate structure containing an asymmetric insulating layer and a plurality of drift drain regions with a first drift region extending under the gate structure. The invention also includes a semiconductor device and an electronic apparatus containing such a MOSFET device. The invention further includes a RF MOSFET device comprising a trench gate structure containing a single channel and an asymmetric oxide layer and a plurality of drift drain regions with a first drift region extending under the gate structure. The invention still further includes a MOSFET device, comprising a trench gate structure containing an asymmetric insulating layer and a plurality of drift drain regions with a first drift region extending under the gate structure.

The inventions also includes a method for making a MOSFET device by providing a trench gate structure containing an asymmetric insulating layer and providing a plurality of drift drain regions with a first drift region extending under the gate structure. The invention further includes a method for making a making a MOSFET device by providing a substrate, providing a trench in the substrate, filling the trench with an insulating layer, providing a second trench in the insulating layer such that the second trench is not symmetric relative to the first trench, filling the second trench with a conductive material, and providing a plurality of dopant regions adjacent the trench with a first dopant region extending under the trench. The invention still further includes a method for making a making a MOSFET device by providing a substrate having an epitaxial upper surface, providing a trench in the upper surface, filling the trench with an oxide layer, providing a second trench in the oxide layer so that the second trench is not symmetric relative to the first trench, filling the second trench with a conductive material, and providing a plurality of dopant regions adjacent the trench and within the epitaxial layer, wherein the plurality of dopant regions contains a first dopant region extending under the trench and a second dopant region with a dopant concentration higher than the first dopant region. The invention also includes MOSFET devices made by such methods.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1–6 are views of one aspect of the MOSFET devices and methods of making the MOSFET devices according to the invention, in which:

FIG. 1 illustrates a prior art MOSFET device;

FIG. 2 illustrates a MOSFET device in one aspect of the invention;

FIGS. 3–5 illustrate various configurations of the MOSFET device during its manufacture in one aspect of the invention; and

FIG. 6 illustrates a MOSFET device in another aspect of the invention.

FIGS. 1–6 presented in conjunction with this description are views of only particular—rather than complete—portions of the MOSFET devices and methods of making the MOSFET devices according to the invention. Together with the following description, the Figures demonstrate and explain the principles of the invention.

DETAILED DESCRIPTION OF THE INVENTION

The following description provides specific details in order to provide a thorough understanding of the invention. The skilled artisan, however, would understand that the invention can be practiced without employing these specific details. Indeed, the invention can be practiced by modifying the illustrated system and method and can be used in conjunction with apparatus and techniques conventionally used in the industry. For example, the MOSFET devices are described for RF applications, but could be used in non-RF applications such as switching.

As noted above, the invention generally comprises a structure that combines the benefits of the LDMOS structure (i.e., a low gate-to-drain capacitance and a good linearity) with the benefits of a short gate channel. Thus, any structure that combines theses feature can be employed in the invention. In one aspect of the invention, these benefits are combined by using a trench gate laterally-diffused MOSFET device as described below. By using this structure, the breakdown capabilities of conventional LDMOS structure can be improved. In addition, the carrier effects (i.e., injection) will be improved, and the peak electric field and impact ionization of the drain region will be reduced.

To achieve these benefits, the structure illustrated in the FIG. 2 is used in the invention. In FIG. 2, the MOSFET device 5 comprises a semiconductor substrate 10, typically of monocrystalline silicon (Si), with an epitaxial layer 60 formed thereon. In one aspect of the invention, the silicon substrate 10 can have a first conductivity type, such as B (boron), with a dopant concentration of about 2×1019 atoms/cm3. In another aspect of the invention, the substrate can have a resistivity ranging from 0.005 to 0.01 ohm centimeter. A contact region 55 can be located on the “backside” of the substrate 10. In one aspect of the invention, the contact region 55 is a metal contact. In one aspect of the invention, the depth of the epitaxial layer 60 can range from about 3 to about 9 microns and can have a first conductivity dopant concentration of about 1.2×1015 atoms/cm3. In another aspect of the invention, the epitaxial layer can have a resistivity ranging from about 20 to about 30 ohm centimeters.

A gate structure 90 is located between source region 95 and drain region 100. The gate structure 90 is separated from the source region 95 by a body region 40. And the gate structure 90 is separated from the drain region 100 by a lightly doped drain (LDD) region 75.

The gate structure 90 contains gate conductor 30, as well as an insulating layer 80 surrounding that part of the gate conductor 30 in the trench 85. The MOSFET device contains channel region 25 of a first conductivity type (p-type in one aspect of the invention) that is adjacent to the side of the insulating layer 80 of the gate structure 90 nearest the source region 95. Because of this configuration of the gate in the trench 85, the gate structure 90 is often referred to as a trench gate in which length of the gate is controlled by the depth of the trench 85. In one aspect of the invention, the trench depth can range from about 0.5 to about 4.0 microns. In another aspect of the invention, the depth of the trench can be about 1 to about 2 microns. In yet another aspect of the invention, the trench depth can be about 1.5 microns.

With this configuration of the gate structure 90, the thin insulating layer between the channel region 25 and the conducting layer 30 operates as a high-quality gate insulating layer. In addition, the insulating layer 80 (which in one aspect of the invention is asymmetric) can also reduce the gate to drain capacitance (Cgd). As well, the thick bottom oxide (with a thickness of about 1 kÅ to about 4 kÅ) can reduce the gate-to-drain overlap capacitance and thereby lower the gate charge.

By applying a positive gate voltage to device 5, the channel region 25 can change the polarity from a first conductivity type to a second conductivity type. This polarity change—called inversion—permits the carriers to drift (e.g., flow) from the dopant region 70 to the lightly doped drain (LDD) region 75. Thus, the channel region 25 can be modulated by a positive gate voltage.

Source region 95 comprises dopant region 35 and source electrode 15. The dopant region 35 is typically of a first conductivity type with a concentration ranging from about 5×1015 to about 1×1019 atoms/cm3. In one aspect of the invention, the concentration of dopant region 35 is about 1×1019 atoms/cm3. The source electrode 15 is located over dopant region 35 and overlaps body region 40. The body region 40 is typically of a first conductivity type with a concentration greater than or equal to the concentration of the epitaxial layer 60. In one aspect of the invention, the concentration of body region 40 is about 2.5×1015 atoms/cm3.

As known in the art, source electrode 15 can be separated from the body region 40 by dopant region 70 of a second conductivity type. As well, the source electrode 15 can be separated from the gate structure 90 by a distance (a) that depends on the desired characteristics of the gate. Generally, this distance (a) can range from about 0.5 to about 1.5 microns.

The drain region 100 contains a drain electrode 20 overlying a portion of LDD region 75. In one aspect of the invention, the drain electrode 20 is separated from the gate by a distance (b) depending on the desired drain-source breakdown voltage. In one aspect of the invention, this distance typically can be between about 3 to about 5 microns. In another aspect of the invention, the drain electrode is separated from gate by a distance of about 4 microns. The drain electrode 20 is also separated from the LDD region 75 by a dopant region 65. In one aspect of the invention, the dopant region 65 is of a second conductivity type with a concentration of ranging from about 1×1015 to 1×1016 atoms/cm3.

The LDD region 75 contains a first drain drift region 45 of the MOS structure. The first drain drift region 45 is formed completely within the epitaxial layer 60, with a part underlying the trench 85. In one aspect of the invention, the first enhanced drain drift region 45 has second conductivity type when the epitaxial layer 60 has a first conductivity type. In one aspect of the invention, the first enhanced drain drift region 45 can have a dopant concentration ranging from about 1×1011 to about 5×1013 atoms/cm3. In another aspect of the invention, this dopant concentration is about 2×1012 atoms/cm3. The first enhanced drain region 45 can have lateral dimensions ranging from about 0.5 to about 5.0 microns and vertical dimensions ranging from about 0.2 to about 0.5 microns

The LDD region 75 also contains a second enhanced drain drift region 50 that is adjacent to and contacting the first drain drift region 45. The second drain drift region 50 is also formed completely within the epitaxial layer 60. In one aspect of the invention, the second drain drift region 50 has second conductivity type when the epitaxial layer 60 has a first conductivity type. In one aspect of the invention, the second drain drift region can have a dopant concentration greater than the first drain drift region 45. In one aspect of the invention, the dopant concentration can range from about 1×1011 to about 1×1014 atoms/cm3. In another aspect of the invention, this dopant concentration is about 1×103 atoms/cm3. The second drain region 50 can have lateral dimensions ranging from more than 0 to about 5 microns and vertical dimensions substantially similar to the first drain drift region 45.

Using the two drain drift regions 45 and 50 in LDD region 75 allows one to increase the maximum drain drift current density of the device, as well as increase the drain-to-source breakdown voltage. Indeed, the effective electrical field in the LDD region 75 is strong enough to cause the avalanche effect of carrier multiplication at certain critical concentration of carriers. Thus, the critical carrier concentration can be related to the breakdown voltage in device 5. In one aspect of the invention, three or more drift regions that are uniformly graded from a light dopant concentration to a heavier dopant concentration can be used as LDD region 75.

In one aspect of the invention, the second drain drift region 50 has a concentration higher than the concentration of the first drain drift region 45. This configuration can result in the redistribution of the critical electrical fields in the channel region 25 and can result in an increase of the drain-to-source breakdown voltage. The maximum current density in the source-drain channel of the device can also be increased when the total concentration in the drain drift region is increased.

Using the two drain drift regions 45 and 50 also allows the LDD region 75 to act as a non-linear resistor, especially when the applied voltage is varied. This non-linear behavior suggests the existence of a pinch-off point in the LDD region 75. In other words, as the applied voltage is increase, the depletion region present in the LDD region 75 can expand and lead to a pinch-off point.

Configuring the LDD region 75 as indicated above can also be used to support efficient operation of device 5. The dopant profile of the LDD region 75 can be controlled by having different sectors each with a different dopant concentration. The different doping concentrations can be configured to ensure that any breakdown does not occur near the upper surface of the device, but deeper within the LDD region 75 near the interface of the dopant region 65 and LDD region 75. The ability to configure the LDD region 75 in this manner must be carefully balanced, of course, with the other operating parameters of the device such as Cgd and the drain to source capacitance (Cds).

As noted above, the drift drain region 45 extends under the trench 85. In one aspect of the invention, the dopant concentration of the region under the trench 85 should be higher than the concentration of the remainder of LDD region 75. This region is an extension of LDD region 75 and helps create a current flow from the drain to the source. The concentration of this region should be tailored to the required drain-source breakdown voltage, as well as to not to substantially increase the gate to drain capacitance.

By using a trench gate, the devices of the invention are able to achieve several improvements over existing LDMOS devices. First, the devices of the invention have an improved RF power gain and efficiency due to the reduction of the Cgd resulting from the asymmetric insulating material in the trench and the shorter channel. Second, the devices of the invention are able to reduce the hot carrier effects by reducing the peak electric field. Third, the operating voltages of the devices of the invention can be increased above the capabilities of existing LDMOS devices.

The device illustrated in FIG. 2 can be made by any process resulting in the depicted structure. In one aspect of the invention, the process described below and illustrated in FIGS. 3–5 is used to make the structure depicted in FIG. 2.

Referring to FIG. 3, the process begins with substrate 10. Any substrate known in the art can be used in the invention. Suitable substrates include silicon wafers, epitaxial Si layers, polysilicon layers, bonded wafers such as used in silicon-on-insulator (SOI) technologies, and/or amorphous silicon layers, all of which may be doped or undoped. If the substrate is undoped, it can then be doped with a first conductivity type dopant to the concentration noted above by any method known in the art.

Next, the backside contact region 55 is formed. In one aspect of the invention, the contact region 55 can be formed by a metallization process. Then, if the epitaxial layer 60 is not already present, it is formed on the substrate 10 by any process known in the art. If the epitaxial layer is not doped in situ, then the desired doping concentration can be formed using any known process. Next, the various dopant regions 35, 40, 45, 50, 65, and 70 can be formed as known in the art.

As depicted in FIG. 3, trench 85 is then formed in the upper surface of the epitaxial layer 60. The trench 85 can be formed by any suitable masking and etching process known in the art. For example, the etching process can begin by forming a mask (not shown) with an opening(s) where the trench(es) will be formed. The silicon in the trench is then removed by etching through the mask. The parameters of the etching process are controlled to preferably form round bottom corners, smooth and continuous sidewalls, flat and clean trench bottom surfaces, and trench depth, thereby maintaining the integrity of the device characteristics using the trenches. After forming the trenches, the mask is removed by any suitable process known in the art.

As depicted in FIG. 4, the trench 85 is then filled with the material for insulating layer 80. This material for the insulating layer can be any high-quality insulating material known in the art, such as silicon nitride, silicon oxide, or silicon oxynitride. In one aspect of the invention, the insulating layer is silicon oxide (or “oxide”). In this aspect of the invention, an oxide layer is provided on the top surface of the epitaxial layer 60, including the trench 85. Any suitable method known in the art—including oxidation and deposition—yielding a high quality oxide layer can be used to provide this oxide layer. The portions of the oxide layer on the surface of the epitaxial layer 60 are then removed by any known process, leaving the oxide solely within the trench 85.

Next, a second trench 105 is formed within the insulating layer 80. This second trench can be formed in a manner substantially similar to the method used to form the first trench 85, with a few modifications. The first modification is that the mask material and the etching chemical may be different to account for the difference between etching silicon and etching the material for the insulating layer 80, e.g., oxide. The second modification is that the width of the mask openings for the second trench 105 will be smaller than the first trench 85.

After the second trench 105 is formed, the conductive material 110 for the gate, source, and drain is deposited to fill and overflow the remaining portions of the second trench 105 as illustrated in FIG. 5. The conductive layer can be suitable material that can be used as a gate conductor, such as a metal, metal alloy, or polysilicon. In one aspect of the invention, the conductive layer is heavily doped polysilicon. The conductive layer can be deposited using any known deposition process, including chemical vapor deposition process. Optionally, the conductive layer 110 can be doped with any suitable dopant to the desired concentration, particularly when the conductive layer is polysilicon or when a silicide can be used to red e the resistance of the gate. Excess (and unneeded) portions of the conductive layer 110 are then removed using any conventional process to form the gate conductor 30, the source electrode 15, and the drain electrode 20. In another aspect of the invention, additional deposition, masking, and etching steps can be used if the conductive material for the gate conductor, the source electrode, and the drain electrode will be different.

After the above processes are concluded, conventional processing can continue to finish the MOSFET device. As well, other processing needed to complete other parts of the semiconductor device can then be carried out, as known in the art.

In the aspect of the invention described above and illustrated in the Figures, the first conductivity type is a p-type dopant and the second conductivity type is an n-type dopant. In another aspect of the invention, the device can be configured with the first conductivity type being a n-type dopant and the second conductivity type dopant being a p-type dopant.

The devices of the invention can also be modified to contain more than a single gate. For example, as depicted in FIG. 6, the devices of the invention can contain two trench gates between the source and drain. In the aspect of the invention shown in FIG. 6, the device can contain one gate with a symmetric oxide and one gate with an asymmetric oxide. In another aspect of the invention, both gates can contain an asymmetric oxide. The device in FIG. 6 is manufactured similar to the device depicted in FIG. 2, except that two trenches with two gate structures could be provided instead of a single trench.

Having described these aspects of the invention, it is understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof.

Claims (39)

1. A method for making a MOSFET, comprising:
providing a substrate including an epitaxial layer;
forming a first trench in the epitaxial layer;
filling the first trench with an insulating layer;
forming a second trench in the insulating layer such that the second trench is not symmetric relative to the first trench;
filling the second trench with a conductive material; and
forming a plurality of dopant regions adjacent the first trench with a first one of the plurality of dopant regions extending under the first trench.
2. The method of claim 1 further comprising forming the plurality of dopant regions within the epitaxial layer.
3. The method of claim 2 wherein a second one of the plurality of dopant regions is formed adjacent the first one of the plurality of dopant regions, the second one of the plurality of dopant regions having a higher dopant concentration than the first one of the plurality of dopant regions.
4. The method of claim 3 wherein the substrate and the epitaxial layer are of a first conductivity type, and the first one of the plurality of dopant regions and the second one of the plurality of dopant regions are of a second conductivity type.
5. A method for making a MOSFET, comprising:
providing a substrate having an epitaxial layer thereon;
forming a first trench in the epitaxial layer;
filling the first trench with an oxide layer;
forming a second trench in the oxide layer so that the second trench is not symmetric relative to the first trench;
filling the second trench with a conductive material; and
forming a plurality of dopant regions adjacent the first trench and within the epitaxial layer, wherein the plurality of dopant regions contains a first dopant region extending under the first trench and a second dopant region with a dopant concentration higher than the first dopant region.
6. The method of claim 5 wherein the substrate and the epitaxial layer are of a first conductivity type and the first and second dopant regions are of a second conductivity type.
7. A method of forming a MOSFET, comprising:
forming a first trench in a silicon region extending over a substrate, the silicon region and the substrate being of a first conductivity type but having different doping concentrations;
filling the first trench with an insulating layer;
forming a second trench in the insulating layer, the second trench being asymmetrical relative to the first trench such that a spacing between a first sidewall of the first trench and a corresponding first sidewall of the second trench is different than a spacing between a second sidewall of the first trench and a corresponding second sidewall of the second trench;
forming a conductive material in the second trench; and
forming a first drift region of a second conductivity type in the silicon region, the first drift region extending under the first trench.
8. The method of claim 7 further comprising:
forming second and third drift regions of the second conductivity type in the silicon region, the second drift region separating the third drift region from the first trench.
9. The method of claim 8 wherein the first, second, and third drift regions are contiguous, the second drift region having a higher doping concentration than the first drift region, and the third drift region having a higher doping concentration than the second drift region.
10. The method of claim 7 wherein the remaining portion of the insulating layer after forming the second trench is thicker along a bottom of the first trench than along one of the sidewalls of the first trench.
11. The method of claim 7 wherein the remaining portion of the insulating layer after forming the second trench is thicker along a first sidewall of the first trench than along a second sidewall of the first trench opposing the first sidewall.
12. The method of claim 7 wherein the silicon region is an epitaxial layer, the method further comprising:
forming the epitaxial layer over the substrate.
13. A MOSFET comprising:
a first silicon region of a first conductivity type;
a gate trench extending into the first silicon region, the gate trench having an asymmetric insulating layer along two of its opposing sidewalls;
a source region having a dopant region of a second conductivity type, the dopant region laterally extending along one side of the gate trench to contact a source electrode; and
a lightly doped drain region of the second conductivity type laterally extending below and along an opposing side of said one side of the gate trench to contact a drain electrode,
wherein a spacing between the drain electrode and the gate trench is greater than a corresponding spacing between the source electrode and the gate trench.
14. The MOSFET of claim 13 wherein the lightly doped drain region partially extends up along a first sidewall of the gate trench such that a channel region along the first sidewall between the source region and the lightly doped drain region extends along only the vertical dimension.
15. The MOSFET of claim 13 wherein the lightly doped drain region comprises at least first and second drift regions, the second drift region being laterally separated from the gate trench at least by the first drift region, the first drift region having a lower doping concentration than the second drift region.
16. The MOSFET of claim 13 wherein the asymmetric insulating layer extends along a bottom of the trench, the asymmetric insulating layer being thicker along the bottom of the gate trench than along the sidewall of the gate trench adjacent the source region.
17. The MOSFET of claim 13 wherein the asymmetric insulating layer is thicker along the sidewall of the gate trench adjacent the lightly doped drain region than along the sidewall of the gate trench adjacent the source region.
18. The MOSFET of claim 13 being configured such that in the on state a conduction channel is formed along the sidewall of the gate trench adjacent the source region while no conduction channel is formed along the sidewall of the gate trench adjacent the lightly doped drain region.
19. The MOSFET of claim 13 wherein the first silicon region is an epitaxial layer over a substrate, the dopant region in the source region and the epitaxial layer being electrically connected together so as to be biased to the same potential.
20. The MOSFET of claim 13 wherein the MOSFET is a radio frequency MOSFET.
21. A MOSFET comprising:
a first silicon region of a first conductivity type;
a gate trench extending into the first silicon region, the gate trench having an asymmetric insulating layer along two of its opposing sidewalls;
a source region having a dopant region of a second conductivity type, the dopant region laterally extending along one side of the gate trench to contact a source electrode; and
a lightly doped drain region of the second conductivity type laterally extending below and along an opposing side of said one side of the gate trench to contact a drain electrode, the lightly doped drain region comprising at least first and second drift regions, the second drift region being laterally separated from the gate trench at least by the first drift region, the first drift region having a lower doping concentration than the second drift region.
22. The MOSFET of claim 21 wherein the lightly doped drain region partially extends up along a first sidewall of the gate trench such that a channel region along the first sidewall between the source region and the lightly doped drain region extends only along the vertical dimension.
23. The MOSFET of claim 21 wherein a spacing between the drain electrode and the gate trench is greater than a corresponding spacing between the source electrode and the gate trench.
24. The MOSFET of claim 21 wherein the asymmetric insulating layer extends along a bottom of the gate trench, the asymmetric insulating layer being thicker along the bottom of the gate trench than along the sidewall of the gate trench adjacent the source region.
25. The MOSFET of claim 21 wherein the asymmetric insulating layer is thicker along the sidewall of the gate trench adjacent the lightly doped drain region than along the sidewall of the gate trench adjacent the source region.
26. The MOSFET of claim 21 being configured such that in the on state a conduction channel is formed along the sidewall of the gate trench adjacent the source region while no conduction channel is formed along the sidewall of the gate trench adjacent the lightly doped drain region.
27. The MOSFET of claim 21 wherein the first silicon region is an epitaxial layer over a substrate, the dopant region in the source region and the epitaxial layer being electrically connected together so as to be biased to the same potential.
28. A MOSFET comprising:
an epitaxial layer of a first conductivity type over a substrate;
a gate trench extending into the epitaxial layer, the gate trench having an asymmetric insulating layer along two of its opposing sidewalls;
a source region having a dopant region of a second conductivity type in the epitaxial layer, the dopant region laterally extending along one side of the gate trench to contact a source electrode; and
a lightly doped drain region of the second conductivity type laterally extending below and along an opposing side of said one side of the gate trench to contact a drain electrode, the lightly doped drain region comprising at least first and second drift regions, the second drift region being laterally separated from the gate trench at least by the first drift region, the first drift region having a lower doping concentration than the second drift region,
wherein a spacing between the drain electrode and the gate trench is greater than a corresponding spacing between the source electrode and the gate trench.
29. The MOSFET of claim 28 wherein the asymmetric insulating layer extends along a bottom of the trench, the asymmetric insulating layer being thicker along the bottom of the gate trench than along the sidewall of the gate trench adjacent the source region.
30. The MOSFET of claim 28 wherein the asymmetric insulating layer is thicker along the sidewall of the gate trench adjacent the lightly doped drain region than along the sidewall of the gate trench adjacent the source region.
31. The MOSFET of claim 28 being configured such that in the on state a conduction channel is formed along the sidewall of the gate trench adjacent the source region while no conduction channel is formed along the sidewall of the gate trench adjacent the lightly doped drain region or along a bottom of the gate trench.
32. A MOSFET comprising:
a first silicon region of a first conductivity type;
first and second gate trenches extending into the first silicon region, the first gate trench having an asymmetric insulating layer along two of its opposing sidewalls, the second gate trench having a symmetric insulating layer along two of its opposing sidewalls;
a plurality of dopant regions in the first silicon region, a first one of the plurality of dopant regions having a second conductivity type and laterally extending along one side of the second gate trench to contact a source electrode, and a second one of the plurality of dopant regions of the second conductivity type separating the first and second gate trenches; and
a lightly doped drain region of the second conductivity type laterally extending along one side of the first gate trench to contact a drain electrode, the lightly doped drain region further extending below both the first and second gate trenches.
33. The MOSFET of claim 32 wherein the lightly doped drain region comprises at least first and second drift regions, the second drift region being laterally separated from the first gate trench at least by the first drift region, the first drift region having a lower doping concentration than the second drift region.
34. The MOSFET of claim 32 wherein the lightly doped drain region partially extends up along a first sidewall of the second gate trench such that a channel region along the first sidewall between the first one of the plurality of dopant regions and the lightly doped drain region extends only along the vertical dimension.
35. The MOSFET of claim 32 wherein a spacing between the drain electrode and the first gate trench is greater than a spacing between the source electrode and the second gate trench.
36. The MOSFET of claim 32 wherein:
the symmetric insulating layer extends along a bottom of the second gate trench, the symmetric insulating layer being thicker along the bottom of the second gate trench than along the sidewalls of the second gate trench, and
the asymmetric insulating layer extends along a bottom of the first gate trench, the asymmetric insulating layer being thicker along the bottom of the first gate trench than along a sidewall of the first gate trench adjacent the second one of the plurality of dopant regions.
37. The MOSFET of claim 32 wherein the asymmetric insulating layer is thicker along a sidewall of the first gate trench adjacent the lightly doped drain region than along a sidewall of the first gate trench adjacent the second one of the plurality of dopant regions.
38. The MOSFET of claim 32 being configured such that in the on state a conduction channel is formed along those sidewalls of the first and second gate trenches adjacent the first one and second one of the plurality of dopant regions while no conduction channel is formed along a sidewall of the first gate trench adjacent the lightly doped drain region.
39. The MOSFET of claim 32 wherein the first silicon region is an epitaxial layer over a substrate.
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Cited By (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060194392A1 (en) * 2003-03-10 2006-08-31 Fuji Electric Device Technology Co., Ltd. Mis-type semiconductor device
US20070063294A1 (en) * 2004-03-24 2007-03-22 Texas Instruments Incorporated Semiconductor Device Having a Fully Silicided Gate Electrode and Method of Manufacture Therefor
US20070262398A1 (en) * 2006-05-11 2007-11-15 Fultec Semiconductor, Inc. High voltage semiconductor device with lateral series capacitive structure
US20090072241A1 (en) * 2007-09-14 2009-03-19 Cree, Inc. Grid-umosfet with electric field shielding of gate oxide
WO2009042547A1 (en) * 2007-09-27 2009-04-02 Fairchild Semiconductor Corporation Semiconductor device with (110)-oriented silicon
US20090213660A1 (en) * 2008-02-25 2009-08-27 Tower Semiconductor Ltd. Three-Terminal Single Poly NMOS Non-Volatile Memory Cell
US20090212342A1 (en) * 2008-02-25 2009-08-27 Tower Semiconductor Ltd. Asymmetric Single Poly NMOS Non-Volatile Memory Cell
US20090236657A1 (en) * 2008-03-24 2009-09-24 Micron Technology, Inc. Impact ionization devices and methods of making the same
US20090294846A1 (en) * 2008-05-28 2009-12-03 Ptek Technology Co., Ltd. Trench-type power mos transistor and integrated circuit utilizing the same
US20100052046A1 (en) * 2005-07-25 2010-03-04 Fairchild Semiconductor Corporation Semiconductor structures formed on substrates and methods of manufacturing the same
US20100059797A1 (en) * 2008-09-09 2010-03-11 Tat Ngai (110)-oriented p-channel trench mosfet having high-k gate dielectric
US20100123171A1 (en) * 2008-04-18 2010-05-20 Robert Kuo-Chang Yang Multi-level Lateral Floating Coupled Capacitor Transistor Structures
US20100301403A1 (en) * 2009-05-29 2010-12-02 Won Gi Min Semiconductor device with multiple gates and doped regions and method of forming
CN101997033A (en) * 2009-08-14 2011-03-30 万国半导体股份有限公司 Shielded gate trench mosfet device and fabrication
US20110121379A1 (en) * 2008-02-25 2011-05-26 Tower Semiconductor Ltd. Three-Terminal Single Poly NMOS Non-Volatile Memory Cell With Shorter Program/Erase Times
US20110163374A1 (en) * 2010-01-06 2011-07-07 Ptek Technology Co., Ltd. Trench-typed power mos transistor and method for making the same
US20110193142A1 (en) * 2010-02-05 2011-08-11 Ring Matthew A Structure and Method for Post Oxidation Silicon Trench Bottom Shaping
CN102194699A (en) * 2010-03-11 2011-09-21 万国半导体股份有限公司 Shielded gate trench MOS with improved source pickup layout
US20120175679A1 (en) * 2011-01-10 2012-07-12 Fabio Alessio Marino Single structure cascode device
US20130109143A1 (en) * 2011-08-11 2013-05-02 Volterra Semiconductor Corporation Vertical Gate LDMOS Device
US8652916B2 (en) 2011-02-11 2014-02-18 International Business Machines Corporation Self aligned impact-ionization MOS (I-MOS) device and methods of manufacture
US8704296B2 (en) 2012-02-29 2014-04-22 Fairchild Semiconductor Corporation Trench junction field-effect transistor
US8816445B2 (en) 2013-01-14 2014-08-26 Ptek Technology Co., Ltd. Power MOSFET device with a gate conductor surrounding source and drain pillars
US20160027874A1 (en) * 2014-07-28 2016-01-28 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor device having super junction structure and method for manufacturing the same
US9768293B1 (en) * 2016-05-24 2017-09-19 Taiwan Semiconductor Manufacturing Co., Ltd. Laterally diffused metal-oxide-semiconductor (LDMOS) transistor with a vertical channel region

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7282401B2 (en) * 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) * 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US20070132016A1 (en) * 2005-12-12 2007-06-14 Elwin Matthew P Trench ld structure
US7700441B2 (en) * 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7473976B2 (en) 2006-02-16 2009-01-06 Fairchild Semiconductor Corporation Lateral power transistor with self-biasing electrodes
US7602001B2 (en) * 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US8236648B2 (en) * 2007-07-27 2012-08-07 Seiko Instruments Inc. Trench MOS transistor and method of manufacturing the same
US7829945B2 (en) * 2007-10-26 2010-11-09 International Business Machines Corporation Lateral diffusion field effect transistor with asymmetric gate dielectric profile
US7649224B2 (en) * 2007-12-13 2010-01-19 Sanyo Electric Co., Ltd. DMOS with high source-drain breakdown voltage, small on- resistance, and high current driving capacity
US8193580B2 (en) * 2009-08-14 2012-06-05 Alpha And Omega Semiconductor, Inc. Shielded gate trench MOSFET device and fabrication
US8236651B2 (en) * 2009-08-14 2012-08-07 Alpha And Omega Semiconductor Incorporated Shielded gate trench MOSFET device and fabrication
CN102623501B (en) * 2011-01-28 2015-06-03 万国半导体股份有限公司 Shielded gate trench MOSFET with increased source-metal contact
US8618601B2 (en) * 2009-08-14 2013-12-31 Alpha And Omega Semiconductor Incorporated Shielded gate trench MOSFET with increased source-metal contact
CN102299073A (en) * 2010-06-25 2011-12-28 无锡华润上华半导体有限公司 Vdmos device and manufacturing method thereof
US8921933B2 (en) * 2011-05-19 2014-12-30 Macronix International Co., Ltd. Semiconductor structure and method for operating the same
US8829603B2 (en) 2011-08-18 2014-09-09 Alpha And Omega Semiconductor Incorporated Shielded gate trench MOSFET package
US8748981B2 (en) 2012-09-07 2014-06-10 Freescale Semiconductor, Inc. Semiconductor device and related fabrication methods
US9070576B2 (en) * 2012-09-07 2015-06-30 Freescale Semiconductor Inc. Semiconductor device and related fabrication methods
US9735243B2 (en) * 2013-11-18 2017-08-15 Infineon Technologies Ag Semiconductor device, integrated circuit and method of forming a semiconductor device
CN104716179A (en) * 2013-12-11 2015-06-17 上海华虹宏力半导体制造有限公司 LDMOS device with deep hole and manufacturing method thereof
US9385229B2 (en) 2014-09-24 2016-07-05 Freescale Semiconductor, Inc. Semiconductor device with improved breakdown voltage
US9306060B1 (en) 2014-11-20 2016-04-05 Freescale Semiconductor Inc. Semiconductor devices and related fabrication methods
CN105990423A (en) * 2015-02-02 2016-10-05 无锡华润上华半导体有限公司 Transverse dual-field-effect tube

Citations (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3404295A (en) 1964-11-30 1968-10-01 Motorola Inc High frequency and voltage transistor with added region for punch-through protection
US3412297A (en) 1965-12-16 1968-11-19 United Aircraft Corp Mos field-effect transistor with a onemicron vertical channel
US3497777A (en) 1967-06-13 1970-02-24 Stanislas Teszner Multichannel field-effect semi-conductor device
US3564356A (en) 1968-10-24 1971-02-16 Tektronix Inc High voltage integrated circuit transistor
US4003072A (en) 1972-04-20 1977-01-11 Sony Corporation Semiconductor device with high voltage breakdown resistance
US4300150A (en) 1980-06-16 1981-11-10 North American Philips Corporation Lateral double-diffused MOS transistor device
US4326332A (en) 1980-07-28 1982-04-27 International Business Machines Corp. Method of making a high density V-MOS memory array
US4337474A (en) 1978-08-31 1982-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4579621A (en) 1983-07-08 1986-04-01 Mitsubishi Denki Kabushiki Kaisha Selective epitaxial growth method
US4638344A (en) 1979-10-09 1987-01-20 Cardwell Jr Walter T Junction field-effect transistor controlled by merged depletion regions
US4639761A (en) 1983-12-16 1987-01-27 North American Philips Corporation Combined bipolar-field effect transistor resurf devices
US4698653A (en) 1979-10-09 1987-10-06 Cardwell Jr Walter T Semiconductor devices controlled by depletion regions
US4716126A (en) 1986-06-05 1987-12-29 Siliconix Incorporated Fabrication of double diffused metal oxide semiconductor transistor
US4746630A (en) 1986-09-17 1988-05-24 Hewlett-Packard Company Method for producing recessed field oxide with improved sidewall characteristics
US4754310A (en) 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
US4774556A (en) 1985-07-25 1988-09-27 Nippondenso Co., Ltd. Non-volatile semiconductor memory device
US4801986A (en) 1987-04-03 1989-01-31 General Electric Company Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
US4821095A (en) 1987-03-12 1989-04-11 General Electric Company Insulated gate semiconductor device with extra short grid and method of fabrication
US4823176A (en) 1987-04-03 1989-04-18 General Electric Company Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area
US4853345A (en) 1988-08-22 1989-08-01 Delco Electronics Corporation Process for manufacture of a vertical DMOS transistor
US4868624A (en) 1980-05-09 1989-09-19 Regents Of The University Of Minnesota Channel collector transistor
US4893160A (en) 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
US4914058A (en) 1987-12-29 1990-04-03 Siliconix Incorporated Grooved DMOS process with varying gate dielectric thickness
US4941026A (en) 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
US4967245A (en) 1988-03-14 1990-10-30 Siliconix Incorporated Trench power MOSFET device
US4974059A (en) 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
US4990463A (en) 1988-07-05 1991-02-05 Kabushiki Kaisha Toshiba Method of manufacturing capacitor
US4992390A (en) 1989-07-06 1991-02-12 General Electric Company Trench gate structure with thick bottom oxide
US5027180A (en) 1986-12-11 1991-06-25 Mitsubishi Electric Corporation Double gate static induction thyristor
US5072266A (en) 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US5071782A (en) 1990-06-28 1991-12-10 Texas Instruments Incorporated Vertical memory cell array and method of fabrication
US5079608A (en) 1990-11-06 1992-01-07 Harris Corporation Power MOSFET transistor circuit with active clamp
US5105243A (en) 1987-02-26 1992-04-14 Kabushiki Kaisha Toshiba Conductivity-modulation metal oxide field effect transistor with single gate structure
US5142640A (en) 1988-06-02 1992-08-25 Seiko Epson Corporation Trench gate metal oxide semiconductor field effect transistor
US5164325A (en) 1987-10-08 1992-11-17 Siliconix Incorporated Method of making a vertical current flow field effect transistor
US5164802A (en) 1991-03-20 1992-11-17 Harris Corporation Power vdmosfet with schottky on lightly doped drain of lateral driver fet
US5216275A (en) 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US5219793A (en) 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
US5219777A (en) 1991-06-14 1993-06-15 Gold Star Electron Co., Ltd. Metal oxide semiconductor field effect transistor and method of making the same
US5233215A (en) 1992-06-08 1993-08-03 North Carolina State University At Raleigh Silicon carbide power MOSFET with floating field ring and floating field plate
US5262336A (en) 1986-03-21 1993-11-16 Advanced Power Technology, Inc. IGBT process to produce platinum lifetime control
US5268311A (en) 1988-09-01 1993-12-07 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
US5275965A (en) 1992-11-25 1994-01-04 Micron Semiconductor, Inc. Trench isolation using gated sidewalls
US5294824A (en) 1992-07-31 1994-03-15 Motorola, Inc. High voltage transistor having reduced on-resistance
US5298761A (en) 1991-06-17 1994-03-29 Nikon Corporation Method and apparatus for exposure process
US5300447A (en) 1992-09-29 1994-04-05 Texas Instruments Incorporated Method of manufacturing a minimum scaled transistor
US5326711A (en) 1993-01-04 1994-07-05 Texas Instruments Incorporated High performance high voltage vertical transistor and method of fabrication
US5350937A (en) 1991-10-08 1994-09-27 Semiconductor Energy Laboratory Co., Ltd. Non-volatile memory device having a floating gate
US5365102A (en) 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
US5366914A (en) 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
US5389815A (en) 1992-04-28 1995-02-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor diode with reduced recovery current
US5405794A (en) 1994-06-14 1995-04-11 Philips Electronics North America Corporation Method of producing VDMOS device of increased power density
US5418376A (en) 1993-03-02 1995-05-23 Toyo Denki Seizo Kabushiki Kaisha Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure
US5424231A (en) 1994-08-09 1995-06-13 United Microelectronics Corp. Method for manufacturing a VDMOS transistor
US5430324A (en) 1992-07-23 1995-07-04 Siliconix, Incorporated High voltage transistor having edge termination utilizing trench technology
US5430311A (en) 1991-09-20 1995-07-04 Hitachi, Ltd. Constant-voltage diode for over-voltage protection
US5429977A (en) 1994-03-11 1995-07-04 Industrial Technology Research Institute Method for forming a vertical transistor with a stacked capacitor DRAM cell
US5434435A (en) 1994-05-04 1995-07-18 North Carolina State University Trench gate lateral MOSFET
US5436189A (en) 1989-10-03 1995-07-25 Harris Corporation Self-aligned channel stop for trench-isolated island
US5438215A (en) 1993-03-25 1995-08-01 Siemens Aktiengesellschaft Power MOSFET
US5473176A (en) 1993-09-01 1995-12-05 Kabushiki Kaisha Toshiba Vertical insulated gate transistor and method of manufacture
US5473180A (en) 1993-07-12 1995-12-05 U.S. Philips Corporation Semiconductor device with an MOST provided with an extended drain region for high voltages
US5474943A (en) 1993-03-15 1995-12-12 Siliconix Incorporated Method for fabricating a short channel trenched DMOS transistor
US5519245A (en) 1989-08-31 1996-05-21 Nippondenso Co., Ltd. Insulated gate bipolar transistor with reverse conducting current
US5541425A (en) 1994-01-20 1996-07-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having trench structure
US5554862A (en) 1992-03-31 1996-09-10 Kabushiki Kaisha Toshiba Power semiconductor device
US5567635A (en) 1992-03-23 1996-10-22 International Business Machines Corporation Method of making a three dimensional trench EEPROM cell structure
US5567634A (en) 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
US5572048A (en) 1992-11-20 1996-11-05 Hitachi, Ltd. Voltage-driven type semiconductor device
US5578851A (en) 1994-08-15 1996-11-26 Siliconix Incorporated Trenched DMOS transistor having thick field oxide in termination region
US5581100A (en) 1994-08-30 1996-12-03 International Rectifier Corporation Trench depletion MOSFET
US5583065A (en) 1994-11-23 1996-12-10 Sony Corporation Method of making a MOS semiconductor device
US5592005A (en) 1995-03-31 1997-01-07 Siliconix Incorporated Punch-through field effect transistor
US5595927A (en) 1995-03-17 1997-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for making self-aligned source/drain mask ROM memory cell using trench etched channel
US5597765A (en) 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
US5623152A (en) 1995-02-09 1997-04-22 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
US5629543A (en) 1995-08-21 1997-05-13 Siliconix Incorporated Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
US5637898A (en) 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
US5640034A (en) 1992-05-18 1997-06-17 Texas Instruments Incorporated Top-drain trench based resurf DMOS transistor structure
US5648670A (en) 1995-06-07 1997-07-15 Sgs-Thomson Microelectronics, Inc. Trench MOS-gated device with a minimum number of masks
US5656843A (en) 1992-08-05 1997-08-12 U.S. Philips Corporation Semiconductor device having a vertical insulated gate field effect device and a breakdown region remote from the gate
US5670803A (en) 1995-02-08 1997-09-23 International Business Machines Corporation Three-dimensional SRAM trench structure and fabrication method therefor
US5689128A (en) 1995-08-21 1997-11-18 Siliconix Incorporated High density trenched DMOS transistor
US5693569A (en) 1995-01-26 1997-12-02 Fuji Electric Co., Ltd. Method of forming silicon carbide trench mosfet with a schottky electrode
US5705409A (en) 1995-09-28 1998-01-06 Motorola Inc. Method for forming trench transistor structure
US5710072A (en) 1994-05-17 1998-01-20 Siemens Aktiengesellschaft Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
US5714781A (en) 1995-04-27 1998-02-03 Nippondenso Co., Ltd. Semiconductor device having a gate electrode in a grove and a diffused region under the grove
US5719409A (en) 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
US5770878A (en) 1996-04-10 1998-06-23 Harris Corporation Trench MOS gate device
US5776813A (en) 1997-10-06 1998-07-07 Industrial Technology Research Institute Process to manufacture a vertical gate-enhanced bipolar transistor
US5780343A (en) 1995-12-20 1998-07-14 National Semiconductor Corporation Method of producing high quality silicon surface for selective epitaxial growth of silicon
US5801417A (en) 1988-05-17 1998-09-01 Advanced Power Technology, Inc. Self-aligned power MOSFET device with recessed gate and source
US5877528A (en) 1997-03-03 1999-03-02 Megamos Corporation Structure to provide effective channel-stop in termination areas for trenched power transistors
US5879971A (en) 1995-09-28 1999-03-09 Motorola Inc. Trench random access memory cell and method of formation

Family Cites Families (57)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US41400A (en) * 1864-01-26 Improvement in the manufacture of soap
US28083A (en) * 1860-05-01 Cementing millstones
US23961A (en) * 1859-05-10 Improvement in harvesting-machines
US14658A (en) * 1856-04-15 Machine foe
DE1589705A1 (en) * 1967-11-15 1970-04-30 Siemens Ag A plurality of electrical functional stages integrated circuit containing
US5607511A (en) * 1992-02-21 1997-03-04 International Business Machines Corporation Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers
US5583368A (en) * 1994-08-11 1996-12-10 International Business Machines Corporation Stacked devices
US5674766A (en) * 1994-12-30 1997-10-07 Siliconix Incorporated Method of making a trench MOSFET with multi-resistivity drain to provide low on-resistance by varying dopant concentration in epitaxial layer
JP3291957B2 (en) * 1995-02-17 2002-06-17 富士電機株式会社 Vertical trench misfet and a method of manufacturing the same
US6049108A (en) * 1995-06-02 2000-04-11 Siliconix Incorporated Trench-gated MOSFET with bidirectional voltage clamping
US6037632A (en) * 1995-11-06 2000-03-14 Kabushiki Kaisha Toshiba Semiconductor device
JP4047384B2 (en) * 1996-02-05 2008-02-13 シーメンス アクチエンゲゼルシヤフト Controllable semiconductor device field effect
US5895951A (en) * 1996-04-05 1999-04-20 Megamos Corporation MOSFET structure and fabrication process implemented by forming deep and narrow doping regions through doping trenches
JP2891205B2 (en) * 1996-10-21 1999-05-17 日本電気株式会社 A method of manufacturing a semiconductor integrated circuit
US6168983B1 (en) * 1996-11-05 2001-01-02 Power Integrations, Inc. Method of making a high-voltage transistor with multiple lateral conduction layers
US6207994B1 (en) * 1996-11-05 2001-03-27 Power Integrations, Inc. High-voltage transistor with multi-layer conduction region
US6011298A (en) * 1996-12-31 2000-01-04 Stmicroelectronics, Inc. High voltage termination with buried field-shaping region
JP3938964B2 (en) * 1997-02-10 2007-06-27 三菱電機株式会社 High voltage semiconductor device and a manufacturing method thereof
US6057558A (en) * 1997-03-05 2000-05-02 Denson Corporation Silicon carbide semiconductor device and manufacturing method thereof
KR100225409B1 (en) * 1997-03-27 1999-10-15 김덕중 Trench dmos and method of manufacturing the same
US5879994A (en) * 1997-04-15 1999-03-09 National Semiconductor Corporation Self-aligned method of fabricating terrace gate DMOS transistor
US6037628A (en) * 1997-06-30 2000-03-14 Intersil Corporation Semiconductor structures with trench contacts
JP3502531B2 (en) * 1997-08-28 2004-03-02 株式会社ルネサステクノロジ A method of manufacturing a semiconductor device
DE19740195C2 (en) * 1997-09-12 1999-12-02 Siemens Ag A semiconductor device with a metal-semiconductor junction with low reverse current
DE19743342C2 (en) * 1997-09-30 2002-02-28 Infineon Technologies Ag Field effect transistor high packing density and process for its preparation
US6337499B1 (en) * 1997-11-03 2002-01-08 Infineon Technologies Ag Semiconductor component
GB9723468D0 (en) * 1997-11-07 1998-01-07 Zetex Plc Method of semiconductor device fabrication
US6081009A (en) * 1997-11-10 2000-06-27 Intersil Corporation High voltage mosfet structure
JPH11204782A (en) * 1998-01-08 1999-07-30 Toshiba Corp Semiconductor device and manufacture therefor
WO1999038214A1 (en) * 1998-01-22 1999-07-29 Mitsubishi Denki Kabushiki Kaisha Insulating gate type bipolar semiconductor device
US5900663A (en) * 1998-02-07 1999-05-04 Xemod, Inc. Quasi-mesh gate structure for lateral RF MOS devices
US5949104A (en) * 1998-02-07 1999-09-07 Xemod, Inc. Source connection structure for lateral RF MOS devices
JP2002503401A (en) * 1998-04-08 2002-01-29 シーメンス アクチエンゲゼルシヤフト The high-voltage corner seal body for the planar structure
US5945724A (en) * 1998-04-09 1999-08-31 Micron Technology, Inc. Trench isolation region for semiconductor device
US6063678A (en) * 1998-05-04 2000-05-16 Xemod, Inc. Fabrication of lateral RF MOS devices with enhanced RF properties
US6048772A (en) * 1998-05-04 2000-04-11 Xemod, Inc. Method for fabricating a lateral RF MOS device with an non-diffusion source-backside connection
DE19820223C1 (en) * 1998-05-06 1999-11-04 Siemens Ag Variable doping epitaxial layer manufacturing method
US6015727A (en) * 1998-06-08 2000-01-18 Wanlass; Frank M. Damascene formation of borderless contact MOS transistors
US6064088A (en) * 1998-06-15 2000-05-16 Xemod, Inc. RF power MOSFET device with extended linear region of transconductance characteristic at low drain current
DE19841754A1 (en) * 1998-09-11 2000-03-30 Siemens Ag Switching transistor with reduced switching losses
DE19848828C2 (en) * 1998-10-22 2001-09-13 Infineon Technologies Ag A semiconductor device with a small ON-state voltage blocking capability and high
US5998833A (en) * 1998-10-26 1999-12-07 North Carolina State University Power semiconductor devices having improved high frequency switching and breakdown characteristics
EP1125236B1 (en) * 1998-10-30 2005-06-01 Walter Reed Army Institute of Research Method and apparatus for predicting human cognitive performance
DE19854915C2 (en) * 1998-11-27 2002-09-05 Infineon Technologies Ag MOS field effect transistor with auxiliary electrode
US6204097B1 (en) * 1999-03-01 2001-03-20 Semiconductor Components Industries, Llc Semiconductor device and method of manufacture
US6188105B1 (en) * 1999-04-01 2001-02-13 Intersil Corporation High density MOS-gated power device and process for forming same
US6198127B1 (en) * 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
US6191447B1 (en) * 1999-05-28 2001-02-20 Micro-Ohm Corporation Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same
DE69938541D1 (en) * 1999-06-03 2008-05-29 St Microelectronics Srl Power semiconductor device having an edge termination structure to a voltage divider
JP3851744B2 (en) * 1999-06-28 2006-11-29 株式会社東芝 A method of manufacturing a semiconductor device
GB9917099D0 (en) * 1999-07-22 1999-09-22 Koninkl Philips Electronics Nv Cellular trench-gate field-effect transistors
US6228727B1 (en) * 1999-09-27 2001-05-08 Chartered Semiconductor Manufacturing, Ltd. Method to form shallow trench isolations with rounded corners and reduced trench oxide recess
GB9922764D0 (en) * 1999-09-28 1999-11-24 Koninkl Philips Electronics Nv Manufacture of trench-gate semiconductor devices
US6222233B1 (en) * 1999-10-04 2001-04-24 Xemod, Inc. Lateral RF MOS device with improved drain structure
US6346469B1 (en) * 2000-01-03 2002-02-12 Motorola, Inc. Semiconductor device and a process for forming the semiconductor device
US6376878B1 (en) * 2000-02-11 2002-04-23 Fairchild Semiconductor Corporation MOS-gated devices with alternating zones of conductivity
US6362112B1 (en) * 2000-11-08 2002-03-26 Fabtech, Inc. Single step etched moat

Patent Citations (99)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3404295A (en) 1964-11-30 1968-10-01 Motorola Inc High frequency and voltage transistor with added region for punch-through protection
US3412297A (en) 1965-12-16 1968-11-19 United Aircraft Corp Mos field-effect transistor with a onemicron vertical channel
US3497777A (en) 1967-06-13 1970-02-24 Stanislas Teszner Multichannel field-effect semi-conductor device
US3564356A (en) 1968-10-24 1971-02-16 Tektronix Inc High voltage integrated circuit transistor
US4003072A (en) 1972-04-20 1977-01-11 Sony Corporation Semiconductor device with high voltage breakdown resistance
US4337474A (en) 1978-08-31 1982-06-29 Mitsubishi Denki Kabushiki Kaisha Semiconductor device
US4698653A (en) 1979-10-09 1987-10-06 Cardwell Jr Walter T Semiconductor devices controlled by depletion regions
US4638344A (en) 1979-10-09 1987-01-20 Cardwell Jr Walter T Junction field-effect transistor controlled by merged depletion regions
US4868624A (en) 1980-05-09 1989-09-19 Regents Of The University Of Minnesota Channel collector transistor
US4300150A (en) 1980-06-16 1981-11-10 North American Philips Corporation Lateral double-diffused MOS transistor device
US4326332A (en) 1980-07-28 1982-04-27 International Business Machines Corp. Method of making a high density V-MOS memory array
US4754310A (en) 1980-12-10 1988-06-28 U.S. Philips Corp. High voltage semiconductor device
US4974059A (en) 1982-12-21 1990-11-27 International Rectifier Corporation Semiconductor high-power mosfet device
US4579621A (en) 1983-07-08 1986-04-01 Mitsubishi Denki Kabushiki Kaisha Selective epitaxial growth method
US4639761A (en) 1983-12-16 1987-01-27 North American Philips Corporation Combined bipolar-field effect transistor resurf devices
US4774556A (en) 1985-07-25 1988-09-27 Nippondenso Co., Ltd. Non-volatile semiconductor memory device
US5262336A (en) 1986-03-21 1993-11-16 Advanced Power Technology, Inc. IGBT process to produce platinum lifetime control
US4716126A (en) 1986-06-05 1987-12-29 Siliconix Incorporated Fabrication of double diffused metal oxide semiconductor transistor
US4746630A (en) 1986-09-17 1988-05-24 Hewlett-Packard Company Method for producing recessed field oxide with improved sidewall characteristics
US4941026A (en) 1986-12-05 1990-07-10 General Electric Company Semiconductor devices exhibiting minimum on-resistance
US5027180A (en) 1986-12-11 1991-06-25 Mitsubishi Electric Corporation Double gate static induction thyristor
US5105243A (en) 1987-02-26 1992-04-14 Kabushiki Kaisha Toshiba Conductivity-modulation metal oxide field effect transistor with single gate structure
US4821095A (en) 1987-03-12 1989-04-11 General Electric Company Insulated gate semiconductor device with extra short grid and method of fabrication
US4823176A (en) 1987-04-03 1989-04-18 General Electric Company Vertical double diffused metal oxide semiconductor (VDMOS) device including high voltage junction exhibiting increased safe operating area
US4801986A (en) 1987-04-03 1989-01-31 General Electric Company Vertical double diffused metal oxide semiconductor VDMOS device with increased safe operating area and method
US5164325A (en) 1987-10-08 1992-11-17 Siliconix Incorporated Method of making a vertical current flow field effect transistor
US5576245A (en) 1987-10-08 1996-11-19 Siliconix Incorporated Method of making vertical current flow field effect transistor
US4893160A (en) 1987-11-13 1990-01-09 Siliconix Incorporated Method for increasing the performance of trenched devices and the resulting structure
US4914058A (en) 1987-12-29 1990-04-03 Siliconix Incorporated Grooved DMOS process with varying gate dielectric thickness
US4967245A (en) 1988-03-14 1990-10-30 Siliconix Incorporated Trench power MOSFET device
US5801417A (en) 1988-05-17 1998-09-01 Advanced Power Technology, Inc. Self-aligned power MOSFET device with recessed gate and source
US5142640A (en) 1988-06-02 1992-08-25 Seiko Epson Corporation Trench gate metal oxide semiconductor field effect transistor
US4990463A (en) 1988-07-05 1991-02-05 Kabushiki Kaisha Toshiba Method of manufacturing capacitor
US4853345A (en) 1988-08-22 1989-08-01 Delco Electronics Corporation Process for manufacture of a vertical DMOS transistor
US5268311A (en) 1988-09-01 1993-12-07 International Business Machines Corporation Method for forming a thin dielectric layer on a substrate
US5072266A (en) 1988-12-27 1991-12-10 Siliconix Incorporated Trench DMOS power transistor with field-shaping body profile and three-dimensional geometry
US4992390A (en) 1989-07-06 1991-02-12 General Electric Company Trench gate structure with thick bottom oxide
US5519245A (en) 1989-08-31 1996-05-21 Nippondenso Co., Ltd. Insulated gate bipolar transistor with reverse conducting current
US5436189A (en) 1989-10-03 1995-07-25 Harris Corporation Self-aligned channel stop for trench-isolated island
US5071782A (en) 1990-06-28 1991-12-10 Texas Instruments Incorporated Vertical memory cell array and method of fabrication
US5079608A (en) 1990-11-06 1992-01-07 Harris Corporation Power MOSFET transistor circuit with active clamp
US5216275A (en) 1991-03-19 1993-06-01 University Of Electronic Science And Technology Of China Semiconductor power devices with alternating conductivity type high-voltage breakdown regions
US5164802A (en) 1991-03-20 1992-11-17 Harris Corporation Power vdmosfet with schottky on lightly doped drain of lateral driver fet
US5219793A (en) 1991-06-03 1993-06-15 Motorola Inc. Method for forming pitch independent contacts and a semiconductor device having the same
US5219777A (en) 1991-06-14 1993-06-15 Gold Star Electron Co., Ltd. Metal oxide semiconductor field effect transistor and method of making the same
US5298761A (en) 1991-06-17 1994-03-29 Nikon Corporation Method and apparatus for exposure process
US5430311A (en) 1991-09-20 1995-07-04 Hitachi, Ltd. Constant-voltage diode for over-voltage protection
US5350937A (en) 1991-10-08 1994-09-27 Semiconductor Energy Laboratory Co., Ltd. Non-volatile memory device having a floating gate
US5366914A (en) 1992-01-29 1994-11-22 Nec Corporation Vertical power MOSFET structure having reduced cell area
US5567635A (en) 1992-03-23 1996-10-22 International Business Machines Corporation Method of making a three dimensional trench EEPROM cell structure
US5554862A (en) 1992-03-31 1996-09-10 Kabushiki Kaisha Toshiba Power semiconductor device
US5389815A (en) 1992-04-28 1995-02-14 Mitsubishi Denki Kabushiki Kaisha Semiconductor diode with reduced recovery current
US5640034A (en) 1992-05-18 1997-06-17 Texas Instruments Incorporated Top-drain trench based resurf DMOS transistor structure
US5233215A (en) 1992-06-08 1993-08-03 North Carolina State University At Raleigh Silicon carbide power MOSFET with floating field ring and floating field plate
US5605852A (en) 1992-07-23 1997-02-25 Siliconix Incorporated Method for fabricating high voltage transistor having trenched termination
US5430324A (en) 1992-07-23 1995-07-04 Siliconix, Incorporated High voltage transistor having edge termination utilizing trench technology
US5294824A (en) 1992-07-31 1994-03-15 Motorola, Inc. High voltage transistor having reduced on-resistance
US5656843A (en) 1992-08-05 1997-08-12 U.S. Philips Corporation Semiconductor device having a vertical insulated gate field effect device and a breakdown region remote from the gate
US5300447A (en) 1992-09-29 1994-04-05 Texas Instruments Incorporated Method of manufacturing a minimum scaled transistor
US5572048A (en) 1992-11-20 1996-11-05 Hitachi, Ltd. Voltage-driven type semiconductor device
US5275965A (en) 1992-11-25 1994-01-04 Micron Semiconductor, Inc. Trench isolation using gated sidewalls
US5326711A (en) 1993-01-04 1994-07-05 Texas Instruments Incorporated High performance high voltage vertical transistor and method of fabrication
US5418376A (en) 1993-03-02 1995-05-23 Toyo Denki Seizo Kabushiki Kaisha Static induction semiconductor device with a distributed main electrode structure and static induction semiconductor device with a static induction main electrode shorted structure
US5474943A (en) 1993-03-15 1995-12-12 Siliconix Incorporated Method for fabricating a short channel trenched DMOS transistor
US5438215A (en) 1993-03-25 1995-08-01 Siemens Aktiengesellschaft Power MOSFET
US5365102A (en) 1993-07-06 1994-11-15 North Carolina State University Schottky barrier rectifier with MOS trench
US5473180A (en) 1993-07-12 1995-12-05 U.S. Philips Corporation Semiconductor device with an MOST provided with an extended drain region for high voltages
US5473176A (en) 1993-09-01 1995-12-05 Kabushiki Kaisha Toshiba Vertical insulated gate transistor and method of manufacture
US5541425A (en) 1994-01-20 1996-07-30 Mitsubishi Denki Kabushiki Kaisha Semiconductor device having trench structure
US5429977A (en) 1994-03-11 1995-07-04 Industrial Technology Research Institute Method for forming a vertical transistor with a stacked capacitor DRAM cell
US5434435A (en) 1994-05-04 1995-07-18 North Carolina State University Trench gate lateral MOSFET
US5710072A (en) 1994-05-17 1998-01-20 Siemens Aktiengesellschaft Method of producing and arrangement containing self-amplifying dynamic MOS transistor memory cells
US5405794A (en) 1994-06-14 1995-04-11 Philips Electronics North America Corporation Method of producing VDMOS device of increased power density
US5442214A (en) 1994-08-09 1995-08-15 United Microelectronics Corp. VDMOS transistor and manufacturing method therefor
US5424231A (en) 1994-08-09 1995-06-13 United Microelectronics Corp. Method for manufacturing a VDMOS transistor
US5639676A (en) 1994-08-15 1997-06-17 Siliconix Incorporated Trenched DMOS transistor fabrication having thick termination region oxide
US5578851A (en) 1994-08-15 1996-11-26 Siliconix Incorporated Trenched DMOS transistor having thick field oxide in termination region
US5581100A (en) 1994-08-30 1996-12-03 International Rectifier Corporation Trench depletion MOSFET
US5583065A (en) 1994-11-23 1996-12-10 Sony Corporation Method of making a MOS semiconductor device
US5597765A (en) 1995-01-10 1997-01-28 Siliconix Incorporated Method for making termination structure for power MOSFET
US5693569A (en) 1995-01-26 1997-12-02 Fuji Electric Co., Ltd. Method of forming silicon carbide trench mosfet with a schottky electrode
US5670803A (en) 1995-02-08 1997-09-23 International Business Machines Corporation Three-dimensional SRAM trench structure and fabrication method therefor
US5623152A (en) 1995-02-09 1997-04-22 Mitsubishi Denki Kabushiki Kaisha Insulated gate semiconductor device
US5595927A (en) 1995-03-17 1997-01-21 Taiwan Semiconductor Manufacturing Company Ltd. Method for making self-aligned source/drain mask ROM memory cell using trench etched channel
US5592005A (en) 1995-03-31 1997-01-07 Siliconix Incorporated Punch-through field effect transistor
US5714781A (en) 1995-04-27 1998-02-03 Nippondenso Co., Ltd. Semiconductor device having a gate electrode in a grove and a diffused region under the grove
US5567634A (en) 1995-05-01 1996-10-22 National Semiconductor Corporation Method of fabricating self-aligned contact trench DMOS transistors
US5665619A (en) 1995-05-01 1997-09-09 National Semiconductor Corporation Method of fabricating a self-aligned contact trench DMOS transistor structure
US5648670A (en) 1995-06-07 1997-07-15 Sgs-Thomson Microelectronics, Inc. Trench MOS-gated device with a minimum number of masks
US5689128A (en) 1995-08-21 1997-11-18 Siliconix Incorporated High density trenched DMOS transistor
US5629543A (en) 1995-08-21 1997-05-13 Siliconix Incorporated Trenched DMOS transistor with buried layer for reduced on-resistance and ruggedness
US5705409A (en) 1995-09-28 1998-01-06 Motorola Inc. Method for forming trench transistor structure
US5879971A (en) 1995-09-28 1999-03-09 Motorola Inc. Trench random access memory cell and method of formation
US5780343A (en) 1995-12-20 1998-07-14 National Semiconductor Corporation Method of producing high quality silicon surface for selective epitaxial growth of silicon
US5637898A (en) 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
US5770878A (en) 1996-04-10 1998-06-23 Harris Corporation Trench MOS gate device
US5719409A (en) 1996-06-06 1998-02-17 Cree Research, Inc. Silicon carbide metal-insulator semiconductor field effect transistor
US5877528A (en) 1997-03-03 1999-03-02 Megamos Corporation Structure to provide effective channel-stop in termination areas for trenched power transistors
US5776813A (en) 1997-10-06 1998-07-07 Industrial Technology Research Institute Process to manufacture a vertical gate-enhanced bipolar transistor

Non-Patent Citations (31)

* Cited by examiner, † Cited by third party
Title
"CoolMOS(TM) the second generation," Infineon Technologies product information (2000).
"IR develops CoolMOS(TM)-equivalent technology, positions it at the top of a 3-tiered line of new products for SMPS," International Rectifiers company information available at http://www.irf.com (1999).
Baliga "New Concepts in Power Rectifiers," Physics of Semiconductor Devices, Proceedings of the Third Int'l Workshop, Madras (India), Committee on Science and Technology in Developing Countries(1985).
Baliga "Options for CVD of Dielectrics Include Low-k Materials," Technical Literature from Semiconductor International Jun. 1998.
Brown et al. Novel Trench Gate Structure Developments Set the Benchmark for Next Generation Power MOSFET Switching Performance. Power Electronics-May 2003 Proceedings (PCIM), Nurenburg, vol. 47, pp. 275-278.
Bulucea "Trench DMOS Transistor Technology For High Current (100 A Range) Switching" Solid-State Electronics vol. 34 No. pp. 493-507 (1991).
Chang et al. "Numerical and experimental Analysis of 500-V Power DMOSFET with an Atomic-Lattice Layout," IEEE Transactions on Electron Devices 36:2623 (1989).
Chang et al. "Self-Aligned UMOSFET's with a Specific On-Resistance of 1mQ cm<SUP>2</SUP>," IEEE Transactions on Electron Devices 34:2329-2333 (1987).
Curtis, et al. "APCVD TEOS: 03 Advanced Trench Isolation Applications," Semiconductor Fabtech 9th Edition (1999).
Darwish et al. A New Power W-Gated Trench MOSFET (WMOSFET) with High Switching Performance. ISPSD Proceedings-Apr. 2003, Cambridge.
Fujihira "Theory of Semiconductor Superjunction Devices" Jpn. J. Appl. Phys. vol. 36 pp. 6254-6252 (1997).
Gan et al. "Poly Flanked VDMOS (PFVDMOS): A Superior Technology for Superjunction Devices," IEEE Power Electronics Specialists Conference, Jun. 17-22, 2001, Vancouver, Canada (2001).
Glenn et al. "A Novel Vertical Deep Trench RESURF DMOS (VTR-DMOS)" IEEE ISPD 2000, May 22-25, Toulouse France.
Kao et al. "Two Dimensional Thermal Oxidation of Silicon-I. Experiments,", IEEE Transactions on Electron Devices, vol. ED-34,No. 5, May 1987.
Kao et al. "Two Dimensional Thermal Oxidation of Silicon-II. Modeling Stress Effects in Wet Oxides,", IEEE Transactions on Electron Devices, vol. ED-35, No. 1, Jan. 1988.
Lorenz et al. "COOL MOS-An important milestone towards a new power MOSFET generation" Power Conversion pp. 151-160 (1988).
Moghadam "Delivering Value Around New Industry Paradigms," Technical Literature from Applied Materials, pp. 1-11, vol. 1, Issue 2, Nov. 1999.
Park et al., "Lateral Trench Gate Super-Junction SOI-LDMOSFETs with Low On-Resistance", Institute for Microelectronics, University of Technology Vienna, Austria (date unknown).
Shenoy et al."Analysis of the Effect of Charge Imbalance on the Static and Dynamic Charateristics of the Super Junction MOSFET," IEEE International Symposium on Power Semiconductor Devices 1999, pp. 99-102 (1999).
Singer "Empty Spaces in Silicon (ESS): An Alternative to SOI," Semiconductor International p. 42, Dec. 1999.
Technical Literature from Quester Technology, Model APT-4300 300mm Atmospheric TEOS/Ozone CVD System (unknown date).
Technical Literature from Quester Technology, Model APT-6000 Atmospheric TEOS-Ozone CVD System (unknown date).
Technical Literature from Silicon Valley Group Thermal Systems, APNext, High Throughput APCVD Cluster Tool for 200 mm/300 mm Wafer Processing (unknown date).
U.S. Appl. No. 08/742,754, filed Oct. 1, 1996.
U.S. Appl. No. 09/405,210, filed Sep. 24, 1999.
U.S. Appl. No. 09/428,616, filed Oct. 27, 1999.
U.S. Appl. No. 09/780,040, filed Feb. 9, 2001.
U.S. Appl. No. 10/120,207, filed Apr. 15, 2002.
Ueda et al. "An Ultra-Low On-Resistance Power MOSFET Fabricated by Using a Fully Self-Aligned Process," IEEE Transactions on Electron Devices 34:926-930 (1987).
Wilamowski "Schottky Diodes with High Breakdown Voltages," Solid-State Electronics 26:491-493 (1983).
Wolf "Silicon Processing for The VLSI Era" vol. 2 Process Integration Lattice Press (1990).

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