US7019796B2 - Thin film transistor electrostatic discharge protective circuit - Google Patents

Thin film transistor electrostatic discharge protective circuit Download PDF

Info

Publication number
US7019796B2
US7019796B2 US10/878,005 US87800504A US7019796B2 US 7019796 B2 US7019796 B2 US 7019796B2 US 87800504 A US87800504 A US 87800504A US 7019796 B2 US7019796 B2 US 7019796B2
Authority
US
United States
Prior art keywords
tft
signal line
esd protective
protective circuit
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime, expires
Application number
US10/878,005
Other versions
US20050285984A1 (en
Inventor
Ja-Fu Tsai
Wen-Chun Wang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Wintek Corp
Original Assignee
Wintek Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Wintek Corp filed Critical Wintek Corp
Priority to US10/878,005 priority Critical patent/US7019796B2/en
Assigned to WINTEK CORPORATION reassignment WINTEK CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TSAI, JA-FU, WANG, WEN-CHUN
Publication of US20050285984A1 publication Critical patent/US20050285984A1/en
Application granted granted Critical
Publication of US7019796B2 publication Critical patent/US7019796B2/en
Adjusted expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136204—Arrangements to prevent high voltage or static electricity failures

Definitions

  • the present invention is related to a protective circuit for avoiding electrostatic discharge (ESD) damage.
  • the ESD protective circuit is built in a driving matrix thin film transistor (TFT) liquid crystal display.
  • FIG. 2 shows a conventional driving matrix liquid crystal display 10 utilizing thin film transistor switch cells (TFTs).
  • the liquid crystal display 10 includes multiple TFTs 2 arranged into a matrix and pixel capacitors 1 connected with the drains of the TFTs 2 .
  • the pixel capacitor 1 includes a liquid crystal capacitor 1 a formed of a liquid crystal layer between pixel electrode and Vcom and a storage capacitor 1 b parallel to the liquid crystal capacitor 1 a .
  • the other ends of the liquid crystal capacitor 1 a and the storage capacitor 1 b are electrically connected to an equal potential contact 4 disposed on a corresponding substrate.
  • a scanning signal line 3 is electrically connected to the gate of the TFTs 2 .
  • the data signal line 5 is electrically connected to the source of the TFTs 2 .
  • the scan signal provided via the scanning signal line 3 makes the TFTs 2 in an on/off state.
  • image signal voltage via the data signal line 5 is provided for the source of the TFTs 2 to charge the pixel capacitor to a voltage level corresponding to the source.
  • the scan line and data line pads adapted to the driving chip are denoted by 8 and 9 .
  • the TFT ESD protective circuit 7 is disposed between the scanning signal line 3 and the Vcom 6 (common electrode) and between the data signal line 5 and the Vcom 6 .
  • the TFT ESD protective circuit 7 serves to eliminate the electrostatic voltage to protect the TFTs 2 from being damaged by electrostatic voltage.
  • the electrostatic voltage is generated easily when assembling the driving matrix substrate (on which switch cells are disposed), especially when arranging the ICs for driving the LCD on the driving matrix substrate.
  • FIG. 3 shows a conventional TFT ESD protective circuit 11 .
  • the TFT ESD protective circuit 11 includes two TFT diodes t 1 , t 2 reversely connected.
  • the pattern of the TFT ESD protective circuit symbol is as shown in FIG. 4 .
  • the gate electrode G and drain electrode D of the TFT t 1 are short-circuited and connected to the scanning signal line 3 and the data signal line 5 .
  • the source electrode S of the TFT t 1 is connected to the Vcom 6 .
  • the source electrode S of the TFT t 2 is connected to the scanning signal line 3 and data signal line 5 .
  • the gate electrode G and drain electrode D of the TFT t 2 are short-circuited and connected to the Vcom 6 .
  • the TFT t 1 of the TFT ESD protective circuit 11 is an element for discharging positive electrostatic voltage
  • the TFT t 2 of the TFT ESD protective circuit 11 is an element for discharging negative electrostatic voltage.
  • positive electrostatic voltage is generated
  • the electrostatic voltage level rises higher than the threshold voltage of TFT.
  • the transistor t 1 is turned on and the positive electrostatic voltage via the scanning signal line 3 and data signal line 5 is discharged by the transistor t 1 .
  • the transistor t 2 discharges the negative electrostatic voltage to achieve ESD protection effect.
  • the TFT ESD protective circuit 11 When the above TFT ESD protective circuit 11 protects the internal TFT array, the TFT ESD protective circuit 11 itself is in the danger of being damaged by the electrostatic voltage.
  • the insulating layer of the gate electrode will be broken down by the electrostatic voltage to cause very great leaking current.
  • the knot of gate electrode at the TFT t 1 and the source electrode will be short-circuited. This leads to short-circuit of the scanning signal line 3 , data signal line 5 and Vcom 6 .
  • This will form a defect on the display panel. The defect will result in that the picture cannot be normally shown in the cell test and module driving of the manufacturing procedure. This problem will affect the yield of products. Therefore, it is tried by the applicant to solve the above problem.
  • the positive ESD protective unit and negative ESD protective unit are independently arranged for respectively discharging positive and negative electrostatic voltages.
  • Each of the positive ESD protective unit and negative ESD protective unit is composed of three TFT for providing multifold ESD protective effect. In the case that the gate electrode insulating layer of any of the three TFT is broken down by electrostatic voltage, the remaining two TFT can still normally operate and keep truly providing ESD protective function. Therefore, the picture still can be normally shown on the display panel and the electrostatic durability of the display is enhanced.
  • FIG. 1 is a circuit diagram of the ESD protective circuit of the present invention
  • FIG. 2 shows a conventional driving matrix liquid crystal display utilizing TFTs
  • FIG. 3 is a circuit diagram of a conventional ESD protective circuit
  • FIG. 4 is a symbol of circuit diagram corresponding to the conventional ESD protective circuit.
  • the TFT ESD protective circuit of the present invention is disposed between a scanning signal line 3 , a data signal line 5 and a Vcom 6 .
  • the scanning signal line 3 and data signal line 5 are respectively connected to a scanning line pad 8 and a data line pad 9 of a driving chip.
  • the TFT ESD protective circuit includes a positive ESD protective unit 13 composed of a first TFT T 1 , a second TFT T 2 and a third TFT T 3 .
  • the gate electrode G and drain electrode D of the first and second TFT T 1 , T 2 are short-circuited and electrically connected with the scanning signal line 3 and data signal line 5 .
  • the source electrode S of the first TFT T 1 is connected with the gate electrode G of the third TFT T 3 .
  • the source electrode S of the second TFT T 2 is connected with the drain electrode D of the third TFT T 3 .
  • the source electrode S of the third TFT T 3 is connected with the Vcom 6 .
  • the TFT ESD protective circuit further includes a negative ESD protective unit 14 composed of a fourth TFT T 4 , a fifth TFT T 5 and a sixth TFT T 6 .
  • the gate electrode G and drain electrode D of the fourth and fifth TFT T 4 , T 5 are short-circuited and connected with the Vcom 6 .
  • the source electrode S of the fifth TFT T 5 is connected with the gate electrode G of the sixth TFT T 6 .
  • the source electrode S of the fourth TFT T 4 is connected with the drain electrode D of the sixth TFT T 6 .
  • the source electrode S of the sixth TFT T 6 is electrically connected with the scanning signal line 3 and data signal line 5 .
  • the TFT ESD protective circuit of the present invention operates in such a manner that when positive electrostatic voltage is generated on the scanning signal line 3 and data signal line 5 , the scanning signal line 3 and data signal line 5 are at high potential state. At this time, the positive electrostatic voltage via the scanning signal line 3 and data signal line 5 will go into the positive ESD protective unit 13 .
  • the electrostatic voltage rises higher than the TFT threshold voltage so that the electrostatic voltage is sufficient to turn on the first and second TFT T 1 , T 2 .
  • the drain electrostatic voltage and source electrode voltage of the first TFT T 1 is nearly equal to each other.
  • the source electrode of the first TFT T 1 and the gate electrode knot of the third TFT T 3 have equal voltage potential.
  • the voltage level is higher than the TFT threshold voltage. Therefore, the third TFT T 3 is turned on. At this time, the first, second and third TFT T 1 , T 2 , T 3 are all at on state. The positive electrostatic voltage via the second and third TFT T 2 , T 3 is discharged. During the discharging procedure of the positive electrostatic voltage, the fourth, fifth and sixth TFT T 4 , T 5 , T 6 are all turned off.
  • the conventional TFT ESD protective circuit 11 in the case that the insulating layer of the gate electrode at TFT t 1 is broken down, the scanning signal line 3 and data signal line 5 will be short-circuited with Vcom. This will lead to abnormal display of the display panel.
  • the TFT ESD protective circuit of the present invention in the case that the gate insulating layer of any of the first, second and third TFT T 1 , T 2 , T 3 of the positive ESD protective unit 13 is broken down by the electrostatic voltage when the positive ESD protective unit 13 discharges the positive electrostatic voltage, for example, in the case that the gate insulating layer the first TFT T 1 is broken down, the positive electrostatic voltage can be still discharged via the second and third TFT T 2 , T 3 . Similarly, in the case that the second TFT T 2 is broken down, the positive electrostatic voltage can be still discharged via the third TFT T 3 .
  • the TFT ESD protective circuit of the present invention can truly provide ESD protective effect and the picture still can be normally shown in the cell test and the module driving of the manufacturing procedure.
  • the fourth, fifth and sixth TFT T 4 , T 5 , T 6 of the negative ESD protective unit 14 are all turned on for eliminating the negative electrostatic voltage.
  • the first, second and third TFT T 1 , T 2 , T 3 are all turned off.
  • the negative ESD protective unit 14 has the same function as the positive ESD protective unit 13 . In the case that any of the three TFT is broken down, the remaining two TFT can still normally operate to discharge the negative electrostatic voltage to avoid defect of the display panel and truly provide ESD protective effect.
  • the ESD protective circuit of the present invention provides multifold ESD protective effect for the liquid crystal display and enhances the durability thereof.

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • General Physics & Mathematics (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A TFT ESD protective circuit disposed between a scanning signal line or a data signal line and a Vcom. The protective circuit includes a positive ESD protective unit and a negative ESD protective unit. Each of the positive static protective unit and negative static protective unit is composed of three TFT. In the case that the gate insulating layer of any of the three TFT is broken down by electrostatic voltage, the remaining two TFT can still normally operate and keep truly providing static protective function.

Description

BACKGROUND OF THE INVENTION
The present invention is related to a protective circuit for avoiding electrostatic discharge (ESD) damage. The ESD protective circuit is built in a driving matrix thin film transistor (TFT) liquid crystal display.
FIG. 2 shows a conventional driving matrix liquid crystal display 10 utilizing thin film transistor switch cells (TFTs). The liquid crystal display 10 includes multiple TFTs 2 arranged into a matrix and pixel capacitors 1 connected with the drains of the TFTs 2. The pixel capacitor 1 includes a liquid crystal capacitor 1 a formed of a liquid crystal layer between pixel electrode and Vcom and a storage capacitor 1 b parallel to the liquid crystal capacitor 1 a. The other ends of the liquid crystal capacitor 1 a and the storage capacitor 1 b are electrically connected to an equal potential contact 4 disposed on a corresponding substrate. A scanning signal line 3 is electrically connected to the gate of the TFTs 2. The data signal line 5 is electrically connected to the source of the TFTs 2. The scan signal provided via the scanning signal line 3 makes the TFTs 2 in an on/off state. When the TFTs 2 is turned on, image signal voltage via the data signal line 5 is provided for the source of the TFTs 2 to charge the pixel capacitor to a voltage level corresponding to the source. The scan line and data line pads adapted to the driving chip are denoted by 8 and 9.
The TFT ESD protective circuit 7 is disposed between the scanning signal line 3 and the Vcom 6 (common electrode) and between the data signal line 5 and the Vcom 6. When electrostatic voltage is generated, the TFT ESD protective circuit 7 serves to eliminate the electrostatic voltage to protect the TFTs 2 from being damaged by electrostatic voltage. In manufacturing procedure of the liquid crystal display, the electrostatic voltage is generated easily when assembling the driving matrix substrate (on which switch cells are disposed), especially when arranging the ICs for driving the LCD on the driving matrix substrate.
FIG. 3 shows a conventional TFT ESD protective circuit 11. The TFT ESD protective circuit 11 includes two TFT diodes t1, t2 reversely connected. The pattern of the TFT ESD protective circuit symbol is as shown in FIG. 4. The gate electrode G and drain electrode D of the TFT t1 are short-circuited and connected to the scanning signal line 3 and the data signal line 5. The source electrode S of the TFT t1 is connected to the Vcom 6. The source electrode S of the TFT t2 is connected to the scanning signal line 3 and data signal line 5. The gate electrode G and drain electrode D of the TFT t2 are short-circuited and connected to the Vcom 6.
The TFT t1 of the TFT ESD protective circuit 11 is an element for discharging positive electrostatic voltage, while the TFT t2 of the TFT ESD protective circuit 11 is an element for discharging negative electrostatic voltage. When positive electrostatic voltage is generated, the electrostatic voltage level rises higher than the threshold voltage of TFT. At this time, the transistor t1 is turned on and the positive electrostatic voltage via the scanning signal line 3 and data signal line 5 is discharged by the transistor t1. Similarly, when negative electrostatic voltage is generated, the transistor t2 discharges the negative electrostatic voltage to achieve ESD protection effect.
When the above TFT ESD protective circuit 11 protects the internal TFT array, the TFT ESD protective circuit 11 itself is in the danger of being damaged by the electrostatic voltage. In the case that the TFT cell is damaged by the electrostatic voltage, the insulating layer of the gate electrode will be broken down by the electrostatic voltage to cause very great leaking current. For example, in the case that the insulating layer of the gate electrode of the TFT t1 is broken down, the knot of gate electrode at the TFT t1 and the source electrode will be short-circuited. This leads to short-circuit of the scanning signal line 3, data signal line 5 and Vcom 6. This will form a defect on the display panel. The defect will result in that the picture cannot be normally shown in the cell test and module driving of the manufacturing procedure. This problem will affect the yield of products. Therefore, it is tried by the applicant to solve the above problem.
SUMMARY OF THE INVENTION
It is therefore a primary object of the present invention to enhance better ESD protective effect than before. Dividing into a positive ESD protective unit and a negative ESD protective unit is better design. The positive ESD protective unit and negative ESD protective unit are independently arranged for respectively discharging positive and negative electrostatic voltages. Each of the positive ESD protective unit and negative ESD protective unit is composed of three TFT for providing multifold ESD protective effect. In the case that the gate electrode insulating layer of any of the three TFT is broken down by electrostatic voltage, the remaining two TFT can still normally operate and keep truly providing ESD protective function. Therefore, the picture still can be normally shown on the display panel and the electrostatic durability of the display is enhanced.
The present invention can be best understood through the following description and accompanying drawings wherein:
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of the ESD protective circuit of the present invention;
FIG. 2 shows a conventional driving matrix liquid crystal display utilizing TFTs;
FIG. 3 is a circuit diagram of a conventional ESD protective circuit; and
FIG. 4 is a symbol of circuit diagram corresponding to the conventional ESD protective circuit.
 DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT
Please refer to FIG. 1. The TFT ESD protective circuit of the present invention is disposed between a scanning signal line 3, a data signal line 5 and a Vcom 6. The scanning signal line 3 and data signal line 5 are respectively connected to a scanning line pad 8 and a data line pad 9 of a driving chip. The TFT ESD protective circuit includes a positive ESD protective unit 13 composed of a first TFT T1, a second TFT T2 and a third TFT T3. The gate electrode G and drain electrode D of the first and second TFT T1, T2 are short-circuited and electrically connected with the scanning signal line 3 and data signal line 5. The source electrode S of the first TFT T1 is connected with the gate electrode G of the third TFT T3. The source electrode S of the second TFT T2 is connected with the drain electrode D of the third TFT T3. The source electrode S of the third TFT T3 is connected with the Vcom 6.
The TFT ESD protective circuit further includes a negative ESD protective unit 14 composed of a fourth TFT T4, a fifth TFT T5 and a sixth TFT T6. The gate electrode G and drain electrode D of the fourth and fifth TFT T4, T5 are short-circuited and connected with the Vcom 6. The source electrode S of the fifth TFT T5 is connected with the gate electrode G of the sixth TFT T6. The source electrode S of the fourth TFT T4 is connected with the drain electrode D of the sixth TFT T6. The source electrode S of the sixth TFT T6 is electrically connected with the scanning signal line 3 and data signal line 5.
The TFT ESD protective circuit of the present invention operates in such a manner that when positive electrostatic voltage is generated on the scanning signal line 3 and data signal line 5, the scanning signal line 3 and data signal line 5 are at high potential state. At this time, the positive electrostatic voltage via the scanning signal line 3 and data signal line 5 will go into the positive ESD protective unit 13. The electrostatic voltage rises higher than the TFT threshold voltage so that the electrostatic voltage is sufficient to turn on the first and second TFT T1, T2. In the instance of the first TFT T1 at ON state, the drain electrostatic voltage and source electrode voltage of the first TFT T1 is nearly equal to each other. The source electrode of the first TFT T1 and the gate electrode knot of the third TFT T3 have equal voltage potential. In addition, the voltage level is higher than the TFT threshold voltage. Therefore, the third TFT T3 is turned on. At this time, the first, second and third TFT T1, T2, T3 are all at on state. The positive electrostatic voltage via the second and third TFT T2, T3 is discharged. During the discharging procedure of the positive electrostatic voltage, the fourth, fifth and sixth TFT T4, T5, T6 are all turned off.
In the conventional TFT ESD protective circuit 11, in the case that the insulating layer of the gate electrode at TFT t1 is broken down, the scanning signal line 3 and data signal line 5 will be short-circuited with Vcom. This will lead to abnormal display of the display panel. In contrast to the conventional TFT ESD protective circuit 11, in the TFT ESD protective circuit of the present invention, in the case that the gate insulating layer of any of the first, second and third TFT T1, T2, T3 of the positive ESD protective unit 13 is broken down by the electrostatic voltage when the positive ESD protective unit 13 discharges the positive electrostatic voltage, for example, in the case that the gate insulating layer the first TFT T1 is broken down, the positive electrostatic voltage can be still discharged via the second and third TFT T2, T3. Similarly, in the case that the second TFT T2 is broken down, the positive electrostatic voltage can be still discharged via the third TFT T3. Similarly, in the case that the third TFT T3 is broken down, the positive electrostatic voltage can be still discharged via the first and second TFT T1, T2. Therefore, in the case that any of the three TFT is broken down, the remaining two TFT can still discharge the positive electrostatic voltage to avoid defect of the display panel. Accordingly, the TFT ESD protective circuit of the present invention can truly provide ESD protective effect and the picture still can be normally shown in the cell test and the module driving of the manufacturing procedure.
Similarly, when negative electrostatic voltage is generated, the fourth, fifth and sixth TFT T4, T5, T6 of the negative ESD protective unit 14 are all turned on for eliminating the negative electrostatic voltage. At this time, the first, second and third TFT T1, T2, T3 are all turned off. The negative ESD protective unit 14 has the same function as the positive ESD protective unit 13. In the case that any of the three TFT is broken down, the remaining two TFT can still normally operate to discharge the negative electrostatic voltage to avoid defect of the display panel and truly provide ESD protective effect. In conclusion, the ESD protective circuit of the present invention provides multifold ESD protective effect for the liquid crystal display and enhances the durability thereof.
The above embodiment is only used to illustrate the present invention, not intended to limit the scope thereof. Many modifications of the above embodiment can be made without departing from the spirit of the present invention.

Claims (4)

1. A TFT ESD protective circuit disposed between a scanning signal line or a data signal line and a Vcom, comprising:
a positive ESD protective unit composed of a first TFT, a second TFT and a third TFT, the gate electrode and drain electrode of the first and second TFT being short-circuited and connected with the scanning signal line and data signal line, the source electrode of the first TFT being connected with the gate electrode of the third TFT, the source electrode of the second TFT being connected with the drain electrode of the third TFT, the source electrode of the third TFT being connected with the Vcom; and
a negative ESD protective unit composed of a fourth TFT, a fifth TFT and a sixth TFT, the gate electrode and drain electrode of the fourth and fifth TFT being short-circuited and connected with the Vcom, the source electrode of the fifth TFT being connected with the gate electrode of the sixth TFT, the source electrode of the fourth TFT being connected with the drain electrode of the sixth TFT, the source electrode of the sixth TFT being connected with the scanning signal line and data signal line.
2. The TFT ESD protective circuit as claimed in claim 1, wherein the scanning signal line is electrically connected with the gate electrode and drain electrode of the first and second TFT and connected with the source electrode of the sixth TFT.
3. The TFT ESD protective circuit as claimed in claim 1, wherein the data signal line is electrically connected with the gate electrode and drain electrode of the first and second TFT and connected with the source electrode of the sixth TFT.
4. The TFT ESD protective circuit as claimed in claim 1, wherein the Vcom of the TFT ESD protective circuit connected with the scanning signal line and the TFT ESD protective circuit connected with the data signal line has equal voltage potential.
US10/878,005 2004-06-29 2004-06-29 Thin film transistor electrostatic discharge protective circuit Expired - Lifetime US7019796B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/878,005 US7019796B2 (en) 2004-06-29 2004-06-29 Thin film transistor electrostatic discharge protective circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/878,005 US7019796B2 (en) 2004-06-29 2004-06-29 Thin film transistor electrostatic discharge protective circuit

Publications (2)

Publication Number Publication Date
US20050285984A1 US20050285984A1 (en) 2005-12-29
US7019796B2 true US7019796B2 (en) 2006-03-28

Family

ID=35505263

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/878,005 Expired - Lifetime US7019796B2 (en) 2004-06-29 2004-06-29 Thin film transistor electrostatic discharge protective circuit

Country Status (1)

Country Link
US (1) US7019796B2 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060092591A1 (en) * 2004-10-28 2006-05-04 Quan Yuan On-substrate ESD protection for array based image sensors
US9501959B2 (en) 2013-09-25 2016-11-22 Samsung Display Co., Ltd. Mother substrate with switch disconnecting test part, array test method thereof and display substrate
WO2018116263A1 (en) 2016-12-24 2018-06-28 Indian Institute Of Science Low power electrostatic discharge protection circuit
CN109917595A (en) * 2017-12-12 2019-06-21 京东方科技集团股份有限公司 Dot structure and its driving method, display panel, display device

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7532265B2 (en) * 2005-06-08 2009-05-12 Wintek Corporation Integrated circuit with the cell test function for the electrostatic discharge protection
US20090128469A1 (en) * 2005-11-10 2009-05-21 Sharp Kabushiki Kaisha Display Device and Electronic Device Provided with Same
TWI310675B (en) * 2006-05-17 2009-06-01 Wintek Corp Flat panel display and display panel
US8253721B2 (en) * 2006-11-28 2012-08-28 Lg Display Co., Ltd. Liquid crystal display device including source voltage generator and method of driving liquid crystal display device
TW200828232A (en) * 2006-12-29 2008-07-01 Au Optronics Corp Data transmission circuit and LCD thereof
TWI342611B (en) * 2007-08-14 2011-05-21 Chunghwa Picture Tubes Ltd Active device array substrate
KR101884891B1 (en) * 2012-02-08 2018-08-31 삼성디스플레이 주식회사 Display device
CN103515941B (en) * 2012-06-21 2015-12-02 京东方科技集团股份有限公司 ESD protection circuit, array base palte and display unit
CN102967973B (en) * 2012-11-08 2015-10-14 京东方科技集团股份有限公司 A kind of ESD protection circuit and driving method and display panel
CN103199513B (en) * 2013-02-22 2016-04-06 合肥京东方光电科技有限公司 Electrostatic discharge protective circuit, display unit and electrostatic protection method
CN104021747A (en) 2014-05-23 2014-09-03 京东方科技集团股份有限公司 Panel function test circuit, display panel, function testing method and electrostatic protection method
CN106997132B (en) * 2017-05-27 2019-03-15 京东方科技集团股份有限公司 A kind of display base plate and display device
CN107039015B (en) * 2017-06-05 2019-05-10 京东方科技集团股份有限公司 A kind of display driver circuit and its control method, display device
CN110310950A (en) 2018-03-27 2019-10-08 三星电子株式会社 Display module and display panel
CN111627370A (en) * 2020-05-18 2020-09-04 武汉华星光电半导体显示技术有限公司 Low-leakage electrostatic discharge circuit and display panel
US11342324B2 (en) * 2020-05-18 2022-05-24 Wuhan China Star Optoelectronics Semiconductor Display Technology Co., Ltd. Low-leakage static electricity releasing circuit, display panel and display device

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5373377A (en) * 1992-02-21 1994-12-13 Kabushiki Kaisha Toshiba Liquid crystal device with shorting ring and transistors for electrostatic discharge protection
US5671026A (en) * 1994-03-02 1997-09-23 Sharp Kabushiki Kaisha Liquid crystal display device with TFT ESD protective devices between I/O terminals or with a short circuited alignment film
US5909035A (en) * 1997-01-10 1999-06-01 Lg Electronics Thin film transistor array having a static electricity preventing circuit
US6388719B1 (en) * 1999-07-12 2002-05-14 Hitachi, Ltd. Liquid crystal display device
US6690433B2 (en) * 2000-08-08 2004-02-10 Lg. Philips Lcd Co., Ltd. Electrostatic damage preventing apparatus for liquid crystal display

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5373377A (en) * 1992-02-21 1994-12-13 Kabushiki Kaisha Toshiba Liquid crystal device with shorting ring and transistors for electrostatic discharge protection
US5671026A (en) * 1994-03-02 1997-09-23 Sharp Kabushiki Kaisha Liquid crystal display device with TFT ESD protective devices between I/O terminals or with a short circuited alignment film
US5909035A (en) * 1997-01-10 1999-06-01 Lg Electronics Thin film transistor array having a static electricity preventing circuit
US6388719B1 (en) * 1999-07-12 2002-05-14 Hitachi, Ltd. Liquid crystal display device
US6690433B2 (en) * 2000-08-08 2004-02-10 Lg. Philips Lcd Co., Ltd. Electrostatic damage preventing apparatus for liquid crystal display

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060092591A1 (en) * 2004-10-28 2006-05-04 Quan Yuan On-substrate ESD protection for array based image sensors
US7532264B2 (en) * 2004-10-28 2009-05-12 Dpix Llc On-substrate ESD protection for array based image sensors
US9501959B2 (en) 2013-09-25 2016-11-22 Samsung Display Co., Ltd. Mother substrate with switch disconnecting test part, array test method thereof and display substrate
WO2018116263A1 (en) 2016-12-24 2018-06-28 Indian Institute Of Science Low power electrostatic discharge protection circuit
CN109917595A (en) * 2017-12-12 2019-06-21 京东方科技集团股份有限公司 Dot structure and its driving method, display panel, display device
CN109917595B (en) * 2017-12-12 2021-01-22 京东方科技集团股份有限公司 Pixel structure, driving method thereof, display panel and display device
US10921659B2 (en) 2017-12-12 2021-02-16 Hefei Xinsheng Optoelectronics Technology Co., Ltd. Pixel structure, drive method thereof, display panel, and display device

Also Published As

Publication number Publication date
US20050285984A1 (en) 2005-12-29

Similar Documents

Publication Publication Date Title
US7019796B2 (en) Thin film transistor electrostatic discharge protective circuit
US9767727B2 (en) Display panel
US5657139A (en) Array substrate for a flat-display device including surge protection circuits and short circuit line or lines
US5606340A (en) Thin film transistor protection circuit
US5744837A (en) Semiconductor device comprising a matrix array, and thin-film transistor liquid-crystal display device
TWI385453B (en) Liquid crystal display
EP1898389A1 (en) Flat panel display device
US7532265B2 (en) Integrated circuit with the cell test function for the electrostatic discharge protection
TWI312144B (en)
US8068082B2 (en) Display apparatus
US7893441B2 (en) Flat panel display including electrostatic protection circuit
US10042223B2 (en) TFT arrays, display panels, and display devices
TWI453517B (en) Pixel array substrate of liquid crystal display
TWI354967B (en) Liquid crystal display
US8031281B2 (en) Liquid crystal display having capacitors as protection elements
US10483292B2 (en) Array substrate and display panel
US7358536B2 (en) Active matrix substrate
JP2008176089A (en) Electrooptical device
RU2731838C1 (en) Protective circuit, matrix substrate and display panel
WO2017041457A1 (en) Protective circuit for gate driver on array unit, and array substrate
JP4547957B2 (en) Electro-optical device and electronic apparatus
JP2008116770A (en) Display device
JPH11233777A (en) Semiconductor device and display device
JP4947801B2 (en) Liquid crystal display
JPWO2007055047A1 (en) Display device and electronic device including the same

Legal Events

Date Code Title Description
AS Assignment

Owner name: WINTEK CORPORATION, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TSAI, JA-FU;WANG, WEN-CHUN;REEL/FRAME:017129/0236

Effective date: 20040524

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FEPP Fee payment procedure

Free format text: ENTITY STATUS SET TO SMALL (ORIGINAL EVENT CODE: SMAL)

FEPP Fee payment procedure

Free format text: MAINTENANCE FEE REMINDER MAILED (ORIGINAL EVENT CODE: REM.)

FEPP Fee payment procedure

Free format text: 11.5 YR SURCHARGE- LATE PMT W/IN 6 MO, SMALL ENTITY (ORIGINAL EVENT CODE: M2556)

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YR, SMALL ENTITY (ORIGINAL EVENT CODE: M2553)

Year of fee payment: 12