US6954879B1 - Method and apparatus for communicating configuration data for a peripheral device of a microcontroller via a scan path - Google Patents

Method and apparatus for communicating configuration data for a peripheral device of a microcontroller via a scan path Download PDF

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US6954879B1
US6954879B1 US10661894 US66189403A US6954879B1 US 6954879 B1 US6954879 B1 US 6954879B1 US 10661894 US10661894 US 10661894 US 66189403 A US66189403 A US 66189403A US 6954879 B1 US6954879 B1 US 6954879B1
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configuration
registers
peripheral
register
scan
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David F. Tobias
Richard G. Russell
Mark T. Ellis
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GlobalFoundries Inc
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Advanced Micro Devices Inc
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    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317Testing of digital circuits
    • G01R31/3181Functional testing
    • G01R31/3185Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536Scan chain arrangements, e.g. connections, test bus, analog signals

Abstract

A microcontroller has many internal peripheral devices. The peripheral devices are coupled to a scan path. A memory storage device that is external to the microcontroller is also coupled to the scan path. When commanded, data is shifted out of each device configuration register onto the scan path and stored in the external memory device. This is particularly useful for obtaining the states of each device without bringing down the application. Furthermore, configuration data stored in external memory can be loaded into the peripheral device configuration registers via the scan path. This invention also supports zero-volt suspend/resume which does not need extra software readable shadow registers which are often required in other architectures for reading back the current state of legacy registers which are read-only.

Description

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a divisional of co-pending U.S. patent application Ser. No. 10/106,631, filed Mar. 26, 2002, which is incorporated herein in its entirety by reference, which is a continuation of U.S. patent application Ser. No. 09/209,190, filed Dec. 10, 1998, now U.S. Pat. No. 6,363,501, which is incorporated by reference in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The apparatus and method according to the invention pertains to peripheral state registers embedded in a microcontrollers, and more specifically, using scan hardware to capture peripheral device states.

2. Description of the Related Art

The proliferation of electronic goods such as telephones, televisions, and video camcorders has been made possible by integrated circuit technology. One type of integrated circuit especially important to electronic devices is the microcontroller.

A microcontroller, or embedded controller, is similar to a microprocessor as used in a personal computer, but with a great deal of additional functionality combined onto the same monolithic semiconductor substrate (i.e., chip). In a typical personal computer, the microprocessor performs the basic computing functions, but other integrated circuits perform functions such as communicating over a network, providing input/output with the user, and controlling peripherals.

In a typical microcontroller, many of these functions are embedded within the integrated circuit chip itself. A typical microcontroller, such as the Am186ES by Advanced Micro Devices, Inc., of Sunnyvale, Calif., not only includes a core microprocessor, but also further includes a memory controller, a direct memory access (DMA) controller, an interrupt controller, and both asynchronous and synchronous serial interfaces. In computer systems, these peripheral devices are typically implemented as separate integrated circuits, requiring a larger area and increasing the size of the product. By embedding these functions within a single chip, size and cost are reduced, often important in consumer products.

From a consumer products designer's viewpoint, often the particular combination of added features makes a particular microcontroller attractive for a given application. Many microcontrollers are available that use the standard 80×86 microprocessor instructions, allowing for software to be easily developed for such microcontrollers. Because of the similar execution unit instruction sets, the added features often become principal differentiating criteria between particular microcontrollers.

The peripheral devices embedded in a microcontroller each have their own individual registers. Typical peripheral device registers include state registers, instruction registers, address registers, status registers and data registers. Depending on the peripheral, certain registers store configuration information needed for the peripheral's proper operation during start up. On system start up, the execution unit initializes each peripheral device with device specific initial configuration data. This initialization could occur during a cold start-up, zero-volt suspend/resume procedure or after a system crash.

In addition to having peripheral devices, many of today's microcontrollers have embedded test circuitry. In 1985, a group of European companies formed Joint European Test Action Group (JETAG) to devise ways to reduce manufacturing costs. One concept was to incorporate such test circuitry into standard components (controlled via software), eliminating the need for sophisticated in-circuit test equipment. This concept gained support in the U.S., where in 1988, several North American companies formed the Joint Test Access Group (JTAG) consortium to formalize the concept. In 1990, the Institute of Electrical and Electronic Engineers (IEEE) refined the concept and created the 1149.1 standard (which is incorporated herein by reference), known as IEEE Standard Test Access Port and Boundary Scan Architecture.

In such architecture, a JTAG test device is connected to a microcontroller and performs a “boundary-scan test” on the microcontroller. Boundary scan cells contain shift register elements that connect together to form a scan chain around the core logic circuit. Input/output (I/O) signals freely pass between integrated circuit (IC) pins and the core logic, through the boundary scan cells, in normal mode. However, in test mode, only test signals are allowed to pass into or out of the core logic, via a test port and through the boundary scan chain, providing observability and controllability of the input and output signals. The JTAG test commands are typically drawn from a fairly limited set of commands particularly adapted for testing the interconnections of microcontrollers and are not typically well suited for testing or monitoring its internal logic. Instructions and associated data for testing are read serially into each microcontroller peripheral boundary scan cell registers and read out serially, and after the instructions has been carried out the result is read out serially.

While boundary scan techniques are useful in testing interconnection between components, the scan path does not include internal logic registers. In full scan path design, typically all registers and storage elements are connected in the scan paths.

Furthermore, access to registers of peripheral devices may not be possible using I/O commands. Some of these registers may not have both read/write capabilities. Thus, data cannot be written to read-only registers with processor I/O commands and data cannot be read from write-only registers with processor I/O commands.

BRIEF SUMMARY OF THE INVENTION

According to the invention, the configuration states of peripheral devices that are embedded in a microcontroller are saved using scan hardware. Various configuration registers, both internal (non-I/O registers) and external (I/O registers), are connected in a configuration scan path internal to the peripheral device. When it is desirable to save the configuration state(s) of the peripheral device(s), the configuration scan path is scanned, and this data can be stored in an external memory device. The external memory device can be either volatile or non-volatile.

In addition, in one embodiment, the scan path is IEEE 1149.1 compliant. Furthermore, according to the invention, various configuration registers, both internal and external, can be saved to an external memory device without intervention of the execution unit of the microcontroller. Instead of the execution unit issuing read and write commands to the various configuration registers and an external memory, configuration data is scanned out to the external memory via a scan path.

Also according to the invention, the configuration states of peripheral devices can be loaded into peripheral device registers using scan hardware. Configuration states can be stored in external memory and shifted into the configuration registers of peripheral devices via a scan path.

Furthermore, according to the invention, configuration states of peripheral devices can be loaded into peripheral device registers that are read-only and saved from peripheral device registers that are write-only by using this scan path.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

A better understanding of the present invention can be obtained when the following detailed description of the preferred embodiment is considered in conjunction with the following drawings, in which:

FIG. 1 shows a typical microcontroller in which the techniques of this invention can be implemented;

FIG. 2 is a block diagram illustrating a scan path between peripheral devices;

FIG. 3 is a block diagram illustrating the internal registers of a peripheral device, namely a universal asynchronous receiver and transmitter (UART);

FIG. 4 is a block diagram illustrating configuration registers within a peripheral device;

FIG. 5 is a flow chart illustrating the method of saving the configuration states of a peripheral device; and

FIG. 6 is a flow chart illustrating the method of loading the configuration states of a peripheral device.

DETAILED DESCRIPTION OF THE INVENTION

Turning to FIG. 1, shown is a block diagram of a typical microcontroller M implemented according to the invention. Such a microcontroller is preferably implemented on a single monolithic integrated circuit. The microcontroller M preferably includes an internal bus 100 coupling a variety of functional units and registers used to control and monitor those units. These include a clock and power management unit 102 with corresponding clock/power registers 104, an interrupt control unit (ICU)106 with corresponding interrupt registers 108, a timer control unit 110 with corresponding timer registers 112, a direct memory access (DMA) unit 114 with corresponding DMA registers 116, a bus interface unit 118 with corresponding bus interface registers 120, an execution unit 124 which is essentially a microprocessor core, a chip select unit 126 with corresponding chip select registers 128, a programmable input/output (PIO) unit 132 with corresponding PIO registers 134, an asynchronous serial port 136 with corresponding asynchronous register 138, and a synchronous serial port 140 with corresponding synchronous registers 142. Further, note the clock and power management unit 102 includes external pads connected to a crystal 144, which provides the timing not only for the execution unit 124, but also for generating the serial clock in the asynchronous serial port 136.

The block diagram of the microcontroller M is typical of microcontrollers, and could be for example, the Am186ES microcontroller by Advanced Micro Devices, Inc., of Sunnyvale, Calif. The techniques and circuitry according to the invention, however, could be applied to a wide variety of microcontrollers as well as other devices that use a non-ideal clock for generation of asynchronous serial port clocks. Further, the term “microcontroller” has differing definitions in industry. Some companies refer to a processor core with additional features (such as I/O) as a “microprocessor” if it has no onboard memory, and digital signal processors (DSPs) are now used for both special and general purpose controller functions. So as here used, the term “microcontroller” covers all of the products, and generally means an execution unit with added functionality all implemented on a single monolithic integrated circuit.

Scan Hardware

Microcontrollers that are IEEE 1149.1 compliant have boundary scan paths that couple the registers of peripheral device's I/O pins. Boundary scan provides access to the periphery of the microcontroller, but not the internal registers of the execution unit and peripheral devices. In full scan path design, all registers are connected in the scan paths. Scan paths connect individual flip-flops within a register and then connect the registers, e.g., bit one of register one is connected to bit two of register one, and bit two is connected to bit three of register one, and so on until the last bit of register one is connected to bit one of register two. According to the invention, scan is implemented on sufficient registers to save configuration state of the device. Furthermore, it is not necessary to capture all data from each register to determine the state of the device. For instance, data from a status register may not be needed to determine the configuration state of the device.

FIG. 2 illustrates typical peripheral devices embedded in a microcontroller M with a scan path. An input pin IN of microcontroller M is provided to shift configuration data into each peripheral configuration register. The configuration registers of the clock and power management unit 102, interrupt control unit 106, timer control unit 110, DMA unit 114, PIO unit 132, asynchronous serial port 136, synchronous serial port 140, chip select unit 126 and bus interface unit 118 are daisy chained together via signal line SCANPATH. For illustrative purposes, the SCANPATH line from the output of the bus interface unit configuration registers 120 a is coupled to the output pin OUT of the microcontroller M. Data is synchronously shifted in or out of each configuration register utilizing clock CLKSCAN. The data out pin OUT is coupled to an external memory 200. Thus, the configuration data from each peripheral device is sequentially shifted out of each configuration register into external memory 200 via SCANPATH. Likewise, the external memory 200 is coupled to the input pin IN, so that data from external memory 200 can be synchronously shifted into each peripheral configuration register via SCANPATH.

Peripheral Device Registers

Peripheral devices embedded in microcontrollers have many different registers that store data for use in a variety of functions. Sometimes, registers necessarily define a configuration state of a peripheral. Other times, registers contain transitory information (such as UART receive status bits) that are not strictly needed to establish the peripheral's configuration. Further, whether a register has information “necessary” to define a peripheral configuration may depend on the particular implementation of the peripheral and its applications. As an illustration, one such peripheral device is an asynchronous serial port 136. A common asynchronous serial port is a Universal Asynchronous Receiver and Transmitter (UART) 300. The UART 300 is one peripheral that provides a serial interface of the microcontroller M. Some of the peripheral's functions include the serialization of parallel data and the insertion of start, parity, and stop bits, or the parallelization of serial data and the separation of start, parity, and stop bits.

FIG. 3 is a block diagram of a typical implementation of the UART 300. The UART 300 has eleven configuration and status registers. The configuration registers include a receiver buffer register 302, data format register 304, divisor latch register (LSB) 306, divisor latch register (MSB) 308, modem control register 310, interrupt enable register 314, interrupt ID register 316, scratch pad register 318, and transmitter hold register 322. The status registers include a modem status register 312 and a serialization status register 320. The registers provide the necessary storage area for interfacing the UART 300 to the rest of the peripheral devices of microcontroller M.

Configuration State Registers

FIG. 4 is a block diagram of a scan path coupling the registers of a peripheral device. For illustrative purposes, the registers from the UART 300 are shown. Since it is not necessary to capture the data from all registers, the scan path couples those registers used to define the device's configuration. For example, in this implementation the status registers 312 and 320, receiver shift register 324 and transmitter shift register 326 of the device are left out of the scan path. A clock signal CLKSCAN is provided to the device for synchronous data shifting. The SCANPATH IN is coupled to the receiver buffer 302. The SCANPATH IN line could have originated from a SCANPATH OUT of other peripheral device or from input pin IN. The registers from the receiver buffer 302 are coupled to the data format register 304. Next, the divisor latch (LSB) register 306 is coupled to the divisor latch (MSB) register 308. The divisor latch (MSB) register 308 is then coupled to the modem control register 310. Next, the modem control register 310 is coupled to the interrupt enable register 314, bypassing the modem status register 312. The interrupt enable register 314 is then coupled to the interrupt ID register 316. The interrupt ID register 316 is coupled to the scratch pad register 318. The scratch pad register 318 is coupled to the transmitter hold register 322, bypassing the serialization status register 320. The transmitter hold register 322 is then coupled to the next peripheral configuration register or output pin OUT.

One skilled in the art could appreciate that inclusion or exclusion of particular registers to be saved can be different from system to system. That is, some predetermined subset of configuration registers could differ according to the system. For example, in a high speed system that quickly restarts, it might be desirable to include status registers in the scan path. Thus, the modem status register 312 and/or serialization status register 320 of the UART 300 can be included in the scan path.

In addition, internal registers (as opposed to I/O registers) can be included in the scan path. The contents of these registers are typically not ascertainable without debug tools or the addition of shadow registers, but it might be desirable to include these registers in the scan path. For example, the receiver shift register 324 and/or transmitter shift register 326 of the UART 300 can be included in the scan path.

Furthermore, externally accessible registers (I/O registers) may have read, write, or read/write capabilities. But using standard I/O commands, data cannot be saved from write-only registers nor written to read-only registers. As an example, the receiver buffer register 302 is typically a read-only register. Configuration data normally cannot be loaded into this register with a write command from execution unit 124.

This inability to read from or write to particular registers can present problems when saving and restoring a peripherals state through routines run by the execution unit 124. Typically, when entering and exiting low power or hibernation modes, a peripherals state is saved and restored via low level power up and power down routines. However, this becomes problematic when read- or write-only registers (or internal hidden registers) are employed. Similar problems arise with locked registers and registers that access different functionality on reads than on writes (i.e., a read returns status; a write alters control).

These legacy-style registers could be made read/write, but that might cause existing software to malfunction. The registers could be made read/write in response to a special mode of operation, but that could require extensive modifications to peripheral cores. Therefore, saving and restoring a peripheral gracefully can be difficult when the peripheral has read-only, write-only, locked, hidden, or otherwise inaccessible registers.

Using the configuration scan path according to the invention provides a graceful approach to those problems. Whether registers necessary for peripheral configuration are read-only, write-only, hidden, locked, or otherwise difficult to save and restore using processor reads and writes, the configuration scan chain can capture that information.

Returning to the example of the receiver buffer register 302, because it is coupled to the scan path (as shown in FIG. 4), configuration data can be shifted into this register via SCANPATH. Likewise, the transmitter hold register 322 typically has write-only capabilities. Data from this register normally cannot be ascertained with I/O commands (or memory commands for memory mapped I/O) from execution unit 124. As shown in FIG. 4, transmitter hold register 322 is coupled to the scan path and configuration data can be shifted out of this register via SCANPATH.

Finally, an example of a peripheral device with external registers that cannot be accessed easily by software due to the nature of the hardware. One example is the interrupt control unit 106. A common interrupt control unit is the legacy 8259 Å style programmable interrupt controller. This controller uses four initialization control words, namely Initialization Command Words (ICW) ICW1-ICW4, which are written sequentially into the device via a single I/O port to four registers. The four registers can be included as configuration registers 108 a and are typically write-only registers. Therefore, the registers cannot be read back out. As shown in FIG. 2, coupling the configuration registers 108 a to the scan path, configuration states of the interrupt control unit 106 can be loaded into external memory 200.

Memory Storage Device

Configuration data that is clocked out of the peripheral devices is preferably stored in external memory 200. Configuration data can also be clocked into the peripheral device from external memory 200. Various memory storage devices could be utilized both volatile and non-volatile. One embodiment of the present invention would utilize a serial EEPROM.

IEEE 1149.1 JTAG Boundary Scan and Test Access Port

Another embodiment of the invention utilizes the JTAG boundary scan path and Test Access Port (TAP) hardware to save the configuration data of the peripheral devices or load configuration data into the peripheral devices. For microcontrollers that are IEEE 1149.1 compliant, the scan paths SCANPATH for each peripheral configuration register can be coupled to the boundary scan. The IEEE 1149.1 standard (May 21, 1990) is described in the publication IEEE Standard Test Access Port and Boundary-Scan Architecture, published by the IEEE, Piscataway, N.J. (herein incorporated by reference.)

A command instruction is loaded through the TAP. When the registers are clocked, configuration data is shifted out of the peripheral device register onto the boundary scan path. In addition, the memory storage device could be coupled to the Test Access Port for easy load/storage of configuration data.

FIG. 5 is a flow diagram illustrating the method of saving configuration data according to the invention. The method starts at step 500. A command to initiate configuration save is initiated at step 502. A clock is provided to the configuration registers and external memory 200 at step 504. At each clock cycle, configuration data is shifted from the peripheral configuration registers at step 506. The configuration data is stored in external memory 200 at step 508. If all of the configuration data has not been saved at step 510, the method jumps to step 504. If all configuration data is saved at step 510, the microcontroller is suspended at step 512. The method ends at 514. This could be initiated by a power down routine for example.

FIG. 6 is a flow diagram illustrating the method of loading configuration data according to the invention. The method starts at step 600. A command to initiate configuration load is initiated at step 602. A clock is provided to the configuration registers and external memory 200 at step 604. At each clock cycle, configuration data is loaded into each peripheral configuration register from external memory 200 at step 606. If not all configuration data has been loaded into the peripheral configuration registers, the method jumps to step 604. If all configuration data has been loaded into the peripheral configuration registers than the microcontroller resumes operation at step 610. The method ends at step 612.

The saving of configuration states of peripheral devices can occur during different scenarios. For example, it might be desirable to save the configuration states of peripheral devices prior to a system power down. The states could be saved in non-volatile memory. On power-up, it might be desirable to load the saved states into the peripheral devices as opposed to loading a default configuration setting.

In addition, it might be desirable to save the configuration states of peripheral devices prior to the system entering a sleep or suspend mode. In sleep mode, the system operates under low power. Some peripheral devices might be unable to retain their data while the system is asleep. When the system is awakened or resumes operation, the configuration states can be loaded into the peripheral devices.

Furthermore, it might be desirable to save the configuration states in the event of a system failure. Configuration states can be periodically saved. Thus, if a system failure should occur, the last saved configuration state could be loaded into the peripheral device, instead of loading the default configuration setting.

By saving the configuration states using the scan path, reconfiguration of the peripheral device registers can be accomplished without intervention of the execution unit 124 of microcontroller M. Thus, there would be no need to reload configuration data with I/O commands. As discussed previously, some configuration registers may not be accessible via processor I/O commands because the registers are internal or may be read-only or write-only.

The foregoing disclosure and description of the invention are illustrative and explanatory thereof, and various changes in the size, shape, materials, components, circuit elements, wiring connections and contacts, as well as in the details of the illustrated circuitry and construction and method of operation may be made without departing from the spirit of the invention.

Claims (11)

1. A microcontroller, comprising:
an execution unit;
a peripheral device coupled to the execution unit, the peripheral device comprising configuration registers;
a means for defining a scan path comprising the configuration registers and for communicating configuration data for the peripheral device; and
a means for saving the configuration data via the scan path.
2. A microcontroller, comprising:
an execution unit;
a peripheral device coupled to the execution unit, the peripheral device comprising configuration registers;
a means for defining a scan path comprising the configuration registers and for communicating configuration data for the peripheral device; and
a means for loading the configuration data via the scan path.
3. A method of saving configuration data for a peripheral device of a microcontroller, the method comprising the steps of:
detecting a command to save configuration data for a peripheral device of a microcontroller; and
saving the configuration data via a scan path comprising a configuration register of the peripheral device in response to the command.
4. The method of claim 3, wherein the saving step is performed prior to placing the microcontroller in a reduced power mode.
5. The method of claim 3, wherein the saving step is performed periodically.
6. The method of claim 3, wherein the configuration register comprises an internal register of the peripheral device.
7. The method of claim 3, wherein the configuration register comprises a read-only register.
8. A method of loading configuration data for a peripheral device of a microcontroller, the method comprising the steps of:
detecting a command to load configuration data for a peripheral device of a microcontroller; and
loading the configuration data via a scan path comprising a configuration register of the peripheral device in response to the command.
9. The method of claim 8, wherein the loading step occurs prior to resumption of activity by the microcontroller.
10. The method of claim 8, wherein the configuration register comprises an internal register of the peripheral device.
11. The method of claim 8, wherein the configuration register comprises a write-only register.
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US10106631 US6928586B1 (en) 1998-12-10 2002-03-26 Method and apparatus for saving peripheral device states of a microcontroller
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Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050071719A1 (en) * 2003-09-25 2005-03-31 International Business Machines Corporation Method and apparatus for diagnosis and behavior modification of an embedded microcontroller
US20070028080A1 (en) * 2005-07-29 2007-02-01 Hobson Louis B Sleep state resume
US7313730B1 (en) * 2004-05-20 2007-12-25 Xilinx, Inc. Configuration logic for embedded software
CN100476729C (en) 2006-01-10 2009-04-08 英业达股份有限公司 Method and system configuring data optimal sequential processing on auxiliary equipment of computer
US20100121988A1 (en) * 2008-11-12 2010-05-13 Microchip Technology Incorporated Dynamic state configuration restore
US20110029694A1 (en) * 2009-08-03 2011-02-03 Advanced Micro Devices, Inc. Software controlled redirection of configuration address spaces
US20110082987A1 (en) * 2009-10-01 2011-04-07 Dell Products L.P. Systems and Methods for Power State Transitioning in an Information Handling System
EP2453362A3 (en) * 2010-11-16 2012-09-19 Canon Kabushiki Kaisha Data transferring apparatus and control method thereof
US20150208124A1 (en) * 2014-01-21 2015-07-23 Mstar Semiconductor, Inc. Smart television system and turn-on and turn-off method thereof

Citations (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710931A (en) 1985-10-23 1987-12-01 Texas Instruments Incorporated Partitioned scan-testing system
US4947357A (en) 1988-02-24 1990-08-07 Stellar Computer, Inc. Scan testing a digital system using scan chains in integrated circuits
US5133071A (en) 1987-11-25 1992-07-21 Hitachi, Ltd. Channel control method and apparatus
US5157781A (en) 1990-01-02 1992-10-20 Motorola, Inc. Data processor test architecture
US5168555A (en) 1989-09-06 1992-12-01 Unisys Corporation Initial program load control
US5173904A (en) * 1987-06-02 1992-12-22 Texas Instruments Incorporated Logic circuits systems, and methods having individually testable logic modules
US5281864A (en) 1991-05-23 1994-01-25 Motorola Gmbh Implementation of the IEEE 1149.1 boundary-scan architecture
US5291495A (en) 1991-07-12 1994-03-01 Ncr Corporation Method for designing a scan path for a logic circuit and testing of the same
US5301156A (en) 1991-07-18 1994-04-05 Hewlett-Packard Company Configurable self-test for embedded RAMs
US5325368A (en) 1991-11-27 1994-06-28 Ncr Corporation JTAG component description via nonvolatile memory
US5329533A (en) 1991-12-26 1994-07-12 At&T Bell Laboratories Partial-scan built-in self-test technique
US5377198A (en) 1991-11-27 1994-12-27 Ncr Corporation (Nka At&T Global Information Solutions Company JTAG instruction error detection
US5377200A (en) 1992-08-27 1994-12-27 Advanced Micro Devices, Inc. Power saving feature for components having built-in testing logic
US5416409A (en) 1992-03-23 1995-05-16 Ministor Peripherals International Limited Apparatus and method for testing circuit board interconnect integrity
US5423050A (en) 1991-11-27 1995-06-06 Ncr Corporation Intermodule test across system bus utilizing serial test bus
US5428623A (en) 1993-07-01 1995-06-27 Tandem Computers Incorporated Scannable interface to nonscannable microprocessor
US5428622A (en) 1993-03-05 1995-06-27 Cyrix Corporation Testing architecture with independent scan paths
US5434804A (en) 1993-12-29 1995-07-18 Intel Corporation Method and apparatus for synchronizing a JTAG test control signal to an on-chip clock signal
US5477545A (en) 1993-02-09 1995-12-19 Lsi Logic Corporation Method and apparatus for testing of core-cell based integrated circuits
US5485466A (en) * 1993-10-04 1996-01-16 Motorola, Inc. Method and apparatus for performing dual scan path testing of an array in a data processing system
US5577052A (en) 1992-10-16 1996-11-19 Texas Instruments Incorporated Scan based testing for analogue circuitry
US5608736A (en) 1991-06-06 1997-03-04 Texas Instruments Incorporated Method and apparatus for a universal programmable boundary scan driver/sensor circuit
US5610926A (en) 1993-02-25 1997-03-11 Texas Instruments Incorporated Method & circuit for testing ic logic circuits
US5623503A (en) 1994-01-31 1997-04-22 Lucent Technologies Inc. Method and apparatus for partial-scan testing of a device using its boundary-scan port
US5627842A (en) 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
US5627841A (en) 1994-10-05 1997-05-06 Nec Corporation Integrated logic circuit with partial scan path circuit and partial scan path design method for same
US5636228A (en) 1996-01-16 1997-06-03 Motorola, Inc. Scan register with decoupled scan routing
US5668490A (en) 1996-05-01 1997-09-16 Sun Microsystems, Inc. Flip-flop with full scan capability
US5694399A (en) * 1996-04-10 1997-12-02 Xilinix, Inc. Processing unit for generating signals for communication with a test access port
US5703818A (en) 1996-08-26 1997-12-30 Mitsubishi Denki Kabushiki Kaisha Test circuit
US5717701A (en) 1996-08-13 1998-02-10 International Business Machines Corporation Apparatus and method for testing interconnections between semiconductor devices
US5784382A (en) 1995-03-01 1998-07-21 Unisys Corporation Method and apparatus for dynamically testing a memory within a computer system
US5802075A (en) * 1997-01-16 1998-09-01 Unisys Corporation Distributed test pattern generation
US5815706A (en) 1992-02-07 1998-09-29 Dell Usa, L.P. Computer system with plug-in override of system ROM
US5841792A (en) 1995-10-06 1998-11-24 Fujitsu Limited Processing system having a testing mechanism
US5898232A (en) 1995-11-08 1999-04-27 Advanced Micro Devices, Inc. Input/output section of an integrated circuit having separate power down capability
US5933626A (en) * 1997-06-12 1999-08-03 Advanced Micro Devices, Inc. Apparatus and method for tracing microprocessor instructions
US5968196A (en) 1998-04-21 1999-10-19 Atmel Corporation Configuration control in a programmable logic device using non-volatile elements
US6020757A (en) 1998-03-24 2000-02-01 Xilinx, Inc. Slew rate selection circuit for a programmable device
US6097988A (en) 1998-02-10 2000-08-01 Advanced Micro Devices, Inc. Logic system and method employing multiple configurable logic blocks and capable of implementing a state machine using a minimum amount of configurable logic
US6102963A (en) 1997-12-29 2000-08-15 Vantis Corporation Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's
US6125463A (en) 1997-06-13 2000-09-26 Bull Hn Information Systems Italia S.P.A. Integrated circuit with serial test interface and logic for loading a functional register using said interface
US6321354B1 (en) 1997-04-29 2001-11-20 Sgs-Thomson Microelectronics S.A. Testable circuit with a low number of leads
US6363501B1 (en) 1998-12-10 2002-03-26 Advanced Micro Devices, Inc. Method and apparatus for saving and loading peripheral device states of a microcontroller via a scan path
US6530050B1 (en) * 1998-12-10 2003-03-04 Advanced Micro Devices Inc. Initializing and saving peripheral device configuration states of a microcontroller using a utility program
US6550031B1 (en) * 1999-10-06 2003-04-15 Advanced Micro Devices Inc. Transparently gathering a chips multiple internal states via scan path and a trigger

Patent Citations (47)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4710931A (en) 1985-10-23 1987-12-01 Texas Instruments Incorporated Partitioned scan-testing system
US5173904A (en) * 1987-06-02 1992-12-22 Texas Instruments Incorporated Logic circuits systems, and methods having individually testable logic modules
US5133071A (en) 1987-11-25 1992-07-21 Hitachi, Ltd. Channel control method and apparatus
US4947357A (en) 1988-02-24 1990-08-07 Stellar Computer, Inc. Scan testing a digital system using scan chains in integrated circuits
US5168555A (en) 1989-09-06 1992-12-01 Unisys Corporation Initial program load control
US5157781A (en) 1990-01-02 1992-10-20 Motorola, Inc. Data processor test architecture
US5281864A (en) 1991-05-23 1994-01-25 Motorola Gmbh Implementation of the IEEE 1149.1 boundary-scan architecture
US5608736A (en) 1991-06-06 1997-03-04 Texas Instruments Incorporated Method and apparatus for a universal programmable boundary scan driver/sensor circuit
US5726999A (en) 1991-06-06 1998-03-10 Texas Instruments Incorporated Method and apparatus for universal programmable boundary scan driver/sensor circuit
US5291495A (en) 1991-07-12 1994-03-01 Ncr Corporation Method for designing a scan path for a logic circuit and testing of the same
US5301156A (en) 1991-07-18 1994-04-05 Hewlett-Packard Company Configurable self-test for embedded RAMs
US5377198A (en) 1991-11-27 1994-12-27 Ncr Corporation (Nka At&T Global Information Solutions Company JTAG instruction error detection
US5325368A (en) 1991-11-27 1994-06-28 Ncr Corporation JTAG component description via nonvolatile memory
US5423050A (en) 1991-11-27 1995-06-06 Ncr Corporation Intermodule test across system bus utilizing serial test bus
US5329533A (en) 1991-12-26 1994-07-12 At&T Bell Laboratories Partial-scan built-in self-test technique
US5815706A (en) 1992-02-07 1998-09-29 Dell Usa, L.P. Computer system with plug-in override of system ROM
US5416409A (en) 1992-03-23 1995-05-16 Ministor Peripherals International Limited Apparatus and method for testing circuit board interconnect integrity
US5377200A (en) 1992-08-27 1994-12-27 Advanced Micro Devices, Inc. Power saving feature for components having built-in testing logic
US5577052A (en) 1992-10-16 1996-11-19 Texas Instruments Incorporated Scan based testing for analogue circuitry
US5627842A (en) 1993-01-21 1997-05-06 Digital Equipment Corporation Architecture for system-wide standardized intra-module and inter-module fault testing
US5477545A (en) 1993-02-09 1995-12-19 Lsi Logic Corporation Method and apparatus for testing of core-cell based integrated circuits
US5610926A (en) 1993-02-25 1997-03-11 Texas Instruments Incorporated Method & circuit for testing ic logic circuits
US5428622A (en) 1993-03-05 1995-06-27 Cyrix Corporation Testing architecture with independent scan paths
US5428623A (en) 1993-07-01 1995-06-27 Tandem Computers Incorporated Scannable interface to nonscannable microprocessor
US5485466A (en) * 1993-10-04 1996-01-16 Motorola, Inc. Method and apparatus for performing dual scan path testing of an array in a data processing system
US5434804A (en) 1993-12-29 1995-07-18 Intel Corporation Method and apparatus for synchronizing a JTAG test control signal to an on-chip clock signal
US5623503A (en) 1994-01-31 1997-04-22 Lucent Technologies Inc. Method and apparatus for partial-scan testing of a device using its boundary-scan port
US5627841A (en) 1994-10-05 1997-05-06 Nec Corporation Integrated logic circuit with partial scan path circuit and partial scan path design method for same
US5784382A (en) 1995-03-01 1998-07-21 Unisys Corporation Method and apparatus for dynamically testing a memory within a computer system
US5841792A (en) 1995-10-06 1998-11-24 Fujitsu Limited Processing system having a testing mechanism
US5898232A (en) 1995-11-08 1999-04-27 Advanced Micro Devices, Inc. Input/output section of an integrated circuit having separate power down capability
US5636228A (en) 1996-01-16 1997-06-03 Motorola, Inc. Scan register with decoupled scan routing
US5694399A (en) * 1996-04-10 1997-12-02 Xilinix, Inc. Processing unit for generating signals for communication with a test access port
US5668490A (en) 1996-05-01 1997-09-16 Sun Microsystems, Inc. Flip-flop with full scan capability
US5717701A (en) 1996-08-13 1998-02-10 International Business Machines Corporation Apparatus and method for testing interconnections between semiconductor devices
US5703818A (en) 1996-08-26 1997-12-30 Mitsubishi Denki Kabushiki Kaisha Test circuit
US5802075A (en) * 1997-01-16 1998-09-01 Unisys Corporation Distributed test pattern generation
US6321354B1 (en) 1997-04-29 2001-11-20 Sgs-Thomson Microelectronics S.A. Testable circuit with a low number of leads
US5933626A (en) * 1997-06-12 1999-08-03 Advanced Micro Devices, Inc. Apparatus and method for tracing microprocessor instructions
US6125463A (en) 1997-06-13 2000-09-26 Bull Hn Information Systems Italia S.P.A. Integrated circuit with serial test interface and logic for loading a functional register using said interface
US6102963A (en) 1997-12-29 2000-08-15 Vantis Corporation Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD's
US6097988A (en) 1998-02-10 2000-08-01 Advanced Micro Devices, Inc. Logic system and method employing multiple configurable logic blocks and capable of implementing a state machine using a minimum amount of configurable logic
US6020757A (en) 1998-03-24 2000-02-01 Xilinx, Inc. Slew rate selection circuit for a programmable device
US5968196A (en) 1998-04-21 1999-10-19 Atmel Corporation Configuration control in a programmable logic device using non-volatile elements
US6363501B1 (en) 1998-12-10 2002-03-26 Advanced Micro Devices, Inc. Method and apparatus for saving and loading peripheral device states of a microcontroller via a scan path
US6530050B1 (en) * 1998-12-10 2003-03-04 Advanced Micro Devices Inc. Initializing and saving peripheral device configuration states of a microcontroller using a utility program
US6550031B1 (en) * 1999-10-06 2003-04-15 Advanced Micro Devices Inc. Transparently gathering a chips multiple internal states via scan path and a trigger

Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7076708B2 (en) * 2003-09-25 2006-07-11 International Business Machines Corporation Method and apparatus for diagnosis and behavior modification of an embedded microcontroller
US20050071719A1 (en) * 2003-09-25 2005-03-31 International Business Machines Corporation Method and apparatus for diagnosis and behavior modification of an embedded microcontroller
US7313730B1 (en) * 2004-05-20 2007-12-25 Xilinx, Inc. Configuration logic for embedded software
US20070028080A1 (en) * 2005-07-29 2007-02-01 Hobson Louis B Sleep state resume
US7480790B2 (en) * 2005-07-29 2009-01-20 Hewlett-Packard Development Company, L.P. Sleep state resume
CN100476729C (en) 2006-01-10 2009-04-08 英业达股份有限公司 Method and system configuring data optimal sequential processing on auxiliary equipment of computer
US20100121988A1 (en) * 2008-11-12 2010-05-13 Microchip Technology Incorporated Dynamic state configuration restore
WO2010056727A1 (en) * 2008-11-12 2010-05-20 Microchip Technology Incorporated Dynamic state configuration restore
US8825912B2 (en) 2008-11-12 2014-09-02 Microchip Technology Incorporated Dynamic state configuration restore
US20110029694A1 (en) * 2009-08-03 2011-02-03 Advanced Micro Devices, Inc. Software controlled redirection of configuration address spaces
US8595386B2 (en) * 2009-08-03 2013-11-26 Advanced Micro Devices, Inc. Software controlled redirection of configuration address spaces
US8751760B2 (en) 2009-10-01 2014-06-10 Dell Products L.P. Systems and methods for power state transitioning in an information handling system
US20110082987A1 (en) * 2009-10-01 2011-04-07 Dell Products L.P. Systems and Methods for Power State Transitioning in an Information Handling System
US8799531B2 (en) 2010-11-16 2014-08-05 Canon Kabushiki Kaisha Data transferring apparatus and control method thereof
EP2453362A3 (en) * 2010-11-16 2012-09-19 Canon Kabushiki Kaisha Data transferring apparatus and control method thereof
US20150208124A1 (en) * 2014-01-21 2015-07-23 Mstar Semiconductor, Inc. Smart television system and turn-on and turn-off method thereof
US9554187B2 (en) * 2014-01-21 2017-01-24 Mstar Semiconductor, Inc. Smart television system and turn-on and turn-off method thereof
CN103796066B (en) * 2014-01-21 2017-08-04 上海晨思电子科技有限公司 An intelligent television system and its shutdown and startup method

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