US6823586B2 - Method of mounting a butterfly package on a PCB - Google Patents

Method of mounting a butterfly package on a PCB Download PDF

Info

Publication number
US6823586B2
US6823586B2 US10/445,343 US44534303A US6823586B2 US 6823586 B2 US6823586 B2 US 6823586B2 US 44534303 A US44534303 A US 44534303A US 6823586 B2 US6823586 B2 US 6823586B2
Authority
US
United States
Prior art keywords
pcb
package
leads
butterfly
mounting
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US10/445,343
Other versions
US20030223203A1 (en
Inventor
Eric Lutkiewicz
Bob Van Leeuwen
Peter J. KleinBeernink
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsoft Technology Licensing LLC
Original Assignee
Meriton Networks Inc Canada
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Meriton Networks Inc Canada filed Critical Meriton Networks Inc Canada
Priority to US10/445,343 priority Critical patent/US6823586B2/en
Assigned to MERITON NETWORKS INC. reassignment MERITON NETWORKS INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KLEINBEERNINK, PETER J, LEEUWEN, BOB VAN, LUTKIEWICZ, ERIC
Publication of US20030223203A1 publication Critical patent/US20030223203A1/en
Application granted granted Critical
Publication of US6823586B2 publication Critical patent/US6823586B2/en
Assigned to HORIZON TECHNOLOGY FUNDING COMPANY LLC reassignment HORIZON TECHNOLOGY FUNDING COMPANY LLC SECURITY AGREEMENT Assignors: MERITON NETWORKS INC.
Assigned to XTERA COMMUNICATIONS, INC. reassignment XTERA COMMUNICATIONS, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: MERITON NETWORKS, INC.
Assigned to XTERA COMMUNICATIONS, INC. reassignment XTERA COMMUNICATIONS, INC. RELEASE OF SECURITY INTEREST Assignors: HORIZON TECHNOLOGY FINANCE CORPORATION
Assigned to LINKEDIN CORPORATION reassignment LINKEDIN CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: XTERA COMMUNICATIONS, INC.
Assigned to MICROSOFT TECHNOLOGY LICENSING, LLC reassignment MICROSOFT TECHNOLOGY LICENSING, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: LINKEDIN CORPORATION
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/147—Structural association of two or more printed circuits at least one of the printed circuits being bent or folded, e.g. by using a flexible printed circuit
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3447—Lead-in-hole components
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49151—Assembling terminal to base by deforming or shaping
    • Y10T29/49153—Assembling terminal to base by deforming or shaping with shaping or forcing terminal into base aperture
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49169—Assembling electrical component directly to terminal or elongated conductor

Definitions

  • This invention relates to equipment design and more particularly to a method of mounting an optical or electrical package, such as a Butterfly package, on a substrate such as a printed circuit board.
  • the Butterfly package is a telecommunications industry standard package for lasers, photodiodes, power detectors, etc.
  • the typical method of mounting a butterfly package requires machining a rectangular hole in the Printed Circuit Board (PCB), mounting or attacking the Butterfly package on the PCB, soldering the leads to the edge-launched pads, and mounting any required heatsinks on the secondary side of the PCB.
  • the standard mounting method of a Butterfly package is problematic in several ways:
  • a machined or punched cut-out increases the manufacturing cost of the PCB and reduces the available PCB space for routing signal lines and placing components.
  • the optical fiber associated with optical components in the package is inherently fragile.
  • the transmission characteristics of an optical signal carried by the fiber can be changed or damaged by what is known as “overbending”, i.e. bending a fiber in too small of a radius.
  • the optical fiber is either in the same plane, or very close to being in the same plane as the leads extending from the package.
  • an extension of the cut-out is usually necessary to allow the fiber to be routed without overbending it. This extension of the cut-out further reduces the PCB packaging density.
  • An alternate method of mounting the Butterfly package involves placing the package on the primary side of the board and forming or bending the leads so that they are mounted on a surface mount pad or project through and are attached to holes in the board.
  • the long lead length required to form the leads at 90 degrees increases the series inductance of the leads so much that the component becomes unusable at high frequencies.
  • Butterfly packages are typically used for packaging optical components they can also be used to package electronic circuitry. Mounting a Butterfly package will involve many of the same problems listed above regardless of what the package itself is housing.
  • the invention is not limited to the mounting of Butterfly packages housing optical components, but includes Butterfly packages housing an electronic circuit or electro-optical circuits.
  • the invention concerns a novel method of mounting a Butterfly package on a PCB. Rather than mounting the package in the standard method, requiring a cut-out in the PCB, low component density, and secondary side mounted heatsinks, the invention introduces a mounting technique wherein the Butterfly package is positioned on its side. This side mounting eliminates the need for a PCB cut-out, allows for a primary side mounted heatsink, and increases the PCB density and volumetric packaging efficiency.
  • connections on the now “bottom side” of the Butterfly package are made as through holes in the PCB, while the leads at the now “top side” of the package are connected to the PCB via a flex circuit or ribbon connection.
  • the connections to the through-hole can be designed to support DC currents or high frequency signals.
  • the flex circuit can be specifically designed to carry anything from DC currents to high frequency signals.
  • a method of mounting a package to a printed circuit board comprising: locating the package on the PCB such that leads on the first side of the body are facing the PCB; connecting the leads on the first side to connection points on the PCB; and connecting the leads on the second side of the body to a flexible ribbon connector.
  • PCB printed circuit board
  • FIG. 1A is a side view of a prior art mounting technique with a PCB cut-out
  • FIG. 1B is an end view of the technique shown in FIG. 1A
  • FIG. 2A is a side view of a prior art mounting technique with leads connected to through holes
  • FIG. 2B is an end view of the technique shown in FIG. 2A;
  • FIG. 3A is a side view of the mounting technique according to the present invention.
  • FIG. 3B is an end view of the mounting technique of FIG. 3A.
  • FIG. 4 is an enlarged view of the lead connection according to the mounting connection of FIG. 3 A.
  • FIGS. 1A and 1B for a conventional mounting of the Butterfly package 102 in which an opening 101 is cut in the PCB 105 to make room for the Package 102 .
  • additional clearance must be taken for an optical fiber 103 to exit the Package 102 and not be “overbent”.
  • Any required heatsinking 107 will typically be mounted on the secondary side of the PCB 105 .
  • the leads of the package 106 are mounted on surface mount pads on the PCB 105 . Significant area for the mounting surface to mount components 104 is lost due to the Butterfly package 102 , surface mount leads 106 , the cutout 101 , and the optical fiber 103 .
  • FIGS. 2A and 2B show an alternate prior art Butterfly package mounting technique.
  • the leads 207 are bent 90 degrees and either mounted on surface mount pads or inserted through holes 203 into the PCB 201 . Any required heatsinks 202 can be mounted on the primary side.
  • the optical fiber 204 exits well above the PCB 201 .
  • Surface mount components 206 can be mounted near the Butterfly package 205 on both the primary and secondary side. The length of the leads 207 , with its associated parasitic inductance makes this method unusable at high frequencies such as Gigahertz data rates.
  • FIGS. 3A and 3B illustrate the method of mounting the Butterfly package according to the present invention wherein the package 305 is mounted on its side.
  • the bottom row of pins 302 are mounted through holes in the PCB 304 .
  • the top row of pins 301 is connected to a flex circuit 306 .
  • the other end of the flex circuit is shown as mounted through holes 308 but could also be mounted to surface mount pads.
  • the through hole connections 308 and 309 can be designed to support DC currents or high frequency signals.
  • the flex circuit 306 can be specifically designed to carry DC currents or high frequency signals.
  • the optical fiber 303 is well above the PCB 304 ; so additional clearances are not required as in the conventional method of mounting.
  • any required heatsinks 307 can be mounted on the primary side of the PCB 304 . Note that through careful design of the heatsink only a small amount of PCB area is lost.
  • the cooling fins of the heatsink 307 can be raised above the PCB 304 resulting in useable layout space for surface mount components 310 , 311 .
  • the Butterfly package 305 could be raised up above the PCB 304 to allow surface mount components 310 to be mounted on the primary side of the PCB 304 under the Butterfly package, however high frequency performance will be reduced.
  • this invention increases the density of components 402 , 407 , 409 capable of being placed in close proximity to the point where an individual lead 406 exits the Butterfly package 403 . Specifically the following advantages are gained
  • the lead length which occupies the surface of the PCB 401 is restricted to the size of the hole 405 through which the lead 406 is mounted;
  • Components 402 , 409 , mounted on the primary of the PCB can be mounted very close to the Butterfly package 403 outline
  • Components 407 , mounted on the secondary side of the PCB can be mounted very close to the lead 406 of the Butterfly package 403 ;
  • the distance to the secondary side components 407 may be reduced by reducing the thickness of the PCB 401 to reduce the lead length 406 ;
  • the component height allocation on the primary side of the board may now be more fully utilized by placement of the (relatively) bulky Butterfly package 403 in the air, along with any accompanying heatsink(s) 404 , mechanical components, optical fiber and cable or wire connections etc.;
  • the flexible circuit may be used to carry electrical components above the main circuit board;

Abstract

A method of mounting a package such as a Butterfly package to a printed circuit board in order to make efficient use of the board's real estate is described. According to a preferred embodiment of the invention the package is mounted on its side such that leads of one side (now the bottom) of the butterfly package are connected either directly to surface mount pads on the PCB or project through and connected to through-holes in the PCB. The leads on the other side (now top) are connected to a flex circuit or ribbon cable. A heatsink can be attached to the package without impinging significantly on the PCB layout.

Description

This application claims benefit under 35 USC 119(e) of U.S. Provisional Application No. 60/383,611 filed May 29, 2002.
FIELD OF THE INVENTION
This invention relates to equipment design and more particularly to a method of mounting an optical or electrical package, such as a Butterfly package, on a substrate such as a printed circuit board.
BACKGROUND
As the demand for data bandwidth in communication systems increases, equipment designers and engineers must find ways of increasing the packaging density of the printed circuit boards (PCBs) to achieve more data bandwidth in less space at lower cost. The Butterfly package is a telecommunications industry standard package for lasers, photodiodes, power detectors, etc. The typical method of mounting a butterfly package requires machining a rectangular hole in the Printed Circuit Board (PCB), mounting or attacking the Butterfly package on the PCB, soldering the leads to the edge-launched pads, and mounting any required heatsinks on the secondary side of the PCB. The standard mounting method of a Butterfly package is problematic in several ways:
A machined or punched cut-out increases the manufacturing cost of the PCB and reduces the available PCB space for routing signal lines and placing components.
Typically, there is more volume available for heatsinks on the primary side of the PCB than on the secondary side. Increasing volume on the secondary side will necessitate increasing the inter-card spacing in a system and, consequently, reduce the overall system density.
The typical horizontal mounting of the Butterfly package, i.e. with leads extending parallel to the plane of the PCB, takes up significant board area. This standard mounting orientation reduces the PCB density and therefore the system density.
In a Butterfly package for an optical application the optical fiber associated with optical components in the package is inherently fragile. The transmission characteristics of an optical signal carried by the fiber can be changed or damaged by what is known as “overbending”, i.e. bending a fiber in too small of a radius. For most Butterfly packages, the optical fiber is either in the same plane, or very close to being in the same plane as the leads extending from the package. For Butterfly packages mounted using a cut-out, as described above, an extension of the cut-out is usually necessary to allow the fiber to be routed without overbending it. This extension of the cut-out further reduces the PCB packaging density.
An alternate method of mounting the Butterfly package involves placing the package on the primary side of the board and forming or bending the leads so that they are mounted on a surface mount pad or project through and are attached to holes in the board. The long lead length required to form the leads at 90 degrees increases the series inductance of the leads so much that the component becomes unusable at high frequencies.
While Butterfly packages are typically used for packaging optical components they can also be used to package electronic circuitry. Mounting a Butterfly package will involve many of the same problems listed above regardless of what the package itself is housing. The invention is not limited to the mounting of Butterfly packages housing optical components, but includes Butterfly packages housing an electronic circuit or electro-optical circuits.
SUMMARY OF THE INVENTION
The invention concerns a novel method of mounting a Butterfly package on a PCB. Rather than mounting the package in the standard method, requiring a cut-out in the PCB, low component density, and secondary side mounted heatsinks, the invention introduces a mounting technique wherein the Butterfly package is positioned on its side. This side mounting eliminates the need for a PCB cut-out, allows for a primary side mounted heatsink, and increases the PCB density and volumetric packaging efficiency.
The connections on the now “bottom side” of the Butterfly package are made as through holes in the PCB, while the leads at the now “top side” of the package are connected to the PCB via a flex circuit or ribbon connection. Depending on the application, the connections to the through-hole can be designed to support DC currents or high frequency signals. Similarly the flex circuit can be specifically designed to carry anything from DC currents to high frequency signals.
Therefore, in accordance with the present invention there is provide a method of mounting a package to a printed circuit board (PCB), the package having a body with a plurality of leads extending outwardly from opposed first and second sides of the body, the method comprising: locating the package on the PCB such that leads on the first side of the body are facing the PCB; connecting the leads on the first side to connection points on the PCB; and connecting the leads on the second side of the body to a flexible ribbon connector.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1A is a side view of a prior art mounting technique with a PCB cut-out;
FIG. 1B is an end view of the technique shown in FIG. 1A
FIG. 2A is a side view of a prior art mounting technique with leads connected to through holes;
FIG. 2B is an end view of the technique shown in FIG. 2A;
FIG. 3A is a side view of the mounting technique according to the present invention;
FIG. 3B is an end view of the mounting technique of FIG. 3A; and
FIG. 4 is an enlarged view of the lead connection according to the mounting connection of FIG. 3A.
DETAILED DESCRIPTION OF THE INVENTION
Refer to FIGS. 1A and 1B for a conventional mounting of the Butterfly package 102 in which an opening 101 is cut in the PCB 105 to make room for the Package 102. In the case of an optical package, additional clearance must be taken for an optical fiber 103 to exit the Package 102 and not be “overbent”. Any required heatsinking 107 will typically be mounted on the secondary side of the PCB 105. The leads of the package 106 are mounted on surface mount pads on the PCB 105. Significant area for the mounting surface to mount components 104 is lost due to the Butterfly package 102, surface mount leads 106, the cutout 101, and the optical fiber 103.
FIGS. 2A and 2B show an alternate prior art Butterfly package mounting technique. In this Lead Forming method of mounting the Butterfly package 205, the leads 207 are bent 90 degrees and either mounted on surface mount pads or inserted through holes 203 into the PCB 201. Any required heatsinks 202 can be mounted on the primary side. The optical fiber 204, exits well above the PCB 201. Surface mount components 206 can be mounted near the Butterfly package 205 on both the primary and secondary side. The length of the leads 207, with its associated parasitic inductance makes this method unusable at high frequencies such as Gigahertz data rates.
FIGS. 3A and 3B illustrate the method of mounting the Butterfly package according to the present invention wherein the package 305 is mounted on its side. The bottom row of pins 302 are mounted through holes in the PCB 304. The top row of pins 301 is connected to a flex circuit 306. The other end of the flex circuit is shown as mounted through holes 308 but could also be mounted to surface mount pads. Depending on the needed application, the through hole connections 308 and 309 can be designed to support DC currents or high frequency signals. Similarly the flex circuit 306 can be specifically designed to carry DC currents or high frequency signals. In the new mounting method, the optical fiber 303 is well above the PCB 304; so additional clearances are not required as in the conventional method of mounting. Any required heatsinks 307 can be mounted on the primary side of the PCB 304. Note that through careful design of the heatsink only a small amount of PCB area is lost. The cooling fins of the heatsink 307 can be raised above the PCB 304 resulting in useable layout space for surface mount components 310, 311. If desired, the Butterfly package 305 could be raised up above the PCB 304 to allow surface mount components 310 to be mounted on the primary side of the PCB 304 under the Butterfly package, however high frequency performance will be reduced.
Refer to FIG. 4 for greater detail of the through hole mounting of FIGS. 3A and 3B. With good design, this invention increases the density of components 402, 407, 409 capable of being placed in close proximity to the point where an individual lead 406 exits the Butterfly package 403. Specifically the following advantages are gained
The lead length which occupies the surface of the PCB 401 is restricted to the size of the hole 405 through which the lead 406 is mounted;
The attachment of the lead 406 to other internal layers 408 of the PCB 401, including the secondary side of the PCB, is accomplished by the same hole 405 through which the lead 406 is mounted;
Components 402,409, mounted on the primary of the PCB can be mounted very close to the Butterfly package 403 outline
Components 407, mounted on the secondary side of the PCB can be mounted very close to the lead 406 of the Butterfly package 403;
The distance to the secondary side components 407 may be reduced by reducing the thickness of the PCB 401 to reduce the lead length 406;
The component height allocation on the primary side of the board may now be more fully utilized by placement of the (relatively) bulky Butterfly package 403 in the air, along with any accompanying heatsink(s) 404, mechanical components, optical fiber and cable or wire connections etc.;
The flexible circuit may be used to carry electrical components above the main circuit board;
Although a particular embodiment of the invention has been described and illustrated it will be apparent to one skilled in the art that numerous changes can be made without departing from the basic concept. It is to be understood, however, that such changes will fall within the full scope of the invention as defined by the appended claims.

Claims (15)

We claim:
1. A method of mounting a package to a printed circuit board (PCB), the package having a body with a plurality of leads extending outwardly from opposed first and second sides of the body, the method comprising:
locating the package on the PCB such that leads on the first side of the body are directed toward the PCB;
connecting the leads on the first side to connection points on the PCB; and
connecting the leads on the second side of the body to a flexible ribbon connector, wherein the flexible ribbon connector is connected to through-holes in the PCB.
2. The method as defined in claim 1 wherein the package is a butterfly package for housing optical components.
3. The method as defined in claim 1 wherein the package is a butterfly package for housing electrical components.
4. The method as defined in claim 1 wherein a heatsink is attached to the package.
5. The method as defined in claim 4 wherein the package is in contact with the PCB.
6. The method as defined in claim 4 wherein the package is located above a primary surface of the PCB.
7. The method as defined in claim 5 wherein cooling fins for the heat sink are located above a primary surface of the PCB.
8. The method as defined in claim 1 wherein the leads on the first side of the package are connected to surface mount pads on the PCB.
9. The method as defined in claim 1 wherein the leads on the first side of the package are inserted through and connected to holes in the PCB. above a primary surface of the PCB.
10. The method as defined in claim 9 wherein the PCB is single layered and the leads are connected to metalized areas on at least one outer layer.
11. The method as defined in claim 9 wherein the PCB is multilayered and the leads are connected to metalized areas on at least one of an outer layer or internal layer.
12. A method of mounting butterfly packages, each having a body and multiple leads extending outwardly from opposite sides thereof, on a printed circuit board (PCB) to increase component density, the PCB having internal layers, the method comprising:
attaching the multiple leads on the butterfly package to a first side of the PCB on which conducting paths have been formed on at least one of primary, secondary or internal layers;
attaching a flexible ribbon connector, to the multiple leads on a second and opposite side of the butterfly package; and
connecting the flexible ribbon connectors to through holes in the PCB.
13. The method as defined in claim 12 wherein the leads on said first side of the butterfly package are kept to a minimum length for high frequency applications.
14. The method as defined in claim 12 wherein a heat sink is attached to the butterfly package such that it is raised above the surface of the PCB.
15. The method as defined in claim 12 wherein leads on said first side of the Butterfly package are long enough to permit the package to be located above the PCB leaving clearance therebetween for other components.
US10/445,343 2002-05-29 2003-05-27 Method of mounting a butterfly package on a PCB Expired - Lifetime US6823586B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US10/445,343 US6823586B2 (en) 2002-05-29 2003-05-27 Method of mounting a butterfly package on a PCB

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US38361102P 2002-05-29 2002-05-29
US10/445,343 US6823586B2 (en) 2002-05-29 2003-05-27 Method of mounting a butterfly package on a PCB

Publications (2)

Publication Number Publication Date
US20030223203A1 US20030223203A1 (en) 2003-12-04
US6823586B2 true US6823586B2 (en) 2004-11-30

Family

ID=29587017

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/445,343 Expired - Lifetime US6823586B2 (en) 2002-05-29 2003-05-27 Method of mounting a butterfly package on a PCB

Country Status (1)

Country Link
US (1) US6823586B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7471520B2 (en) * 2005-03-10 2008-12-30 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Impedance matching external component connections with uncompensated leads
CN100531516C (en) * 2005-07-22 2009-08-19 鸿富锦精密工业（深圳）有限公司 Printing circuit board

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4812949A (en) * 1986-03-28 1989-03-14 Bull, S.A. Method of and apparatus for mounting an IC chip
US5117281A (en) * 1989-10-23 1992-05-26 Nec Corporation Semiconductor device having a heat-sink attached thereto
US5149958A (en) * 1990-12-12 1992-09-22 Eastman Kodak Company Optoelectronic device component package
US5184211A (en) * 1988-03-01 1993-02-02 Digital Equipment Corporation Apparatus for packaging and cooling integrated circuit chips
US5410451A (en) * 1993-12-20 1995-04-25 Lsi Logic Corporation Location and standoff pins for chip on tape
US6035523A (en) * 1995-06-16 2000-03-14 Apple Computer, Inc. Method and apparatus for supporting a component on a substrate

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4812949A (en) * 1986-03-28 1989-03-14 Bull, S.A. Method of and apparatus for mounting an IC chip
US5184211A (en) * 1988-03-01 1993-02-02 Digital Equipment Corporation Apparatus for packaging and cooling integrated circuit chips
US5117281A (en) * 1989-10-23 1992-05-26 Nec Corporation Semiconductor device having a heat-sink attached thereto
US5149958A (en) * 1990-12-12 1992-09-22 Eastman Kodak Company Optoelectronic device component package
US5410451A (en) * 1993-12-20 1995-04-25 Lsi Logic Corporation Location and standoff pins for chip on tape
US6035523A (en) * 1995-06-16 2000-03-14 Apple Computer, Inc. Method and apparatus for supporting a component on a substrate

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
Bailey, Chris, "Modelling the effect of temperature on product reliability", 19th IEEE Semi-Therm Sypmosium, 2003.

Also Published As

Publication number Publication date
US20030223203A1 (en) 2003-12-04

Similar Documents

Publication Publication Date Title
JP4628714B2 (en) Circuit interconnection structure
US5949657A (en) Bottom or top jumpered foldable electronic assembly
US7606050B2 (en) Compact module system and method
AU690401B2 (en) Electronic circuit structure
US6609914B2 (en) High speed and density circular connector for board-to-board interconnection systems
US6685364B1 (en) Enhanced folded flexible cable packaging for use in optical transceivers
CN101180924B (en) Inductor
US6487083B1 (en) Multilayer circuit board
US20080037238A1 (en) Structure for electromagnetically shielding a substrate
EP0600590A1 (en) Cooling electronic circuit assemblies
KR20080009317A (en) High capacity thin module system and method
KR100763059B1 (en) Power delivery apparatus, systems, and methods
US11096290B2 (en) Printed circuit board with edge soldering for high-density packages and assemblies
JP2004063861A (en) Optical communication apparatus, optical transmitter, optical transceiver, and optical transmission system
US6823586B2 (en) Method of mounting a butterfly package on a PCB
JPS634712B2 (en)
US6445590B1 (en) Capacitor for DRAM connector
JP3012184B2 (en) Mounting device
US6924439B1 (en) Signal conducting applique and method for use with printed circuit board
US6542376B1 (en) High density packaging of electronic components
US6137061A (en) Reduction of parasitic through hole via capacitance in multilayer printed circuit boards
KR100276858B1 (en) Electronic package with enhanced pad design
US20230197635A1 (en) Stiffener ring for packages with micro-cable/optical connectors
JPH0430497A (en) Printed wiring board unit
JPH098462A (en) Multilayer printed-wiring board module

Legal Events

Date Code Title Description
AS Assignment

Owner name: MERITON NETWORKS INC., CANADA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LUTKIEWICZ, ERIC;LEEUWEN, BOB VAN;KLEINBEERNINK, PETER J;REEL/FRAME:014126/0273

Effective date: 20030522

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: HORIZON TECHNOLOGY FUNDING COMPANY LLC,CONNECTICUT

Free format text: SECURITY AGREEMENT;ASSIGNOR:MERITON NETWORKS INC.;REEL/FRAME:018934/0670

Effective date: 20061218

Owner name: HORIZON TECHNOLOGY FUNDING COMPANY LLC, CONNECTICU

Free format text: SECURITY AGREEMENT;ASSIGNOR:MERITON NETWORKS INC.;REEL/FRAME:018934/0670

Effective date: 20061218

FPAY Fee payment

Year of fee payment: 4

SULP Surcharge for late payment
AS Assignment

Owner name: XTERA COMMUNICATIONS, INC., TEXAS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MERITON NETWORKS, INC.;REEL/FRAME:028541/0891

Effective date: 20120501

REMI Maintenance fee reminder mailed
FPAY Fee payment

Year of fee payment: 8

SULP Surcharge for late payment

Year of fee payment: 7

AS Assignment

Owner name: XTERA COMMUNICATIONS, INC., TEXAS

Free format text: RELEASE OF SECURITY INTEREST;ASSIGNOR:HORIZON TECHNOLOGY FINANCE CORPORATION;REEL/FRAME:033076/0377

Effective date: 20140523

FEPP Fee payment procedure

Free format text: PAT HOLDER NO LONGER CLAIMS SMALL ENTITY STATUS, ENTITY STATUS SET TO UNDISCOUNTED (ORIGINAL EVENT CODE: STOL); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: LINKEDIN CORPORATION, CALIFORNIA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:XTERA COMMUNICATIONS, INC.;REEL/FRAME:038979/0876

Effective date: 20140527

AS Assignment

Owner name: MICROSOFT TECHNOLOGY LICENSING, LLC, WASHINGTON

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LINKEDIN CORPORATION;REEL/FRAME:044746/0001

Effective date: 20171018