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US6820216B2 - Method and apparatus for accelerating fault handling - Google Patents

Method and apparatus for accelerating fault handling Download PDF

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Publication number
US6820216B2
US6820216B2 US09822929 US82292901A US6820216B2 US 6820216 B2 US6820216 B2 US 6820216B2 US 09822929 US09822929 US 09822929 US 82292901 A US82292901 A US 82292901A US 6820216 B2 US6820216 B2 US 6820216B2
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sequence
processor
state
instructions
point
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US20020144179A1 (en )
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Robert Cmelik
Malcolm Wing
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Intellectual Ventures Holding 81 LLC
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Transmeta Inc
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/38Concurrent instruction execution, e.g. pipeline, look ahead
    • G06F9/3861Recovery, e.g. branch miss-prediction, exception handling
    • G06F9/3863Recovery, e.g. branch miss-prediction, exception handling using multiple copies of the architectural state, e.g. shadow registers
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F9/00Arrangements for programme control, e.g. control unit
    • G06F9/06Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
    • G06F9/30Arrangements for executing machine-instructions, e.g. instruction decode
    • G06F9/30003Arrangements for executing specific machine instructions
    • G06F9/30076Arrangements for executing specific machine instructions to perform miscellaneous control operations, e.g. NOP
    • G06F9/30087Synchronisation or serialisation instructions
    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRICAL DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14Error detection or correction of the data by redundancy in operation
    • G06F11/1402Saving, restoring, recovering or retrying
    • G06F11/1405Saving, restoring, recovering or retrying at machine instruction level

Abstract

A process which stores an indication of a next instruction in a sequence of instructions which is to be executed whenever during execution of instructions of the sequence it is apparent that state of the process is consistent, and refers to the stored indication to determine an instruction at which to begin re-execution of the sequence after executing a fault handler initiated by an interrupt to the sequence.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to computer systems and, more particularly, to a method and apparatus by which a computer processor may accelerate fault handling.

2. History of the Prior Art

A computer processor continually encounters circumstances in which it must halt the processing of a particular sequence of instructions to attend to some occurrence not usually encountered in the sequence. These occurrences are variously referred to as errors, exceptions, faults, and other terms which are often defined differently by different parties and under different circumstances. In general, such occurrences all require the processor to halt the sequence of instructions it is presently processing and take some action outside of the execution of the interrupted sequence.

As one example, an error in executing a particular sequence may require that the processor stop the execution, discard the results generated to that point, and move back to an earlier point in the sequence to begin reexecution. On the other hand, an interrupt may be generated by a modem signaling that data is arriving from circuitry external to the computer that is executing the sequence. Such an interrupt may require the processor to stop execution of the sequence, receive the externally-provided data, and then return to executing the sequence at the point at which it was stopped. There are many other situations in which a processor must halt its processing in order to attend to matters outside of the execution of an executing sequence, and all are subject to a number of the same difficulties. Because there are many different situations, in this specification, the use of each of the terms fault, exception, error, and the like is intended to encompass all of these terms except where otherwise stated or made obvious from the text.

The typical method of handling exceptions is to interrupt the sequence of instructions being executed, save enough information about the sequence and its execution up to its interruption to be able to return to the sequence and continue its execution, then transfer control of the processor to a software sequence of instructions for handling the exception (usually referred to as an exception handler), execute the exception handler to handle whatever needs be done to take care of the exception, retrieve the information about the interrupted sequence and its execution up to its interruption, and recommence execution of the interrupted sequence of instructions. Of course, in many situations, the exception will be such that the interrupted sequence cannot or should not continue so that the processor will be directed to some other sequence of instructions by the handler.

In those situations in which the proper action for the processor is to return to the interrupted sequence and continue its execution, it is necessary for the processor to understand at what point the interruption occurred so that execution may recommence at the proper point in the sequence.

In many situations, even though a typical processor will have stored information sufficient to be able return to the point of interruption, it may not know the exact point in the sequence to which it should return and will have to compute this point. For example, when a process is interrupted in order to allow another process to execute, then it is necessary for the interrupt to take effect at a point at which consistent state exists. However, a processor executing a speculative sequence of instructions will probably not commit to memory information generated by the speculative sequence until the sequence is determined to be the proper sequence for execution and has executed without error. Thus, if execution of a speculative sequence is interrupted, the interrupt may not occur at a point at which consistent state exists because information from the interrupted sequence has not yet been stored. Thus, the point at which the sequence is actually interrupted might not be a point at which consistent state exists and at which a new sequence may begin. Although the processor knows where the interrupt occurred, the processor may have insufficient information to immediately return to a point at which consistent state exists. In such a case it is necessary for the processor to use what data it has to determine a correct point to recommence execution. A significant amount of time and storage is often required to accomplish this determination, especially where subroutines are involved in the interrupted sequence.

It is desirable to provide circuitry and processes by which a processor may determine a point to recommence execution of an interrupted sequence of instructions more quickly than by using prior art techniques.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to enhance the operation of a microprocessor by providing improved methods and circuitry for accomplishing fault handling.

This and other objects of the present invention are realized by a process which stores an indication of a next instruction in a sequence of instructions which is to be executed whenever during execution of instructions of the sequence it is apparent that state of the process is consistent, and refers to the stored indication to determine an instruction to which to return from handling a fault.

These and other objects and features of the invention will be better understood by reference to the detailed description which follows taken together with the drawings in which like elements are referred to by like designations throughout the several views.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating circuit elements utilized by the methods of FIGS. 2 and 3.

FIG. 2 is a flow chart illustrating a general method in accordance with the invention.

FIG. 3 is a flow chart illustrating a particular method in accordance with the invention.

DETAILED DESCRIPTION

The present invention is illustrated in FIG. 1. The invention includes a processor 10 that utilizes a register 12 (or other storage media) to record the address of the next instruction that is designated to be executed whenever the operating system has determined that state of the system is consistent. By recording the address of the next instruction in line to be executed at a point at which state becomes consistent, the proper point for resuming execution of a sequence of instructions which is later interrupted can be determined without computation by simply reading the address from the register 12. If the sequence which is interrupted is a speculative sequence for which system state is not consistent at the point at which the sequence is interrupted, then moving back to a point at which system state was consistent and referring to the instruction at the address held by the register 12 allows the interrupted sequence to be resumed expeditiously at the proper point without computing this point from the address held in a program counter 14 at the point of the interrupt.

The present invention is especially useful when utilized with a new processor designed by Transmeta Corporation of Santa Clara, Calif. The new microprocessor combines a simple but fast host processor (called a “morph host”) and software (referred to as “code morphing software”) to execute application programs designed for a processor (the “target processor”) having an instruction set different than the morph host processor. The morph host processor executes the code morphing software which translates the target programs dynamically into morph host processor instructions able to accomplish the purpose of the original target software. As the target instructions are translated, the new host instructions are both executed and stored in a translation buffer where they may be accessed without further translation. Although the initial translation of a program is slow, once translated, many of the steps normally required by prior art hardware to execute a program are eliminated.

In order to be able to execute programs designed for other processors at a rapid rate, the morph host processor includes a number of hardware enhancements. One of these enhancements is a gated store buffer which holds memory stores generated as sequences of morph host instructions are executed. A second enhancement is a set of host registers which store state of the target processor at the beginning of any sequence of target instructions being translated. If the translated morph host instructions execute without raising an exception, the target state at the beginning of the sequence of instructions is updated to the target state at the point at which the sequence completed and the memory stores are committed to memory.

If an exception occurs during the execution of the sequence of host instructions which have been translated, processing stops; and the entire operation may be returned or rolled back to the beginning of the sequence of target instructions at which known consistent state of the target processor exists. This allows very rapid and accurate handling of exceptions while dynamically translating and executing instructions. The new processor is described in detail in U.S. Pat. No. 6,031,992; Cmelik et al.

Since the new processor is continuously updating system state to be consistent after executing sequences of instructions, it is quite simple for this processor to store the address of the next instruction which is to be executed in the register 11 at the point at which state is brought up to date (or “committed” in the terms of the above-mentioned patent). In order to accomplish this, the system software causes the processor to respond to a “commit” instruction by storing the address of the next instruction following the commit in the register 12. Normally, such an instruction merely follows in the sequence. However, in one embodiment, if the next instruction is a branch instruction, then the address of the target of the branch instruction is stored in the register 12.

The invention allows the above-described processor to handle faults at any point during sequences of instructions without first determining whether state is consistent at the point of the interrupt. Even though a fault happens at a time when state is inconsistent, after the fault handler completes, the software provides an immediate rollback to a consistent point. Thus, even though state is inconsistent at the point of the interrupt and the address held by the processor program counter 14 where the interrupt occurred points to the wrong address for recommencing execution of the interrupted sequence, after the rollback, state has become consistent and the address stored in the register 12 whenever a commit occurs is the address at which the processor should start the interrupted program after the interrupt has been handled.

This ability to immediately determine the correct address of the next instruction upon a return from interrupt accelerates execution of fault handling processes and processor speed. For example, this ability is especially useful in handling direct memory access operations initiated by sources outside the particular computer. Since such accesses are safe only where system state is consistent, the ability to guarantee consistent system state after each interrupt and an immediate return address following the interrupt are quite valuable.

Although the invention is especially useful when used with the above-described processor, it would appear that any processor (or processor and software) which affirmatively determines or recognizes that system state is consistent might utilize the invention to accelerate the handling of faults in a manner within the scope of this invention. It should be noted that although the above-described processor typically utilizes software to make the determination that state is consistent, other means such as hardware means can be utilized to accomplish the same purpose. Similarly, although the above-described processor typically utilizes software to store the address of the next instruction which is to be executed in the register 11 at the point at which state is brought up to date, other means such as hardware means can be utilized to accomplish the same purpose. The process of this invention is much easier and faster than trying to go back through the translation to determine the proper point to restart.

Although the present invention has been described in terms of a preferred embodiment, it will be appreciated that various modifications and alterations might be made by those skilled in the art without departing from the spirit and scope of the invention. The invention should therefore be measured in terms of the claims which follow.

Claims (10)

What is claimed is:
1. A method for accelerating the handling of faults by a computer processor comprising the steps of:
translating target processor instructions into a sequence of instructions;
executing said sequence of instructions;
storing an indication of a next instruction in said sequence of instructions which is to be executed whenever during execution of instructions of a sequence it is apparent that state of process is consistent, wherein said indication is stored in response to a commit instruction, and
referring to the stored indication to determine an instruction at which to begin re-execution of the sequence after executing a fault handler initiated by an interrupt to the sequence.
2. A method as claimed in claim 1 further comprising the step of detecting when state of the process is consistent.
3. A method as claimed in claim 1 in which the step of storing an indication of a next instruction in a sequence of instructions which is to be executed whenever during execution of instructions of the sequence it is apparent that state of the process is consistent is accomplished by a software process executing on the computer processor.
4. A method as claimed in claim 1 in which the step of referring to the stored indication to determine an instruction at which to begin re-execution of the sequence after executing a fault handler initiated by an interrupt to the sequence is accomplished by a software process executing on the computer processor.
5. A processor comprising a first storage media for retaining an indication of a next instruction in a sequence of instructions, wherein said sequence of instructions include translated target processor instructions, and a second storage media for retaining an indication of a next instruction to be executed whenever state of the processor becomes consistent, wherein said indication is stored in response to a commit instruction.
6. A processor as claimed in claim 5 further comprising means for detecting consistency of state of a processor, and means for storing an indication of a next instruction to be executed in the second storage media whenever state of the processor becomes consistent.
7. A processor as claimed in claim 6 in which the means for detecting consistency of state of a processor includes software executing on the processor.
8. A processor as claimed in claim 6 in which the means for storing an indication of a next instruction to be executed in the second storage media whenever state of the processor becomes consistent includes software executing on the processor.
9. A processor as claimed in claim 6 in which the means for detecting consistency of state of a processor includes hardware circuitry.
10. A processor as claimed in claim 6 in which the means for storing an indication of a next instruction to be executed in the second storage media whenever state of the processor becomes consistent includes hardware circuitry.
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US20050172077A1 (en) * 2002-03-22 2005-08-04 Microsoft Corporation Multi-level persisted template caching
US20060031706A1 (en) * 2002-01-24 2006-02-09 Nick Ramirez Architecture for high availability using system management mode driven monitoring and communications
US20080126883A1 (en) * 2006-07-27 2008-05-29 Paul Caprioli Method and apparatus for reporting failure conditions during transactional execution
US7640450B1 (en) 2001-03-30 2009-12-29 Anvin H Peter Method and apparatus for handling nested faults
US20110126049A1 (en) * 2009-11-24 2011-05-26 Honeywell International Inc. Architecture and method for hardware-assisted processor checkpointing and rollback
US20110125968A1 (en) * 2009-11-24 2011-05-26 Honeywell International Inc. Architecture and method for cache-based checkpointing and rollback

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US7263631B2 (en) * 2004-08-13 2007-08-28 Seakr Engineering, Incorporated Soft error detection and recovery
US20170277539A1 (en) * 2016-03-24 2017-09-28 Imagination Technologies Limited Exception handling in processor using branch delay slot instruction set architecture

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Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7640450B1 (en) 2001-03-30 2009-12-29 Anvin H Peter Method and apparatus for handling nested faults
US20060031706A1 (en) * 2002-01-24 2006-02-09 Nick Ramirez Architecture for high availability using system management mode driven monitoring and communications
US7434085B2 (en) * 2002-01-24 2008-10-07 Intel Corporation Architecture for high availability using system management mode driven monitoring and communications
US20050172077A1 (en) * 2002-03-22 2005-08-04 Microsoft Corporation Multi-level persisted template caching
US20080126883A1 (en) * 2006-07-27 2008-05-29 Paul Caprioli Method and apparatus for reporting failure conditions during transactional execution
US7617421B2 (en) * 2006-07-27 2009-11-10 Sun Microsystems, Inc. Method and apparatus for reporting failure conditions during transactional execution
US20110126049A1 (en) * 2009-11-24 2011-05-26 Honeywell International Inc. Architecture and method for hardware-assisted processor checkpointing and rollback
US20110125968A1 (en) * 2009-11-24 2011-05-26 Honeywell International Inc. Architecture and method for cache-based checkpointing and rollback
US8108721B2 (en) * 2009-11-24 2012-01-31 Honeywell International Inc. Architecture and method for hardware-assisted processor checkpointing and rollback
US8458403B2 (en) 2009-11-24 2013-06-04 Honeywell International Inc. Architecture and method for cache-based checkpointing and rollback

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