US6768961B2 - System and method for analyzing error information from a semiconductor fabrication process - Google Patents
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- US6768961B2 US6768961B2 US09/952,848 US95284801A US6768961B2 US 6768961 B2 US6768961 B2 US 6768961B2 US 95284801 A US95284801 A US 95284801A US 6768961 B2 US6768961 B2 US 6768961B2
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- 230000009897 systematic effect Effects 0.000 claims abstract description 64
- 238000005192 partition Methods 0.000 claims abstract description 5
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- 238000000546 chi-square test Methods 0.000 claims description 12
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- 229910052710 silicon Inorganic materials 0.000 description 2
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- 238000000528 statistical test Methods 0.000 description 2
- 239000007795 chemical reaction product Substances 0.000 description 1
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- 238000013461 design Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
- H01L22/20—Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2894—Aspects of quality control [QC]
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- the present invention generally relates to a system and method for analyzing error information from a semiconductor fabrication process, and more particularly, to a system and method which accurately identifies systematic, repeated and random errors from wafer map data acquired during a semiconductor fabrication process.
- a large fab may contain hundreds of automated tools that cooperatively work to convert circular silicon “wafers” (each consisting of dozens, hundreds, and even potentially thousands of chips) into functioning products.
- a “recipe” determines which operations these various tools perform, and is based upon the end-product that is to be manufactured. Recipes can be quite complicated, involving the use of hundreds of tools, each conducting specialized operations on the wafer, in a specific order, over a period of weeks or even months.
- One of the challenges in these fabs is to control the manufacturing equipment and tools in a manner that minimizes variations and defects in the products being produced.
- the manufacturing equipment and tools used within these fabs have a multitude of parameters which must be examined and controlled in order to minimize variations and errors.
- a stepper images portions of the design onto the wafer multiple times, but does so in a step-wise fashion over groups of chips.
- the grouping of chips used is determined by the “reticle.” For example, a reticle layout may specify two rows of two columns of chips (a “two-by-two reticle layout”).
- the overall yield of a wafer may be divided into three unique yield categories.
- systematic yield the substandard or failing chips result from systematic factors or errors in the fab.
- Systematic errors can be desirably controlled, reduced and/or substantially eliminated once known.
- An example of a systematic error would be a tool that is not functioning properly.
- random yield the substandard or failing chips are caused by random factors or errors in the fab.
- An example of a random error would be dust that settled on the wafer as it was being fabricated.
- repeated or “reticle” yield the substandard or failing chips result from repeated factors or errors in the fab (e.g., the chips fail in a pattern consistent with the reticle layout).
- Improving yield is a major objective of the semiconductor industry and has a direct economic impact to the semiconductor industry.
- a higher yield translates into more devices that may be sold by the manufacturer.
- semiconductor manufacturing companies have implemented systems for collecting and analyzing error data. These prior systems often employ images and image processing algorithms and devices to document and/or identify errors within a wafer and to take action to prevent such errors from occurring in subsequent fabrications.
- a wafer map provides a display of the chips on a wafer with each chip marked to indicate a result from the production process. For example, chips that pass a certain benchmark may be colored blue, whereas the ones that fail may be colored red.
- the pass/fail information conveyed by such a wafer map is a way of recording the yield of the wafer.
- the present invention provides many advantages over conventional error information analysis methods and systems.
- the present invention accurately classifies chip errors on a wafer map in a plurality of categories, such as systematic, random and repeated failures.
- the present invention allows a fabrication engineer or professional to provide corrective action which is purposely designed to overcome the specific type of errors or failures encountered.
- a system for analyzing error information describing a plurality of failing chips on a semiconductor wafer.
- the system includes a controller which is adapted to receive the error information and to classify each of the plurality of failing chips in a unique one of a plurality of error categories.
- a system for analyzing error information describing a plurality of failing chips on a semiconductor wafer.
- the system includes an input assembly which is adapted to accept and communicate the error information in the form of a wafer map; and a controller which is communicatively coupled to the input assembly and which receives the wafer map from the input assembly.
- the controller is adapted to classify each of the failing chips in a unique one of the group of categories including systematic failures, repeated failures and random failures, based upon the wafer map.
- a method for analyzing error information from a semiconductor manufacturing process includes the steps of: receiving wafer map data identifying a plurality of failing chips on a semiconductor wafer; and classifying each of the failing chips in a unique one of the group of categories including systematic errors, repeated errors, and random errors.
- FIG. 1 is a block diagram illustrating one non-limiting embodiment of a system for analyzing error information acquired during a semiconductor fabrication process which is made in accordance with a preferred embodiment of the present invention.
- FIG. 2 is a block diagram illustrating the broad functionality employed by the system shown in FIG. 1 .
- FIG. 3 is an exemplary illustration of a wafer map may which may be used by the system and method of the preferred embodiment of the invention.
- FIG. 4 is an exemplary illustration of a three-by-three neighborhood for a chip on a silicon wafer.
- FIG. 5 is an exemplary illustration of a wafer map identifying the systematic failures of the wafer shown in FIG. 3 .
- FIG. 6 is an exemplary illustration of a wafer map identifying the repeated failures of the wafer shown in FIG. 3 .
- FIG. 7 is an exemplary illustration of a wafer map identifying the random failures of the wafer shown in FIG. 3 .
- FIG. 8 is an exemplary illustration of a wafer map with systematic failing chips partitioned into a pair of spatial clusters.
- the present invention provides a system and method for analyzing error information from a semiconductor fabrication process, and which categorizes the errors present on a wafer map as systematic, repeated or random failures.
- the present invention may be created by and/or constitute or comprise software which resides within a conventional computer system.
- the present invention may be implemented in hardware or may incorporate other modules or functionality not described herein.
- FIG. 1 shows a system 10 in accordance with the present invention, and which is implemented on a computer system.
- system 10 may represent a conventional and commercially available computer system, manufacturing execution system, or an independent microprocessor-based system built specifically for use with the present invention.
- System 10 comprises a control and memory unit 12 , a user input assembly 14 , a display unit 16 , and an input/output unit 18 .
- Control and memory unit 12 may be a conventional and commercially available processor-based system including a microprocessor or microcontroller and both volatile and non-volatile memory.
- User input assembly 14 may be one or more conventional and commercially available input devices such as and without limitation a keyboard, mouse, touch pad, light pen, and/or any other conventional and commercially available devices suitable to permit a user to input data into system 10 (e.g., into control and memory unit 12 ).
- Input/output unit 18 may be a suitable and commercially available device or a combination of devices adapted to provide data to, and access data from, control and memory unit 12 , and may comprise without limitation one or more conventional disk drives, ports and communication devices for transferring data over a local or global computer network.
- Input/output unit 18 may further include other conventional peripheral devices such as printers, scanners and the like.
- Display unit 16 may be a conventional and commercially available output display device such as and without limitation a computer monitor, a flat panel display or other conventional display device which is suitable to display output generated by computer system 10 .
- the present invention may comprise software or firmware contained on a storage device, mainframe computer, or network server which may be accessed and loaded into control and memory unit 12 by way of input/output unit 18 .
- the present invention may be stored within the permanent or non-volatile memory of unit 12 .
- FIG. 2 is a block diagram 20 illustrating the broad functionality, strategy or method used by the system 10 to extract various error information from wafer map data in a semiconductor fabrication process.
- system 10 is effective to classify errors from a wafer map in one of the following categories: systematic errors, repeated or reticle errors and random errors.
- the strategy 20 is briefly executed as follows: system 10 receives error information regarding a semiconductor fabrication process in the form of wafer maps in functional block or step 22 ; system 10 identifies and extracts data representing systematic errors in functional block or step 24 ; system 10 identifies and extracts data representing reticle and random errors in functional block or step 26 ; and system 10 partitions systematic failing chips into spatial clusters in functional block or step 28 .
- system 10 receives error information regarding a semiconductor fabrication process in the form of wafer maps in functional block or step 22 ; system 10 identifies and extracts data representing systematic errors in functional block or step 24 ; system 10 identifies and extracts data representing reticle and random errors in functional block or step 26 ; and system 10
- system 10 receives error information regarding the semiconductor manufacturing process in the form of wafer maps.
- a wafer map illustrates the position of each of the chips on a particular wafer, with each of the chips marked to indicate whether it has “passed” (e.g., the chip functions according to various predetermined benchmarks) or “failed” (e.g., the chip does not function according to one or more predetermined benchmarks).
- a non-limiting example of a wafer map 40 which may be used within the present invention, is illustrated in FIG. 3 .
- the wafer map 40 illustrates a plurality of chips 42 arranged in a two-dimensional layout representative of the wafer on which the chips are formed.
- the reticles used on the wafer are superimposed on the map 40 .
- the reticle zones are defined as a two-by-two area.
- the upper right-hand corner 44 of each reticle is darkened to differentiate between each reticle on the map 40 .
- the one or more failing chips 46 on the map 40 are labeled with an “X”. While for the purposes of this illustration failing chips 46 have been labeled with an “X”, it should be appreciated that wafer maps used and generated by system 10 may utilize any method of marking passing and failing chips which is suitable for image recognition purposes, such as assigning specific colors to passing and failing chips.
- System 10 may receive the wafer map data in any suitable manner.
- the wafer maps 40 may be received by system 10 over a communications network by use of input/output unit 18 , or may be entered into system 10 by a user (e.g., a manufacturing engineer) through user input assembly 14 .
- system 10 may receive raw data describing results of post-processing tests performed on the wafers and/or data identifying particular chips on the wafers that have failed certain performance benchmarks.
- system 10 may generate its own wafer maps in a conventional manner, based upon the raw data.
- system 10 In separating or partitioning the systematic failures from other failures (e.g., reticle failures and random failures), system 10 implements a strategy that does not examine the chips on a “one-at-a-time” basis, but rather views each chip in the context of how the chips surrounding it exhibit pass/fail patterns. This technique is commonly referred to as an image smoothing process.
- the system 10 examines all chips within a three-by-three neighborhood of a chip i. In each three-by-three neighborhood there are potentially twenty-four chips surrounding a chip i (not including the chip i).
- An example of a three-by-three neighborhood 50 for a chip 52 is illustrated in FIG. 4 . It should be appreciated that chips in the center of a wafer will most likely have twenty-four chips surrounding them in their respective three-by-three neighborhoods, while chips at the edges of a wafer will not.
- the chip 48 illustrated in FIG. 3 only has twelve such neighbors.
- system 10 defines a scaled binomial random variable function, y i , for each chip i.
- n i denotes the number of neighbors in a three-by-three neighborhood
- Equation (1) may be modified so that a factor of two is applied in the summation for chips directly adjacent to chip i, and a factor of one otherwise, so long as the denominator is adjusted so that each y i still ranges from zero to one.
- each z i also ranges from zero to one.
- x i 0 if chip i is a passing chip
- x i 1 if chip i is a failing chip
- x j 0 if chip j is a passing chip
- x j 1 if chip j is a failing chip
- w ij 1 if chip i is either vertically, horizontally or diagonally adjacent to chip j (i.e., adjacent in the sense of the possible moves of a king on a chessboard), and w ij is 0 otherwise.
- Approximate distributions of the test statistic W may be calculated in a conventional manner when the number of chips on the wafer map is large. However, these distributions are for testing the statistical null hypothesis H 0 : The chips are distributed randomly versus the alternative hypothesis H 1 : The chips are not distributed randomly. In applying the test of spatial randomness for the purposes of determining systematic failures, the alternative hypothesis is H 2 : The chips are distributed randomly except for various clusters of chips that are pre-specified (e.g., the above-defined “fixed” chips).
- the following Monte Carlo algorithm is used.
- the test statistic W is calculated.
- N e.g. 100
- the strategy randomly permutes the “non-fixed” chips without replacement (e.g., the strategy randomly assigns 1 and 0 values to the non-fixed chips).
- the strategy then calculates test statistic W i under each permutation.
- the “p-value” of the statistical test of H 0 versus H 2 is # ⁇ W i ⁇ W
- the system 10 applies the foregoing strategy to wafer map 40 , and displays only the failing chips 46 resulting from systematic failures, which are labeled with an “X”.
- the controller 12 generates an output signal to display unit 16 , effective to cause display unit 16 to display a graphical presentation of the systematic failures superimposed over the wafer map, as illustrated in FIG. 5 .
- system 10 may display the systematic failures in any other suitable or desirable format.
- system 10 segregates the systematic chips in the set of failing chips, it proceeds to functional block or step 26 , where it classifies the remaining failing chips as either repeated or random. Particularly, the system 10 performs a test to identify the chips resulting from repeated or reticle errors; those not so-identified are then considered random.
- the term “remaining chips” shall mean the remainder of failing chips after the systematic chips have been extracted.
- the number of failing chips in reticle zone i may be denoted by F i , and the order statistics thereof may be denoted as follows:
- the count of the reticle zone with the highest failure count is a greater distance from the average reticle zone count than the count of the reticle zone with the lowest failure count
- all failing chips in the reticle zone with the highest failure count are marked as repeated failure chips. If the chi-square test failed, the system 10 repeats the chi-square test on the remaining reticle zones, and so on, until the chi-square test for independence passes.
- system 10 applies the foregoing strategy to wafer map 40 , and displays only the failing chips 46 resulting from repeated failures, which are labeled with an “X”. Once the repeated failures have been extracted, system 10 may further display only the failing chips 46 resulting from random errors, as shown in FIG. 7 .
- the controller 12 generates an output signal to display unit 16 , effective to cause display unit 16 to display graphical presentations of the repeated failures and random failures superimposed over the wafer map, as illustrated in FIGS. 6 and 7, respectively.
- system 10 may display the repeated and systematic failures in any other suitable or desirable format.
- system 10 may provide printed images of the various classified chips, and/or graphical comparisons and/or analysis of the systematic, repeated and random failures (e.g., by use of display unit 16 and input/output unit 18 ).
- system 10 may calculate and display the systematic, repeated and random yields for each wafer, which may be defined by the following equations:
- System 10 may also communicate the foregoing information to other portions of the manufacturing execution system or to other computer systems for further analysis.
- system 10 may perform further analysis on the failing chips that have been designated as systematic, as set forth functional block or step 28 of FIG. 2 . Particularly, system 10 may further partition the identified systematic failing chips into different spatial clusters for the purposes of feeding each spatial cluster into conventional image recognition software that can be used to identify spatial signatures present within the systematic chips, in order to determine the origin or cause of the failure.
- a wafer map may exhibit multiple distinct systematic spatial patterns, as well as failures due to random and reticle factors.
- Known software algorithms exist (e.g., image recognition or spatial signature analysis software) to compare systematic spatial patterns against a known library of spatial patterns for the purposes of automatic identifying the respective origins of the systematic errors.
- a match of a spatial pattern against a known library of similar patterns is helpful, because the corrective action that was ultimately undertaken with respect to the spatial pattern in the library usually will aid in correcting the problem currently under consideration.
- System 10 implements a conventional “flood fill” algorithm to partition the systematic failing chips into different spatial clusters.
- Colors[ 1 . . . n] is an array of n different colors used to mark the different clusters in the systematic wafer map.
- the color of each chip in the wafer map of systematic failing chips may be marked with 0 .
- Color is then set equal to 1.
- System 10 loops over each chip in the wafer map. If the color of the chip is 0, system 10 calls a Fill recursive algorithm (defined below) with the coordinates of the chip. System 10 then increments Color and repeats the procedure.
- the Fill(x, y) algorithm may be defined as follows:
- the present invention accurately classifies each of the failing chips on a wafer in a unique one of a plurality of error categories, such as systematic, random and repeated type errors. This allows a fabrication engineer or professional to provide corrective action which is purposely designed to overcome the specific type of errors or failures encountered. It should further be appreciated that in other embodiments, the system 10 may be used to classify errors in different and/or additional types of categories or subcategories.
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Cited By (2)
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US20080147355A1 (en) * | 2006-12-19 | 2008-06-19 | Qimonda North America Corp. | Die and Wafer Failure Classification System and Method |
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US8782087B2 (en) | 2005-03-18 | 2014-07-15 | Beyondcore, Inc. | Analyzing large data sets to find deviation patterns |
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US10802687B2 (en) | 2011-12-04 | 2020-10-13 | Salesforce.Com, Inc. | Displaying differences between different data sets of a process |
US11054815B2 (en) * | 2016-03-11 | 2021-07-06 | Applied Materials, Inc. | Apparatus for cost-effective conversion of unsupervised fault detection (FD) system to supervised FD system |
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