US6723613B2 - Method of forming an isolated-grain rugged polysilicon surface via a temperature ramping step - Google Patents

Method of forming an isolated-grain rugged polysilicon surface via a temperature ramping step Download PDF

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US6723613B2
US6723613B2 US10188910 US18891002A US6723613B2 US 6723613 B2 US6723613 B2 US 6723613B2 US 10188910 US10188910 US 10188910 US 18891002 A US18891002 A US 18891002A US 6723613 B2 US6723613 B2 US 6723613B2
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silicon
amorphous
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polysilicon
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Chin-Te Huang
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Semiconductor Manufacturing International (Shanghai) Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L28/00Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40Capacitors
    • H01L28/60Electrodes
    • H01L28/82Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/84Electrodes with an enlarged surface, e.g. formed by texturisation being a rough surface, e.g. using hemispherical grains
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02436Intermediate layers between substrates and deposited layers
    • H01L21/02439Materials
    • H01L21/02441Group 14 semiconducting materials
    • H01L21/0245Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02521Materials
    • H01L21/02524Group 14 semiconducting materials
    • H01L21/02532Silicon, silicon germanium, germanium
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02518Deposited layers
    • H01L21/02587Structure
    • H01L21/0259Microstructure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02612Formation types
    • H01L21/02617Deposition types
    • H01L21/0262Reduction or decomposition of gaseous compounds, e.g. CVD
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02365Forming inorganic semiconducting materials on a substrate
    • H01L21/02656Special treatments
    • H01L21/02664Aftertreatments
    • H01L21/02667Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/10Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H01L27/108Dynamic random access memory structures
    • H01L27/10844Multistep manufacturing methods
    • H01L27/10847Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells
    • H01L27/1085Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto
    • H01L27/10852Multistep manufacturing methods for structures comprising one transistor one-capacitor memory cells with at least one step of making the capacitor or connections thereto the capacitor extending over the access transistor

Abstract

A method is disclosed for increasing the surface area of hemispherical-grain polysilicon and for forming a storage-node capacitor plate that can be used in the manufacture of dynamic random access memories (DRAMs). A layer of polycrystalline silicon is deposited on a substrate. This layer is either in-situ doped or doped after it is deposited via implantation or diffusion. Next, an amorphous silicon layer is deposited on top of the polycrystalline silicon layer. Hemispherical-grain (HSG) polysilicon seeds are then grown on the upper surface of the amorphous silicon layer using one of several known techniques. An anneal sequence is then performed in the presence of silane. An initial temperature of about 550° C. is maintained for about 3.5 minutes. At the end of that period, the temperature is ramped at a rate of 2° C. per minutes over a period of about 8 minutes. Upon reaching a temperature of about 568° C., that final temperature is maintained for an additional period of about 6 minutes. During the anneal sequence, silicon atoms within the amorphous silicon layer migrate to the seeded locations and incorporate themselves in the crystal matrices of the HSG seeds, thereby causing them to grow. The ramped temperature during the anneal sequence is highly effective in forming isolated grains of HSG polysilicon. The underlying doped polysilicon layer provides electrical continuity between the isolated grains of HSG polysilicon.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to semiconductor manufacturing technology and, more particularly, to methods for improving the morphology of rugged polycrystalline silicon, as it relates to increased surface area of the material and its usefulness as a capacitor plate electrode in integrated circuits.

2. Description of the Prior Art

In 1965, Gordon Moore, the co-founder of Intel Corporation, observed that the number of transistors per square inch on integrated circuits had doubled every year since the invention of the integrated circuit. Moore predicted that this trend would continue for the foreseeable future. Although the pace slowed somewhat in subsequent years, the past forty years have seen a doubling of transistor density approximately every 18 months. Most experts, including Moore himself, expect this trend to continue for at least another 15 years, when the finite size of atomic particles may limit any significant increases in miniaturization.

The miniaturization trend predicted by Moore has proved applicable to nearly all types of integrated circuits, including logic circuits, microprocessors, and semiconductor memory. As the density of integrated circuits has increased, corresponding increases in device speed have been coupled with corresponding decreases in cost and power consumption per transistor.

For at least a quarter of a century, dynamic random access memory (DRAM)-despite the fact that it is generally slower than static random access memory (SRAM) of the same generation, and requires periodic refresh to prevent data volatility—has established itself as the principal type of main memory for computer applications, as a result of its low cost per bit of storage. The basic units of a DRAM memory cell are a capacitor and an access transistor, through which the capacitor can be initially charged, refreshed, and “read”. The cell capacitor generally comprises a storage node plate that is directly coupled to the cell access transistor; a cell plate that is generally maintained at ground potential, and is common to all cells on the same chip; and a dielectric layer sandwiched between the storage node plate and the cell plate. As DRAM density increases, chip real estate available for capacitor construction must invariably decrease. However, the charge required to provide adequate functionality of memory cells and the sense amplifiers used to read their charge contents does not decrease at the same rate. Consequently, DRAM manufacturers have found it necessary to maintain cell capacitance using a variety of three-dimensional techniques, such as the construction of stacked or trench capacitors, the use of new capacitor dielectric materials having higher dielectric constants, and the use of capacitor plate material having non-smooth surfaces.

Silicon has been used extensively, both as a substrate and as a deposited material, for most past and present generations of integrated circuits. Solid silicon exists in both crystalline and amorphous forms. Crystalline silicon can be either monocrystalline or polycrystalline. The wafers, on which most integrated circuits are constructed, are typically monocrystalline (single-crystal) silicon. Under proper conditions, additional monocrystalline silicon can be epitaxially grown on a silicon wafer substrate using chemical vapor deposition. Polycrystalline silicon (often called polysilicon for short), typically results when silicon is deposited at a temperature in excess of about 580° C. using a chemical vapor deposition process in the absence of a monocrystalline surface which could order the deposition of silicon atoms into a single-crystal matrix. At a temperature of less than about 580° C., amorphous silicon will be deposited. The exact transition temperature, where the change from amorphous to polycrystalline silicon occurs, depends on the types of precursor compounds and certain temperature-unrelated reaction conditions used in the chemical vapor deposition process.

Polysilicon is commonly utilized as a material for both capacitor plates in DRAM memory cells, because of its compatibility with subsequent high temperature processing, thermal expansion properties compatible with those of silicon dioxide, and its ability to be conformally deposited over widely varying topography. In order for polysilicon to conduct electricity, it must be conductively doped, which can be accomplished either during the deposition process (in situ) or subsequent to its deposition via diffusion or implantation of the appropriate impurities.

It has been recognized, for about a decade, that capacitance of a capacitor formed from a polysilicon layer can be increased merely by increasing the surface roughness of the polysilicon film that is used as a capacitor storage node. As capacitance is roughly proportional to the surface area of the smallest of the two capacitor plates, capacitance can be increased if roughness of the plate contributes to its area. In order for this to occur, the dielectric layer between a DRAM cell's storage node plate and the cell plate must be sufficiently thin to conformally coat the rough surface of the storage node. In addition, the dielectric layer must be particularly resistant to electrical breakdown, as the rough surface will suffer electrical breakdown at a much lower voltage than would a smooth surface with a dielectric layer of the same composition and thickness. By employing a relatively thin dielectric layer, the roughness on the storage node capacitor plate is transferred to the cell's dielectric layer and, finally, to the cell plate, resulting in a larger surface area and, hence, greater capacitance than would have a similarly shaped capacitor formed from smooth polysilicon capacitive layers.

It is well known in the art that rough polysilicon, known either as rugged polysilicon or hemisherical-grain (HSG) polysilicon, can be formed by a variety of methods. The known methods include a single-step low pressure chemical vapor deposition (LPCVD), and a multi-step procedure involving depositing a layer of amorphous silicon, seeding the layer of amorphous, and annealing the seeded layer to convert the amorphous silicon to HSG. For the single-step method, silicon is deposited at a temperature between the range of temperatures where amorphous silicon is formed and the range of temperatures where polycrystalline silicon is formed. The process is typically performed within a range of about 555-568° C. at a pressure of about 190 mtorr. Silane (SiH4) is typically used as the primary precursor for this process. For the method involving the seeding and annealing of amorphous silicon, an amorphous silicon layer is first deposited. Subsequently, the deposited layer is seeded with either silane or disilane molecules in order to form crystals upon the surface of the amorphous silicon layer. The seeded layer is then annealed in a vacuum. Amorphous silicon atoms migrate and grow grains of HSG on the silicon crystals. The anneal step can be performed at a temperature in excess of about 450° C.

A tracing and subsequent digitization of a scanning electro micrograph of the surface of a 1.34 μm square sample of a rugged polysilicon layer 100 formed using the conventional techniques heretofore described is shown in FIG. 1. It will be noted that an alternating array of plateaus 101 and valleys 102 have been formed within the rugged polysilicon layer 100, thereby increasing the surface area thereof. It will be noted that, with few exceptions, each plateau 101 appears to be interconnected with all other plateaus.

SUMMARY OF THE INVENTION

The present invention includes a method for increasing the surface area of hemispherical-grain polysilicon and for forming a storage-node capacitor plate that can be used in the manufacture of dynamic random access memories (DRAMs). The invention represents an improvement to the multi-step process described in the Background of the Invention section. As the instant process is likely to be used primarily in the manufacture of dynamic random access memories, it will be disclosed in that context. A layer of polycrystalline silicon having a thickness within a range of about 200 to 300 Å is deposited on a substrate. This layer is either in-situ doped or doped after it is deposited via implantation or diffusion. Next, an amorphous silicon layer also having a -thickness within a range of about 200 to 300 Å is deposited on top of the polycrystalline silicon layer. Hemispherical-grain (HSG) polysilicon seeds are then grown on the upper surface of the amorphous silicon layer using one of several known techniques. For example, following a dilute hydrofluoric (DHF) acid dip to remove any native oxide, the amorphous silicon is subjected to an ultra-high vacuum (UHV) condition at a temperature within a range of about 500 to 800° C. for a period of from about 1 to 10 minutes in the presence of either silane or disilane at a concentration below about 1.0×10−1/m3. These conditions are conducive to the growth of HSG silicon seeds on the surface of the amorphous silicon layer. An anneal sequence is then performed in the presence of silane. An initial temperature of about 550° C. is maintained for about 3.5 minutes. At the end of that period, the temperature is ramped at a rate of 2° C. per minutes over a period of about 8 minutes. Upon reaching a temperature of about 568° C., that final temperature is maintained for an additional period of about 6 minutes. During the anneal sequence, silicon atoms within the amorphous silicon layer migrate to the seeded locations and incorporate themselves in the crystal matrices of the HSG seeds, thereby causing them to grow. The ramped temperature during the anneal sequence is highly effective in forming isolated grains of HSG polysilicon. The underlying doped polysilicon layer provides electrical continuity between the isolated grains of HSG polysilicon.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a top planar view of a 1.34 μm square sample of a typical hemispherical-grain polysilicon layer that has been formed using conventional techniques known in the art;

FIG. 2 is a cross-sectional view of a portion of an in-process integrated circuit, which includes a substrate on which has been deposited a polysilicon layer;

FIG. 3 is a cross-sectional view of the in-process integrated circuit portion of FIG. 2, following the deposition of an amorphous silicon layer thereon;

FIG. 4 is a cross-sectional view of the in-process integrated circuit portion of FIG. 3 following seeding of the amorphous silicon layer;

FIG. 5 is a cross-sectional view of the in-process integrated circuit portion of FIG. 4 following a ramped elevated temperature anneal step; an

FIG. 6 is a top planar view of a 1.34 μm square sample of a hemispherical-grain polysilicon layer that has been formed using a ramped elevated temperature anneal step.

PREFERRED EMBODIMENT OF THE INVENTION

The present invention includes a method for increasing the surface area of hemispherical-grain polysilicon and for forming a storage-node capacitor plate that can be used in the manufacture of dynamic random access memories (DRAMs). The invention provides a marked increase in capacitance for capacitor plates so formed by creating isolated clumps or nodules of hemispherical-grain silicon. As the instant process is likely to be used primarily in the manufacture of dynamic random access memories, it will be disclosed in that context.

Referring now to the in-process integrated circuit 200 of FIG. 2, a polycrystalline silicon (polysilicon) layer 201 having a thickness within a range of about 200 to 300 Å has been deposited superjacent a semiconductor substrate. Preferably, the polysilicon layer 201 is deposited via chemical vapor due to the high degree of conformality (evenness of thickness) on surfaces of varied orientation and complexity. The polysilicon layer 201 is either in-situ doped or doped after it is deposited via implantation or diffusion so as to render it electrically conductive. For DRAM capacitor plates, phosphorus is considered to be the preferred primary dopant.

Referring now to FIG. 3, an amorphous silicon layer 301 having a thickness within a range of about 200 to 300 Å has been deposited superjacent the polysilicon layer 201. The amorphous silicon layer 301 is deposited via chemical vapor deposition at a temperature within a range of 535 to 550° C., using silane gas as a precursor compound.

Referring now to FIG. 4, the amorphous silicon layer 301 is seeded with hemispherical-grain (HSG) polysilicon seeds are then grown on the upper surface of the amorphous silicon layer using one of several known techniques. One commonly practiced seeding technique involves subjecting the amorphous silicon layer 301 to a dilute hydrofluoric (DHF) acid dip to remove any native oxide, then subsequently subjecting it to an ultra-high vacuum (UHV) condition at a temperature within a range of about 500 to 800° C. for a period of from about 1 to 10 minutes in the presence of either silane or disilane at a concentration below about 1.0×10−3/m3. These conditions are conducive to the growth of HSG silicon seeds, or granules 402, on the surface of the amorphous silicon layer. The seeded amorphous silicon layer 401 is now ready for a novel elevated temperature anneal step.

Referring now to FIG. 5, the seeded amorphous silicon layer 401 is subjected to a ramped anneal procedure. The procedure is implemented by subjected the seeded amorphous silicon layer 401 to an initial temperature of about 550° C. for about 3.5 minutes. The temperature is then ramped to a final temperature of about 565 to 575° C. over a period of about 8 minutes. The final temperature is then maintained for about 6 minutes. For a presently preferred implementation of the anneal procedure, a temperature ramp rate of about 2° C. per minute is employed in combination with a final temperature of about 568° C. During the anneal sequence, silicon atoms within the amorphous silicon layer migrate to the seeded locations and incorporate themselves in the crystal matrices of the HSG seeds, thereby causing them to grow. The ramped temperature during the anneal sequence is highly effective in forming isolated grains, or nodules 501 of HSG polysilicon. Each of the grains 501 is separated from adjacent grains 501 by a valley 502. Thus, the underlying doped polysilicon layer 201 provides electrical continuity between the isolated grains, or nodules 501 of HSG polysilicon.

Tests performed using the isolated-grain rugged poly process for 256-megabyte DRAM devices yielded a cell capacitance increase of 2 femtofarads, or about 8 percent, as compared with DRAM devices manufactured using the conventional rugged polysilicon formula described in the Background of the Invention section.

A tracing and subsequent digitization of a scanning electro micrograph of the surface of a 1.34 μm square sample of a rugged polysilicon layer 600, formed using the techniques of the present invention, is shown in FIG. 6. It will be noted that in this drawing figure, each nodule of hemispherical-grain polysilicon 501 is separated from each of the other nodules by a network of interconnecting valleys 502.

Although only a single embodiment of the improved rugged poly formation process is disclosed herein, it will be obvious to those having ordinary skill in the art that changes and modifications may be made thereto without departing from the scope and the spirit of the invention as hereinafter claimed.

Claims (20)

What is claimed is:
1. A method of forming a capacitor plate having an isolated-grain rough polysilcon surface, the method comprising the steps of:
providing a semiconductor substrate;
depositing a layer of polycrystalline silicon which at least partially overlies the substrate;
doping the polycrystalline layer to render it electrically conductive;
depositing an amorphous silicon layer which overlies the polycrystalline layer;
seeding the amorphous silicon layer with hemispherical-grain polysilicon granules;
annealing the seeded amorphous silicon layer, which includes temperature ramping from an initial temperature of about 550° C. for to a final temperature within a range of about 565 to 575° C. over a period of about 8 minutes.
2. The method of claim 1, wherein a temperature ramping rate of about 2° C. per minute is employed.
3. The method of claim 1, wherein the initial temperature is maintained for about 3.5 minutes.
4. The method of claim 1, wherein the final temperature is maintained for about 6 minutes.
5. The method of claim 1, wherein the amorphous silicon layer is deposited in a reaction chamber via low-pressure chemical vapor deposition at a temperature within a range of about 535 to 550° C. using silane gas as a precursor compound.
6. The method of claim 1, wherein annealing of the seeded amorphous silicon layer is performed in an ambiance containing silane gas.
7. The method of claim 1, wherein said polycrystalline layer is doped primarily with phosphorus.
8. The method of claim 5, wherein the flow of silane into the reaction chamber is maintained within a range of about 500 to 1200 sccm.
9. The method of claim 6, wherein the annealing step is performed in a furnace into which a silane gas flow, within a range of about 500 to 1200 sccm, is maintained.
10. The method of claim 6, wherein seeding of the amorphous silicon layer is accomplished by:
subjecting the amorphous silicon layer to a dilute hydrofluoric (DHF) acid dip to remove any native oxide; and
subjecting the amorphous silicon layer to an ultra-high vacuum condition at a temperature within a range of about 500 to 800° C. for a period of from about 1 to 10 minutes in the presence of either silane or disilane gas at a concentration below about 1.0×10−3/m3.
11. A method of converting an amorphous silicon layer to a plurality of spaced-apart hemispherical-grain polysilicon nodules, the method comprising the steps of:
depositing an amorphous silicon layer which overlies a base layer;
seeding the amorphous silicon layer with hemispherical-grain polysilicon granules;
annealing the seeded amorphous silicon layer, which includes temperature ramping from an initial temperature of about 550° C. for to a final temperature within a range of about 565 to 575° C. over a period of about 8 minutes.
12. The method of claim 11, wherein said base layer is a phosphorus-doped polycrystalline silicon layer.
13. The method of claim 11, wherein the intial temperature is maintained for about 3.5 minutes.
14. The method of claim 11, wherein the final temperature is maintained for about 6 minutes.
15. The method of claim 11, wherein the amorphous silicon layer is deposited superjacent a polycrystalline silicon layer in a reaction chamber via low-pressure chemical vapor deposition at a temperature within a range of about 535 to 550° C. using silane gas as a precursor compound.
16. The method of claim 11, wherein annealing of the seeded amorphous silicon layer is performed in an ambiance containing silane gas.
17. The method of claim 15, wherein the flow of silane into the reaction chamber is maintained within a range of about 500 to 1200 sccm.
18. The method of claim 11, wherein the annealing step is performed in a furnace into which a silane gas flow, within a range of about 500 to 1200 sccm, is maintained.
19. The method of claim 11, wherein hemispherical-grain (HSG) polysilicon seeds are grown on the upper surface of the amorphous silicon layer using the steps of:
subjecting the amorphous silicon layer to a dilute hydrofluoric (DHF) acid dip to remove any native oxide; and
subjecting the amorphous silicon layer to an ultra-high vacuum condition at a temperature within a range of about 500 to 800° C. for a period of from about 1 to 10 minutes in the presence of either silane or disilane at a concentration below about 1.0×10−3/m3.
20. The method of claim 11, wherein a temperature ramping rate of about 2° C. per minute is employed.
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US20060118781A1 (en) * 2004-12-03 2006-06-08 Omnivision Technologies, Inc. Image sensor and pixel having a polysilicon layer over the photodiode

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JP4072621B2 (en) * 2003-10-23 2008-04-09 国立大学法人名古屋大学 The method for manufacturing a manufacturing method and a floating gate type memory capacitor structure of the silicon nanocrystals
KR101012103B1 (en) 2008-05-02 2011-02-07 주식회사 유진테크 Method for depositing of ultra fine grain poly silicon thin film

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US20050239263A1 (en) * 1997-02-28 2005-10-27 Micron Technology, Inc. Diffusion-enhanced crystallization of amorphous materials to improve surface roughness
US20040245559A1 (en) * 2003-06-03 2004-12-09 Marsela Pontoh Capacitor constructions
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