US6573944B1 - Horizontal synchronization for digital television receiver - Google Patents
Horizontal synchronization for digital television receiver Download PDFInfo
- Publication number
- US6573944B1 US6573944B1 US09/562,455 US56245500A US6573944B1 US 6573944 B1 US6573944 B1 US 6573944B1 US 56245500 A US56245500 A US 56245500A US 6573944 B1 US6573944 B1 US 6573944B1
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- US
- United States
- Prior art keywords
- source
- signal
- drive signals
- control signal
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/015—High-definition television systems
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/04—Synchronising
- H04N5/12—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising
- H04N5/126—Devices in which the synchronising signals are only operative if a phase difference occurs between synchronising and synchronised scanning devices, e.g. flywheel synchronising whereby the synchronisation signal indirectly commands a frequency generator
Definitions
- This invention relates to the field of horizontal synchronization in digital television receivers.
- Analog video signals have a horizontal synchronizing and scanning frequency of approximately 15.735 KHz in the NTSC system. This synchronizing and scanning frequency is different in the PAL and SECAM systems, but is generally comparable. Irrespective of the system, this is generally referred to as a standard horizontal synchronizing and scanning frequency, often denoted as fH or 1 fH.
- Television receivers providing progressive scanning rather than interlaced scanning operate at twice the standard synchronizing frequency, approximately 31.47 KHz in NTSC, often denoted as 2 fH.
- Such television receivers upconvert the analog video input using digital circuits that double the number of horizontal lines per field, either by repeating each line or by interpolation.
- a phase detector is utilized to synchronize the 2 fH deflection circuit with the 1 fH input video signal.
- Digital television receivers for example those designed to process video signals in the MPEG2 format, can have horizontal synchronization circuits operating at 2.14 fH, approximately 33.75 KHz.
- the circuits for processing an MPEG2 signal include a time base correction function that obviates the need for a phase detector. Instead, a binary rate multiplier responsive to a microprocessor controls an oscillator, which in turn drives a number of counters that divide the oscillator output down to the desired horizontal drive frequency.
- the upconverted video data is written into and read from a memory in such a way that time base correction is provided.
- a solution was needed that would enable a digital television receiver to display digital video signals, for example in MPEG2 format, at 2.14 fH and to display standard video signals, for example NTSC, in an upconverted, progressively scanned format.
- the 1 fH synchronizing/drive signal obtained from the 1 fH video input signal is compared to the 2 fH deflection drive pulse in a phase detector.
- the output of the phase detector is then used to control the frequency of a voltage controlled oscillator.
- the display pixel clock for the MPEG2 video signal is derived from the VCO, and accordingly, controlling its frequency permits closing the phase locked loop to bring the 2 fH deflection in phase/frequency lock with the 1 fH NTSC input horizontal synchronizing component.
- this solution posed a further problem of needing to operate the television receiver at two different horizontal scanning frequencies for different kinds of video input signals, for example digital video signals in MPEG2 format at 2.14 fH and analog video signals in NTSC, PAL or SECAM format at 2 fH.
- a horizontal synchronizing system in accordance with the inventive arrangements comprises: a source of a horizontal synchronizing signal; a source of first and second higher frequency horizontal drive signals; a source of a first control voltage; a source of a second control signal; and, said source of said drive signals having a phase-locked mode of operation at said first higher frequency responsive to said first control signal and a phase-unlocked mode of operation at said second higher frequency responsive to said second control signal.
- the system can further comprise means for phase locking said first drive signal with said source of said horizontal synchronizing signal.
- the source of said drive signals can comprises a controllable oscillator.
- the oscillator can advantageously operate at the same frequency responsive to both said first and second control signals.
- the source of said drive signals can advantageously further comprise counters clocked by the oscillator and supplying different numbers of samples during blanking at said first and second higher frequencies respectively.
- Another horizontal synchronizing system in accordance with the inventive arrangements, that solves the problems faced by the prior art, comprises: a source of a horizontal synchronizing signal; a source of first and second higher frequency horizontal drive signals; a phase detector for generating a first control voltage responsive to said horizontal synchronizing signal and said first horizontal drive signal; a source of a second control signal; and, a switch for selectively supplying said first control signal to said source of said drive signals for a phase-locked mode of operation at said first higher frequency and supplying said second control signal to said source of said drive signals for a phase-unlocked mode of operation at said second higher frequency.
- the source of the drive signals can comprise: a voltage controlled oscillator; and, counters for supplying different numbers of samples during blanking at said first and second higher frequencies respectively.
- the source of said second control signal can comprise: a binary rate multiplier; and, a binary rate multiplier filter.
- the system can advantageously further comprise a circuit responsive to said drive signals for and generating a pulse width stretched timing signal as an input to said phase detector, in order to control the response speed of the phase locked loop.
- a horizontal synchronizing system in accordance with a presently preferred embodiment comprises: a source of an fH horizontal synchronizing signal; a source of nfH and mfH horizontal drive signals, where n ⁇ 2, m ⁇ 2 and n is an integer; a phase detector for generating a first control signal responsive to said fH horizontal synchronizing signal and said nfH horizontal drive signal; a source of a second control signal; and, a switch for selectively supplying said first control signal to said source of said drive signals for a phase-locked mode of operation at nfH and supplying said second control signal to said source of said drive signals for a phase-unlocked mode of operation at mfH.
- the factor n can be equal to 2 and the factor m can be equal to 2.14.
- the source of said drive signals can comprise: a voltage controlled oscillator; and, counters for changing the number of samples during blanking at said nfH and mfH frequencies.
- FIG. 1 is a block diagram of a multiple frequency horizontal synchronizing system in accordance with the inventive arrangements.
- FIG. 2 is a schematic diagram of a first embodiment for implementing the synchronizing system shown in FIG. 1 .
- FIG. 3 is a schematic diagram of a second embodiment for implementing the synchronizing system shown in FIG. 1 .
- FIG. 4 illustrates waveforms useful for explaining operation of the phase detector in FIG. 3 .
- FIG. 1 A block diagram of a multiple frequency horizontal synchronizing system 10 in accordance with the inventive arrangements is shown in FIG. 1 .
- the system has selectable modes of operation including an open loop and a closed loop control path for an oscillator 20 .
- Oscillator 20 can, for example, be a voltage controlled oscillator (VCO) or a voltage controlled crystal oscillator (VCXO).
- Open loop control is used for displaying digital video signals, for example in MPEG2 format.
- the oscillator 20 operates at 13.5 MHz, which is then doubled to 27 MHz and used as the reference for an 81 MHz pixel display clock and the MPEG2 system clock.
- the open loop control path begins with a microprocessor ( ⁇ P) 26 that supplies a digital frequency control value to a binary rate multiplier (BRM) 22 over a data bus 40 .
- the digital frequency control value is converted to an MPEG2 system clock control voltage by a BRM filter 24 .
- the output of BRM filter 24 on line 25 is a first input to a filter source switch 18 .
- the MPEG2 system clock control voltage is supplied to the oscillator 20 from filter source switch 18 responsive to a 2 fH/2.14 fH selection signal generated by the microprocessor 27 .
- the BRM filter input represents the control signal used for 2.14 fH deflection.
- the selection signal is illustrated as a direct wire connection, but selection control can also be implemented by the data bus 40 or by a serial data and control bus of the kind having SDA and SCL signals, not shown.
- a clock generation and counters circuit 28 is responsive to the output of the oscillator 20 .
- a raster generator 30 is responsive to the clock generation and counters circuit 28 , and in turn, drives a display circuit 36 .
- the display circuit generates a 2.14 fH drive signal 37 .
- circuits 28 , 30 and 36 are embodied in an Sti7000 integrated circuit 38 available from ST Microelectronics.
- the closed loop path includes a phase detector 14 .
- a standard 1 fH analog video signal for example NTSC, PAL or SECAM, is an input to a digitizer and synchronizing signal separator 12 .
- a 1 fH synchronizing signal is a first input to the phase detector 14 .
- the drive signal generated by the display circuit 36 is fed back as a second input to the phase detector 14 .
- the feedback path includes a branch point 42 that illustrates three different embodiments.
- path 44 leads directly to the phase detector without any modification of the drive signal.
- the phase detector compares the phase of every 1 fH synchronizing pulse with every other pulse of the drive signal.
- the drive signal will have a frequency of 2 fH.
- pulse width stretch circuit 46 the drive pulses are stretched, for example from a width of approximately 1 ⁇ sec to approximately 9 ⁇ sec.
- divider circuit 48 the drive signal is divided by two. The embodiments represented by circuits 46 and 48 enable the resulting phase locked loop to operate with a faster response time than when direct path 44 is utilized.
- the output of the phase detector is integrated by a phase detector filter 16 .
- the integrated output is a phase lock control voltage supplied as a second input to filter source switch 18 over line 17 .
- the phase detector filter input represents the control signal used for 2 fH deflection.
- the analog video that has been processed by digitizer 12 is supplied on lines 15 to a 1 fH to 2 fH upconversion circuit 32 .
- the upconversion can be accomplished by doubling the number of horizontal lines, as the digitized video is read out from a memory 34 .
- the upconversion can be accomplished by interpolation.
- the upconverted video signal is read from the memory 34 into the display circuit 36 , and then supplied as a video output signal (VIDEO OUT).
- the upconversion circuit 32 can also be a part of the Sti7000 integrated circuit.
- the filter source switch will at that time be supplying the MPEG2 system clock control voltage to the oscillator and the output of the phase detector 16 , if any, will be effectively ignored.
- the oscillator When the system supplies the 2 fH drive signal instead of the 2.14 fH drive signal the oscillator operates at the same clock frequency. Instead of changing the oscillator frequency, the operation of the clock generation and counters circuit 28 is modified to change the number of samples during blanking. The significant difference is that the 2 fH drive signal and the 1 fH input signal are phase locked, thus eliminating, or at least substantially eliminating the noise problem resulting from unlocked operation.
- FIG. 2 illustrates a first set of embodiments for implementing various parts of the system 10 shown in FIG. 1 .
- Pulse width stretching circuit 46 can be embodied as a CD4098 integrated circuit U 2 , a CMOS dual one-shot.
- the one-shot utilizes an external timing circuit formed by capacitor C 3 and resistors R 2 and R 3 to stretch the 2 fH drive pulse from a 1 ⁇ sec duration to a 9 ⁇ sec duration.
- the phase detector 14 can be implemented by a MC1391 integrated circuit U 3 , a television horizontal processor including a phase detector.
- the output of the one-shot U 2 is filtered by resistors R 4 and R 5 and capacitor C 4 and then applied to pin 4 of U 3 .
- the 1 fH horizontal synchronizing signal is filtered by resistor R 1 and capacitor C 1 and applied to pin 3 of U 3 .
- the output of the phase detector is applied to a phase detector filter 16 , which is embodied as an integrator formed by capacitors C 5 and C 6 and resistor R 6 .
- the voltage on the output of the integrator is then fed to a voltage scaler 60 , embodied as a TL082 operational-amplifier U 4 , where the voltage is scaled to match the range to the VCO/VCXO 20 .
- the filter source switch 18 can be embodied as CD4053B analog multiplexer integrated circuit U 5 .
- One input contact of a switch A is coupled to the output of the op-amp U 4 on pin 13 .
- the other input contact of switch A is coupled to the BRM filter 24 , through resistor R 22 , on pin 13 of U 5 .
- a switch embodied by transistor Q 1 controls the voltage on pin 11 of U 5 responsive to the 2 fH/2.14 fH control signal, thus controlling the operation of switch A.
- Switch A selects either the BRM filter or the phase detector filter as the control source for the oscillator 20 , for operation at 2.14 fH and 2 fH respectively.
- FIG. 3 illustrates a second set of embodiments for implementing various parts of the system 10 shown in FIG. 1 .
- the embodiment of FIG. 3 is particularly useful for a VCXO oscillator, which uses varactors to control frequency.
- This embodiment advantageously combines the phase detector and scaler of FIG. 2, thus reducing the number of components, by having the output of the phase detector directly generate the range of 0 to 15 volts required for the VCXO varactors.
- the phase detector 14 is embodied in a CD4053B analog multiplexer U 6 , in which switch A is switched between +15 volts on pin 13 and ground on pin 12 at a 2 fH rate based on the deflection.
- the 3 is embodied by a component one-shot circuit formed by transistors Q 2 and Q 3 .
- the values of resistors R 10 , R 11 , R 12 , R 13 and R 14 are chosen to provide an approximately 9 ⁇ sec output pulse responsive to an approximately 1 ⁇ sec input pulse, as in FIG. 2 . It will be appreciated that the embodiments of the pulse width stretch circuit 46 shown in FIGS. 2 and 3 are interchangeable.
- the 2 fH rate control for switch A is the width-extended 2 fH drive pulse applied to pin 11 .
- Switch B is controlled by transistor Q 4 responsive to the 1 fH synchronizing component.
- the output of switch B is coupled from pin 1 to the phase detector filter 16 , embodied by capacitors C 16 and C 17 and resistor R 18 .
- the integrated voltage is coupled to one input of switch C on pin 3 .
- the BRM filter output is coupled to the other input of switch C on pin 5 .
- Switch C switches the voltage applied to the VCXO varactors between the phase detector output for 1 fH video signal upconversion operation and the BRM output used in normal MPEG2 decoding.
- the magnitudes of the phase detector filter charge and discharge currents are primarily determined by the value of resistor R 17 , presently 20 K. In the locked condition the average value of the charge and discharge currents are equal.
- FIG. 4 illustrates the voltage at pin 15 , the voltage at pin 10 and the current at through resistor R 17 , which is also the current at pin 1 . It can be seen that the 1 fH signal on pin 10 samples every other pulse of the 2 fH signal on pin 15 , thus causing the positive and negative currents at resistor R 17 /pin 1 . More particularly, when the pulses of the 1 fH signal occur, the integrator is charged or discharged. When the 1 fH pulses do not occur, the input to the integrator floats. The integrated current at pin 3 need not be scaled to drive the varactors of a VCXO.
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- Multimedia (AREA)
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- Synchronizing For Television (AREA)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/562,455 US6573944B1 (en) | 2000-05-02 | 2000-05-02 | Horizontal synchronization for digital television receiver |
CA002345559A CA2345559C (en) | 2000-05-02 | 2001-04-26 | Horizontal synchronization for digital television receiver |
EP01110480A EP1152601A3 (en) | 2000-05-02 | 2001-04-27 | Horizontal synchronization for digital television receiver |
KR1020010023521A KR100673922B1 (ko) | 2000-05-02 | 2001-04-30 | 디지털 텔레비전 수신기용 수평 동기 시스템 |
MYPI20012024A MY126094A (en) | 2000-05-02 | 2001-04-30 | Horizontal synchronization for digital television receiver |
JP2001134413A JP2001358969A (ja) | 2000-05-02 | 2001-05-01 | ディジタルテレビジョン受信機の水平同期 |
CNB011214961A CN1204737C (zh) | 2000-05-02 | 2001-05-02 | 数字电视接收机的水平同步系统 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/562,455 US6573944B1 (en) | 2000-05-02 | 2000-05-02 | Horizontal synchronization for digital television receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
US6573944B1 true US6573944B1 (en) | 2003-06-03 |
Family
ID=24246355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/562,455 Expired - Fee Related US6573944B1 (en) | 2000-05-02 | 2000-05-02 | Horizontal synchronization for digital television receiver |
Country Status (7)
Country | Link |
---|---|
US (1) | US6573944B1 (ko) |
EP (1) | EP1152601A3 (ko) |
JP (1) | JP2001358969A (ko) |
KR (1) | KR100673922B1 (ko) |
CN (1) | CN1204737C (ko) |
CA (1) | CA2345559C (ko) |
MY (1) | MY126094A (ko) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030179318A1 (en) * | 2002-03-22 | 2003-09-25 | Mohammad Alkhalili | Self-adjusting pixel clock and method therefor |
US7522216B2 (en) * | 2005-09-20 | 2009-04-21 | National Semiconductor Corporation | Video synchronization signal detection circuit |
US20160351169A1 (en) * | 2015-05-27 | 2016-12-01 | Au Optronics Corporation | Source driving device, timing controlling device, method for receiving display signal and method for transmitting display signal |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100484183B1 (ko) * | 2002-12-04 | 2005-04-20 | 삼성전자주식회사 | 수평 동기 신호 변동을 제어하는 영상 재생 장치 및 그 방법 |
Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4414571A (en) | 1980-10-09 | 1983-11-08 | Matsushita Electric Industrial Co., Ltd. | Television receiver |
US4996596A (en) * | 1988-09-02 | 1991-02-26 | Sanyo Electric Co., Ltd. | Phase synchronizing circuit in video signal receiver and method of establishing phase synchronization |
US5289508A (en) | 1990-11-30 | 1994-02-22 | Fujitsu Limited | Clock information transmitting device and clock information receiving device |
US5459756A (en) | 1994-06-27 | 1995-10-17 | Motorola, Inc. | Sampling phase detector arrangement |
EP0779741A2 (en) | 1995-12-12 | 1997-06-18 | Thomson Consumer Electronics, Inc. | A method and apparatus for generating variable rate synchronization signals |
US5796392A (en) | 1997-02-24 | 1998-08-18 | Paradise Electronics, Inc. | Method and apparatus for clock recovery in a digital display unit |
WO1999016243A1 (en) | 1997-09-26 | 1999-04-01 | Sarnoff Corporation | Synchronized multiple format video processing method and apparatus |
US5907364A (en) | 1995-05-29 | 1999-05-25 | Hitachi, Ltd. | Display device for information signals |
US6028641A (en) | 1996-06-03 | 2000-02-22 | Lg Electronics Inc. | Device and method for generating a stable system clock in HDTV |
US6091304A (en) | 1998-09-22 | 2000-07-18 | Lg Information & Communications, Ltd. | Frequency band select phase lock loop device |
-
2000
- 2000-05-02 US US09/562,455 patent/US6573944B1/en not_active Expired - Fee Related
-
2001
- 2001-04-26 CA CA002345559A patent/CA2345559C/en not_active Expired - Fee Related
- 2001-04-27 EP EP01110480A patent/EP1152601A3/en not_active Withdrawn
- 2001-04-30 KR KR1020010023521A patent/KR100673922B1/ko not_active IP Right Cessation
- 2001-04-30 MY MYPI20012024A patent/MY126094A/en unknown
- 2001-05-01 JP JP2001134413A patent/JP2001358969A/ja not_active Withdrawn
- 2001-05-02 CN CNB011214961A patent/CN1204737C/zh not_active Expired - Fee Related
Patent Citations (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4414571A (en) | 1980-10-09 | 1983-11-08 | Matsushita Electric Industrial Co., Ltd. | Television receiver |
US4996596A (en) * | 1988-09-02 | 1991-02-26 | Sanyo Electric Co., Ltd. | Phase synchronizing circuit in video signal receiver and method of establishing phase synchronization |
US5289508A (en) | 1990-11-30 | 1994-02-22 | Fujitsu Limited | Clock information transmitting device and clock information receiving device |
US5459756A (en) | 1994-06-27 | 1995-10-17 | Motorola, Inc. | Sampling phase detector arrangement |
US5907364A (en) | 1995-05-29 | 1999-05-25 | Hitachi, Ltd. | Display device for information signals |
EP0779741A2 (en) | 1995-12-12 | 1997-06-18 | Thomson Consumer Electronics, Inc. | A method and apparatus for generating variable rate synchronization signals |
US6028641A (en) | 1996-06-03 | 2000-02-22 | Lg Electronics Inc. | Device and method for generating a stable system clock in HDTV |
US5796392A (en) | 1997-02-24 | 1998-08-18 | Paradise Electronics, Inc. | Method and apparatus for clock recovery in a digital display unit |
WO1999016243A1 (en) | 1997-09-26 | 1999-04-01 | Sarnoff Corporation | Synchronized multiple format video processing method and apparatus |
US6091304A (en) | 1998-09-22 | 2000-07-18 | Lg Information & Communications, Ltd. | Frequency band select phase lock loop device |
Non-Patent Citations (2)
Title |
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Copy of EPO Search Report. |
Fairchild Semiconductor Nov. 1983 CD4051BC CD4052BC CD4053BC Single 8-Channel Analog Multiplexer/Demultiplexer Dual 4-Channel Analog Multiplexer/Demultiplexer Triple 2-Channel Analog Multiplexer/Demultiplexer. |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030179318A1 (en) * | 2002-03-22 | 2003-09-25 | Mohammad Alkhalili | Self-adjusting pixel clock and method therefor |
US7136109B2 (en) * | 2002-03-22 | 2006-11-14 | Pelco | Self-adjusting pixel clock and method therefor |
US7522216B2 (en) * | 2005-09-20 | 2009-04-21 | National Semiconductor Corporation | Video synchronization signal detection circuit |
US20160351169A1 (en) * | 2015-05-27 | 2016-12-01 | Au Optronics Corporation | Source driving device, timing controlling device, method for receiving display signal and method for transmitting display signal |
US9865232B2 (en) * | 2015-05-27 | 2018-01-09 | Au Optronics Corp. | Source driving device, timing controlling device, method for receiving display signal and method for transmitting display signal |
Also Published As
Publication number | Publication date |
---|---|
KR20010100943A (ko) | 2001-11-14 |
EP1152601A2 (en) | 2001-11-07 |
CN1204737C (zh) | 2005-06-01 |
KR100673922B1 (ko) | 2007-01-25 |
CA2345559A1 (en) | 2001-11-02 |
CN1327342A (zh) | 2001-12-19 |
JP2001358969A (ja) | 2001-12-26 |
MY126094A (en) | 2006-09-29 |
CA2345559C (en) | 2009-03-24 |
EP1152601A3 (en) | 2003-03-26 |
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