US6487706B1 - Contract methodology for concurrent hierarchical design - Google Patents
Contract methodology for concurrent hierarchical design Download PDFInfo
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- US6487706B1 US6487706B1 US09/651,464 US65146400A US6487706B1 US 6487706 B1 US6487706 B1 US 6487706B1 US 65146400 A US65146400 A US 65146400A US 6487706 B1 US6487706 B1 US 6487706B1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/394—Routing
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- This invention relates to wiring design for VLSI chips, and particularly to a method for partitioning wiring resources for connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels of hierarchy.
- This disclosure describes a methodology for partitioning the wiring resource among individual physical elements of a hierarchical design in such a way as to allow the different elements (which can be at various levels of the hierarchy) to be physically wired concurrently while insuring that the overall complete design is free of shorts or other conflicts.
- the “wiring contract” is employed as a vehicle to pass wiring resource constraints across partitioned physical design elements as well as across the various levels of design hierarchy.
- our method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels begins by defining a size for the chip of a hierarchical design, and then removing blocked wiring areas, including clock and power grid areas, leaving the wiring channels available for interconnecting the individual elements of the VLSI chip.
- a percentage of the available area is allocated per wiring levels for global and local wiring as parallel iterations for the global and local wiring proceed and modified as the parallel iterations for the global and local wiring progress.
- the number of wires may increase for the power grid area to prevent a signal wire from having an “active” wire on either side of the signal wire.
- a vertical slice of the wiring resources used for the space above a macro entity is defined and the macro entity is checked with this context of the VLSI chip physical design above it.
- the process employs a blockage modeling tool to accurately wire DRC correct wiring designs using automatic routing tools.
- This blockage modeling tool handles the newer, more complex types of design ground rules, such as wire spacings that are functions of the wires′ widths or wire spacing to via junction that are dependent on both the metal extension beyond the via junction and the width of the covering metal. It adds artificial blockages to guide the routing tools to wire a design without shorts or DRC violations when these situations force the spacings to be more than the “absolute” minimum.
- FIG. 1 illustrates partitioning of a VLSI chip.
- FIG. 2 illustrates some of the “fixed” wiring constraints that need to be managed and passed to the various levels of hierarchy.
- FIG. 3 illustrates contracts generated for unit and chip levels of hierarchy (which are inverses of each other) to define regions where each level of hierarchy can and can't wire.
- FIG. 4 illustrates the wiring bays on two levels of metal.
- FIG. 5 illustrates a technique by which the electrical coupling between signal nets can be minimized by allocation of tracks adjacent to the power rails to the physical hierarchy level which will tend to have the longest wires.
- FIG. 6 illustrates a shadow generated for a specific macro design entity.
- FIG. 7 illustrates the modification of the blockage model for a shape in a macro to account for complex spacing ground rules.
- each partition has been partitioned into logical partitions (units) with each partition sized and assigned a non-overlapping region of the chip area (see FIG.- 1 ).
- Each partition in turn can be further partitioned into smaller elements (macros) and each of these partitions can be further partitioned into smaller elements until you have a physical hierarchy of “n” levels, where “n” can be any integer but is typically limited to the number of levels required reach a manageable size design entity.
- each partition has a physical representation, which we will henceforth refer to as an “autoAbstract”.
- This autoAbstract is an abstraction which contains a rectangle representing the physical size of this partition, plus terminal pins representing the physical connections to/from this partition.
- a chip floor plan has been created containing these units.
- FIG. 1 illustrates A VLSI chip partitioned into 4 units (labeled A,B,C,D) where each of the units is further partitioned into macros and each of the macros can be further partitioned into smaller elements until you have “n” levels of physical hierarchy.
- Each element at each level of hierarchy can theoretically be physically designed and implemented concurrently using the techniques in this invention to manage physical constraints between the levels.
- FIG. 2 illustrates some of the “fixed” wiring constraints that need to be managed and passed to the various levels of hierarchy.
- the chip level contains a power distribution grid that runs over the air-space of the partitioned units (labeled A,B,C,D).
- a power distribution contract for block “A” is generated using the contract methodology described in this invention.
- FIG. 3 illustrates contracts generated for unit and chip levels of hierarchy (which are inverses of each other) to define regions where each level of hierarchy can and can't wire.
- the chip level uses wiring tracks over the airspace of the partitioned unit block B to wire the nets defined by connections to terminals a 2 (on block A) and c 2 (on block C) as well as terminals d 3 (on block D) and c 1 (on block C).
- These net wiring implementations require that the chip view of the wiring contract contains “open” areas where the nets can be wired and the unit view of the wiring contract represent the inverse so that the unit does not wire in the chip's space.
- FIG. 4 illustrates the wiring bays on two levels of metal (labeled p,q).
- FIG. 5 illustrates a technique by which the electrical coupling between signal nets can be minimized by allocation of tracks adjacent to the power rails (Power and Ground rails) to the physical hierarchy level which will tend to have the longest wires.
- the wire tracks adjacent to the power rails are allocated to the chip level as illustrated in the chip view of contract.
- the wiring tracks that are not adjacent to the power rails are allocated to the unit partition as illustrated in the unit view of contract.
- FIG. 6 illustrates a shadow generated for a specific design entity (in this case macro E).
- This shadow is a vertical slice up thru all wiring planes and up thru all levels of hierarchy (in this case the unit and chip levels).
- the shadow contains all shapes in the vertical slice, illustrated as two net segments in this example.
- FIG. 7 illustrates the modification of the blockage model for a shape in macro Ml to account for complex spacing ground rules.
- the resulting spacing will meet the technology ground rule without complicating the wiring routine.
- Step 1) Size the resource allocation on each wiring layer. Considerations:
- Global wires should be assigned to the wiring layers of lower resistivity, as these wires tend to be longer than local wires, and hence more sensitive to RC delay and coupling effects.
- Wiring may have to be restricted on such layers, such as pre-wiring every third channel to the power grid (thus limiting the number of “active” neighboring wires to a maximum of one), and/or limiting the length of wires on these wiring layers.
- Step 2) This is the step of building chip/partition “contracts”.
- the power/clock grids cuts the chip into wiring bays of 10 channels each on a particular wiring layer.
- the percentage we wish to allocate to the chip on this particular layer is 60%. If we shrink the 10-channel bays by 60%, then we will have 4-channel bays representing the channels allocated for the partitions. After applying this technique on every wiring layer, we now have wiring bays for each layer reserved for the partitions, or an alternate way of saying it is that we have a blockage map of the channels where we cannot put global wires in the places where those channels intersects a partition.
- Step 3 a Our method for partitioning wiring connecting individual physical elements of a VLSI chip of a hierarchical design having multiple levels, begins by defining a size for the chip of a hierarchical design, and then removing blocked areas, including clock and power grid areas, leaving the wiring channels available for interconnecting the individual elements of the VLSI chip. A percentage of the available area is allocated for wiring levels for global and local wiring as parallel iterations for the global and local wiring proceed and modified as the parallel iterations for the global and local wiring progress. During the parallel iterative process we may also choose to change some of the available signal wiring channels into fixed power grid wires to increase the number of “quiet” wires on either side of the signal wires.
- the wire resource allocation defined in the wiring contracts were implemented in such a way as to reduce the coupled noise on the signal routes. This was done by taking into consideration the power distribution design and allocating the wiring track adjacent to the power distribution to the design entity which was expected to have the longest routes on that wiring level, i.e. for MQ wiring level the power distribution was defined such that 4 signal wiring tracks fit between power (VDD and GND) rails and, since the chip entity was expected to have longer routes then the unit entities, the contract was defined such that the 2 MQ tracks adjacent to power were allocated to the chip and 2 tracks not adjacent to power were allocated to unit (see FIG. 5 ). For the few cases where the chip wiring channel is used for a net highly sensitive to coupling, the adjacent unit wiring channel may be converted to a fixed power grid wire to reduce the coupling.
- Step 3 b In the interactive process, a vertical slice of wiring resources used for the space above a macro entity is defined and the macro entity is checked with the context of the VLSI chip physical design above it.
- the wiring contracts were also used to be able to perform quick physical design verification of the lower levels in the design hierarchy without having the entire design in place.
- a vertical slice of all the wiring resources used in the airspace of a macro entity as reflected in the wiring contracts for the unit and chip could be extracted and used for verification at the macro level (see FIG.- 6 ).
- Step 3 c The process employs a blockage modeling tool to accurately wire DRC correct wiring designs using automatic routing tools illustrated by the examples in the Figures.
- the blockage modeling tool keeps any adjacent wire at a spacing value greater that a minimum spacing away for a wire when the width of a wire is greater than a rule defined width. It also adds an artificial blockage to guide the routing tools to wire a design without shorts or DRC violations when there is a wide wire and its metal overlap past a via and its width is above a certain width and spaced less than a predetermined value from an adjacent wire on the same metal layer.
- the first example is when the width of a wire (such as power, clock, I/O, etc.) is greater than some value defined in the layout rules (see FIG.- 7 ). When this occurs, any adjacent wire must be kept some spacing value greater than the minimum spacing away. There are ranges of widths/spaces to which the design must adhere.
- the second example involves a metal overlap past a via requirement when the metal line is above a certain width and spaced less than some value from an adjacent wire on the same metal layer.
- the blockage modeling code will recognize the above situations (as well as many others) and add artificial blockages where required to guide the routing tools and ensure an error free design.
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US09/651,464 US6487706B1 (en) | 2000-08-30 | 2000-08-30 | Contract methodology for concurrent hierarchical design |
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Cited By (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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US6629306B2 (en) * | 2001-11-30 | 2003-09-30 | Sun Microsystems, Inc. | Signal routing based approach for increasing decoupling capacitance using preferential shielding |
US20030229862A1 (en) * | 2002-06-10 | 2003-12-11 | Sun Microsystems, Inc. | Patching technique for correction of minimum area and jog design rule violations |
US20040015797A1 (en) * | 2002-07-19 | 2004-01-22 | Micron Technology, Inc. | Line width check in layout database |
US20040019862A1 (en) * | 2002-07-23 | 2004-01-29 | Sun Microsystems, Inc. | Structure and method for separating geometries in a design layout into multi-wide object classes |
US20040064795A1 (en) * | 2002-09-30 | 2004-04-01 | Sun Microsystems, Inc. | Via enclosure rule check in a multi-wide object class design layout |
US20040064797A1 (en) * | 2002-09-30 | 2004-04-01 | Sun Microsystems, Inc. | Pure fill via area extraction in a multi-wide object class design layout |
US20040063228A1 (en) * | 2002-09-30 | 2004-04-01 | Sun Microsystems, Inc. | Redundant via rule check in a multi-wide object class design layout |
US20040064796A1 (en) * | 2002-09-30 | 2004-04-01 | Sun Microsystems, Inc. | Correction of spacing violations between pure fill via areas in a multi-wide object class design layout |
US20040255258A1 (en) * | 2003-06-13 | 2004-12-16 | Sun Microsystems, Inc. | Method, apparatus, and computer program product for generation of a via array within a fill area of a design layout |
US20050055654A1 (en) * | 2003-09-08 | 2005-03-10 | Jai-Ming Lin | Method for checking an IC layout |
US20060095870A1 (en) * | 2004-10-29 | 2006-05-04 | Synopsys, Inc. | Power network analyzer for an integrated circuit design |
US7096447B1 (en) | 2003-10-15 | 2006-08-22 | Sun Microsystems, Inc. | Method and apparatus for efficiently locating and automatically correcting certain violations in a complex existing circuit layout |
US7353490B2 (en) | 2004-10-29 | 2008-04-01 | Synopsys, Inc. | Power network synthesizer for an integrated circuit design |
US20080235647A1 (en) * | 2005-07-28 | 2008-09-25 | Harm Peter Hofstee | Modular design method and apparatus |
US20090037857A1 (en) * | 2007-07-30 | 2009-02-05 | International Business Machines Corporation | Methods for design rule checking with abstracted via obstructions |
US7536658B2 (en) | 2004-10-29 | 2009-05-19 | Synopsys, Inc. | Power pad synthesizer for an integrated circuit design |
US20090217227A1 (en) * | 2008-02-22 | 2009-08-27 | Dotson Michael W | Method and apparatus for parallel processing of semiconductor chip designs |
US20100058275A1 (en) * | 2008-08-29 | 2010-03-04 | International Business Machines Corporation | Top Level Hierarchy Wiring Via 1xN Compiler |
US20100077370A1 (en) * | 2008-09-23 | 2010-03-25 | Qualcomm Incorporated | System And Method Of Connecting A Macro Cell To A System Power Supply |
US20100122230A1 (en) * | 2008-11-13 | 2010-05-13 | Qualcomm Incorporated | Method to Automatically Add Power Line in Channel Between Macros |
US20110289468A1 (en) * | 2009-12-09 | 2011-11-24 | International Business Machines Corporation | Circuit Macro Placement Using Macro Aspect Ratio Based on Ports |
CN102622468A (en) * | 2012-02-20 | 2012-08-01 | 苏州领佰思自动化科技有限公司 | Method and system for large-scale integrated circuit channel wiring based on parallel computation |
US8316336B1 (en) * | 2006-04-13 | 2012-11-20 | Cadence Design Systems, Inc. | Method and mechanism for modeling interconnect structures for integrated circuits |
US20140344778A1 (en) * | 2013-05-17 | 2014-11-20 | Oracle International Corporation | System and method for code generation from a directed acyclic graph using knowledge modules |
CN104750886A (en) * | 2013-12-29 | 2015-07-01 | 北京华大九天软件有限公司 | Method for confirming pin access area in integrated circuit layout wiring |
CN104750885A (en) * | 2013-12-29 | 2015-07-01 | 北京华大九天软件有限公司 | Method for pre-distributing wiring resources for pins in integrated circuit layout wiring |
US9679099B2 (en) | 2015-07-01 | 2017-06-13 | International Business Machines Corporation | De-coupling capacitance placement |
US9910948B2 (en) | 2016-01-27 | 2018-03-06 | International Buisiness Machines Corporatoin | Layout of large block synthesis blocks in integrated circuits |
US10923425B2 (en) * | 2017-01-20 | 2021-02-16 | Arm Limited | Power distribution |
CN112632899A (en) * | 2020-12-30 | 2021-04-09 | 上海华大九天信息科技有限公司 | Wiring method for equalizing resistance |
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US10534884B2 (en) | 2016-01-27 | 2020-01-14 | International Business Machines Corporation | Layout of large block synthesis blocks in integrated circuits |
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CN112632899A (en) * | 2020-12-30 | 2021-04-09 | 上海华大九天信息科技有限公司 | Wiring method for equalizing resistance |
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