US6363464B1 - Redundant processor controlled system - Google Patents

Redundant processor controlled system Download PDF

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US6363464B1
US6363464B1 US09/414,915 US41491599A US6363464B1 US 6363464 B1 US6363464 B1 US 6363464B1 US 41491599 A US41491599 A US 41491599A US 6363464 B1 US6363464 B1 US 6363464B1
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processor
data
shadow
memory
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Michael T. Mangione
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Nokia of America Corp
Wsou Investments LLC
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Nokia of America Corp
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    • GPHYSICS
    • G06COMPUTING; CALCULATING; COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00Error detection; Error correction; Monitoring
    • G06F11/07Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16Error detection or correction of the data by redundancy in hardware
    • G06F11/20Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
    • G06F11/2097Error detection or correction of the data by redundancy in hardware using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements maintaining the standby controller/processing unit updated

Abstract

The operation of a shadow processor for a system having redundant controllers is arranged so that it receives a FIFO fill indicator from another shadow processor associated with that one of the controllers that is in a standby mode, and, if the value of the indicator reaches a predetermined value, then the shadow processor throttles the data writing activity of the active controller for an amount of time sufficient to allow the other shadow processor time to unload the FIFO below a particular fill level.

Description

FIELD OF THE INVENTION

The invention relates to systems employing active and standby processors, and more particularly relates to the writing of data from the active processor to the standby processor so that the latter processor may track accurately the activity of the former processor.

BACKGROUND OF THE INVENTION

Many different systems, e.g., computer processing systems, communication systems, etc., employ redundant system processors for reliability purposes. Typically, the processors are respectively designated the active and standby processors, in which the active processor controls the operation of the system and the standby processor monitors the health of the active processor. The standby processor assumes an active state whenever diagnostic processes indicate that the active processor is faulty. To help ensure that its transition from the standby state to the active state does not impact the system, the standby processor continually tracks the activity of the active processor. The standby processor does this by monitoring the writing of certain data pertaining to the system in memory, as is shown in FIG. 1.

In particular, operational system 300 includes, inter alia, the underlying system 250 whose operation is controlled by redundant controllers (processors) 100 and 200. Each of the controllers include, inter alia, a processor (105, 205), memory (110, 210) and shadow processor (120, 220). Assume that controllers 100 are respectively designated as active and standby. In the active state, shadow processor 120 monitors the data that system processor 105 writes into memory 110 via bus 115. If shadow processor 120 finds that data is being written into one of a predetermined group of memory 110 locations, then shadow processor 120 passes the write address and data to shadow processor 220 via path 121. The write address and data is loaded into a conventional FIFO within processor 220. Processor 220 unloads such data from its FIFO and stores it via bus 215 in a memory 210 location specified by the address accompanying the data. To do so, processor 220 must contend with system processor 205 for access to bus 215. If processor 205 is also contending for bus 215, and the active system processor 105 is storing an appreciable amount of data in the aforementioned group of memory 110 locations, then it is possible that shadow processor 220 might not be able to access bus 215 frequently enough to keep pace with the loading of shadow data in its FIFO. Consequently, data may be lost when the FIFO overflows, which would seriously impact the ability of standby controller 200 to track active controller 100.

SUMMARY OF THE INVENTION

I address the above problem and advance the relevant art by controlling the speed at which the active processor is writing data into the monitored memory locations whenever the number of memory locations containing unloaded data in the FIFO of the standby shadow processor reaches a predetermined level. In accordance with an aspect of the invention, the active processor monitors the number of locations of the standby FIFO that are filled and invokes such control when it detects that that number has reached the aforementioned predetermined level. In accordance with another aspect of the invention, the active shadow processor exercises such control by contending for access to the memory access bus and “holding” onto the bus for a brief period of time sufficient to allow the standby shadow processor enough time to unload its FIFO below a certain point.

These and other aspects of the claimed invention will be appreciated from the following detailed description read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWING

In the drawing:

FIG. 1 is broad block diagram of a prior system employing redundant controllers each having a shadow processor;

FIG. 2 is a broad block diagram of a system employing redundant controllers each having a shadow processor arranged in accordance with the principles of the invention;

FIG. 3 is a broad block diagram of a shadow processor of FIG. 2; and

FIG. 4 is a state diagram illustrating the operation of the shadow processor of FIG. 3 in accordance with the principles of the invention.

DETAILED DESCRIPTION

Each of the shadow processors 120 and 220, FIG. 2, when in the active mode, monitor the memory writing activity of its respective active system processor (105 or 205, as the case may be) in the manner discussed above.

When such activity indicates that the active system processor, e.g., system processor 105, is writing data into one of a predetermined group(s) of memory locations, then the associated active shadow processor, e.g., shadow processor 120, writes a copy of that data and accompanying write address in the input FIFO of the standby shadow processor, e.g., shadow processor 220, via path 121, as mentioned above. If the level of such activity is high—meaning that the active system processor is writing a large amount data into the group of memory location—then it is possible that the standby shadow processor might not be able to unload its input FIFO as fast as the active shadow processor is supplying data to that FIFO. In that event, the latter FlFO could overflow, thereby interrupting the ability of the standby system processor to accurately monitor the activity of the active system processor.

I address this problem by arranging the standby shadow processor so that it supplies the fill level of its input FIFO to the active shadow processor via FP path 221. When the fill level reaches a predetermined point, e.g., a point between half-full and fill, then the active shadow processor responds thereto by contending for access to the system bus, e.g., bus 115, in accordance with a conventional bus contention scheme. When it is granted such access, then the active shadow processor holds onto to the bus for a brief period of time as a way of controlling the memory writing activity of the active system processor, all in accordance with the principles of the invention. The brief period of time is sufficient to allow the standby shadow processor to unload its FIFO below a certain fill point, e.g., to half full.

In one illustrative embodiment of the invention, the active shadow processor repeatedly accesses the system bus for a very brief period of time until the fill indicator on the FP path indicates that the number of input memory locations containing data in the FIFO of the standby shadow has decreased substantially below the aforementioned predetermined point, e.g., from three-quarters full to half full.

For the sake of simplicity and clarity, the following first discusses the operation the active shadow processor and then discusses the standby shadow processor. It is to be understood of course that any discussion relating to the active shadow processor pertains equally well to the standby shadow processor and vice-versa.

Turning then to FIG. 3, shadow memory control 120-5, which may be, for example, a Field Programmable Gate Array (FPGA) 120-5, continuously monitors the data writes performed by its associated active system processor 105. Shadow memory control 120-5 does by monitoring the address portion of its associated system memory read/write bus, e.g., bus 115 of FIG. 2, via path 120-15. When the active system processor 105 places a write address on bus 115, then memory control 120-5 checks to see if that memory address is within a range(s) of addresses stored in its internal memory region table 120-10. Memory control 120-5 does this to determine if the ensuing memory write needs to be shadowed. If the address is not within the range(s) of such addresses, then memory control 120-5 disregards the active system processor memory write operation. Otherwise, shadow memory control 120-5 writes a copy of the address and associated controls signals (I.E., a FIFO clock enable on path 121-2 and FIFO clock signal on path 121-3) onto path 121. Memory control 120-5 then waits for the active processor to place the data that is to be written into the identified memory location onto the data leads of bus 115. When the active processor does so, then memory control 120-5 obtains a copy of the data via bus 120-20 connected to the data leads of bus 115. Memory control 120-5 stores the copied data in data register 120-25 and then writes it into the FIFO 120-40 of the standby shadow processor along with the accompanying write address via path 121.

(As an aside, the active processor may change the range(s) of addresses stored in table 120-10 of both the active and standby shadow processor by activating control enable 120-33, addressing each such table via slave address bus 120-31 and overwriting the data contained in the tables using slave data bus 120-32.)

The active shadow processor receives the “fill” indicator/pointer for the input FIFO of the standby shadow processor via path 221, as mentioned above. In one illustrative embodiment of the invention, path 221 is formed by, e.g., three leads. The levels of the signals on path 221 indicate when the standby FIFO is at least three-quarters full (100), at least half-full (001) and less than half-full (000). As discussed above, the active shadow processor controls the data writing activity of the active system processor as a function of the signals on path/bus 221. To say it another way, the active shadow processor throttles the activity on bus 115 responsive to the levels of the signals on path 221.

More specifically, and also referring to the state diagram shown in FIG. 4, the active shadow processor remains in a throttle idle state 401 as long as the standby FIFO is less than half full, as indicated by the 000 state on path 221 (hereinafter also referred to as the FIFO flag). The active shadow processor advances (jumps) to a throttle state 402 when the levels of the signals characterizing the FIFO flag change to 100, indicating that the standby FIFO is at least three-quarters full. The active shadow processor then advances to a bus request state 403, where it contends in a conventional manner for access to the active bus, e.g., bus 115, via bus control signal path 120-45. When it is granted such access, as represented by state 404, then the active shadow processor holds the bus for predetermined period of time characterized by a predetermined number of system clock cycles, e.g., 250 clock cycles. At the end of the latter period of time, the active shadow processor relinquishes its control of system bus 115 and returns to throttle state 402. At state 402, the active shadow processor returns to Idle state 401 if the standby FIFO flag indicates that standby FFO is less than half full. Otherwise, the active shadow processor advances to state 403 to continue such throttling by once again contending for access to system bus 115.

Turning now to a discussion of the operation of the standby shadow processor, the active shadow processor, as mentioned above, writes data and accompanying addresses into standby FIFO 120-40. In an illustrative embodiment of the invention, FIFO 120-40 may comprise, e.g., 4000 memory locations, each location having at least 81 bits. Standby FIFO 120-40 changes the state of FIFO flag 221 accordingly when data is written into the FIFO. The standby shadow memory control 120-5 monitors the state of the FIFO flag via path 120-42. When the state of the flag goes non-empty (001), then the standby shadow memory control 120-5 unloads the data and accompanying address out of the standby FIFO 120-40. If the unloaded address falls within the range of addresses stored in table 120-10, then the standby memory control 120-5 acquires access to bus 215 and stores the unloaded data in memory 210, FIG. 2, at a location specified by the unloaded address. The standby shadow processor does this by placing the unloaded address onto bus 120-15 and then placing the unloaded data onto bus 120-20 along with the necessary control signals. Note that standby shadow control 120-5 discards the data and accompanying address if the address is not valid.

It will thus be appreciated that, although the invention illustrated herein is described in the context of a specific illustrative embodiment, those skilled in the art will be able to devise numerous alternative arrangements which, although, not explicitly shown or described herein, nevertheless, embody the principles of the invention and are within its spirit and scope.

Claims (10)

I claim:
1. A system having first and second controllers respectively operating at a given point in time as active and standby controllers, each of said first and second controllers comprising
a system processor, FIFO memory associated with said system processor, a shadow processor, said system processor, memory and shadow processor connected via a system bus;
wherein the system processor of the active controller writes data into its associated FIFO memory;
wherein the shadow processor of the active controller continuously monitors said data writes performed by its associated active system processor;
wherein the shadow processor writes a copy of said data and accompanying write memory address into the input FIFO of the shadow processor of the standby controller via said data pathway;
wherein the shadow processor of the standby controller supplies the fill level of its input FIFO to the shadow processor of the active controller; and
when said fill level reaches a first predetermined value, the active shadow processor responds thereto by decreasing the rate at which the active processor is writing data into the system memory, until such time the standby shadow processor unloads its fill level below a second predetermined value.
2. The system of claim 1 wherein the first predetermined value indicates that the FIFO memory of the other shadow processor is at least three-quarters full and the second predetermined value indicates that the FIFO memory of the other shadow processor is less than half full.
3. The system of claim 1 further comprising
a bus for writing data into the system memory, and wherein the control apparatus performs such decreasing by accessing said bus for a predetermined period of time and repeating such accessing until the number indicator reaches said second predetermined value.
4. The system of claim 1 wherein the control apparatus includes apparatus for unloading the data and system memory address from the associated FIFO and, if the system memory address is within a predetermined range of such addresses, for then storing the data in another system memory at a location specified by the system memory address, otherwise discarding the data.
5. A shadow processor for a system having redundant controllers, in which each of said redundant controllers having a shadow processor and being operative for writing system data into respective system memories, said shadow controller comprising
means for receiving an indicator from another shadow processor associated with that one of the controllers that is in a standby mode; and
means, responsive to the indicator reaching a first predetermined value, for controlling the data writing activity of the other one of the controllers and continuing such control until the value of the indicator decreases to a second predetermined value.
6. A shadow processor for a system having redundant controllers, each of said redundant controllers having a shadow processor and being operative for writing system data into respective system memories, said shadow controller comprising
a FIFO memory of a predetermined number of memory locations, in which each said FIFO memory includes an indicator to indicate the number of such memory locations that contain data;
means, for receiving the indicator from another shadow processor associated with that one of the controllers that is in a standby mode, and control apparatus operative when the respective one of said redundant controllers is active and is writing data into at least one of a predetermined range of memory locations and passing the data and memory address of the data into the FIFO memory of the other shadow processor, and for controlling the rate at which the active controller is writing data into the system memory as a function of the value of said indicator.
7. The shadow processor of claim 6 wherein said system includes
a bus for writing data into the system memory, and wherein the control apparatus performs such controlling by decreasing the rate at which the active one of the controllers accesses the system memory via said bus.
8. The shadow processor of claim 6 wherein the FIFO memory includes apparatus to indicate by way of said indicator the number of FIFO memory locations that contain data.
9. A method of operating a shadow processor comprising the steps of
(a) remaining in an idle state as long as a FIFO fill indicator supplied by another shadow processor is below a first predetermined value;
(b) contending for access to a system bus when the FIFO fill indicator reaches or exceeds the first predetermined value, and holding onto to the system bus for a predetermined period of time and then relinquishing such access;
(c) repeating step (b) until the FIFO fill indicator decreases to a second predetermined value, and then returning to step (a).
10. A method of operating a shadow processor within a system having redundant controllers, in which each of the redundant controllers is operative for writing system data into respective system memories, said method comprising the steps of,
receiving an indicator from another shadow processor associated with that one of the controllers that is in a standby mode; and
responsive to the indicator reaching a first predetermined value, controlling the data writing activity of the other one of the controllers and continuing such control until the value of the indicator decreases to a second predetermined value.
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Cited By (46)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020073288A1 (en) * 2000-12-07 2002-06-13 Lg Electronics Inc. Apparatus and method for verifyng memory coherency of duplication processor
US6625750B1 (en) * 1999-11-16 2003-09-23 Emc Corporation Hardware and software failover services for a file server
US6934898B1 (en) * 2001-11-30 2005-08-23 Koninklijke Philips Electronics N.V. Test circuit topology reconfiguration and utilization techniques
US20050210191A1 (en) * 2004-03-17 2005-09-22 Naotaka Kobayashi Storage control system and control method for storage control system
US7028218B2 (en) 2002-12-02 2006-04-11 Emc Corporation Redundant multi-processor and logical processor configuration for a file server
US20070113224A1 (en) * 2005-07-05 2007-05-17 Viasat, Inc. Task Matching For Coordinated Circuits
US20070113230A1 (en) * 2005-07-05 2007-05-17 Viasat, Inc. Synchronized High-Assurance Circuits
US20070186068A1 (en) * 2005-12-19 2007-08-09 Agrawal Vijay H Network redirector systems and methods for performing data replication
US20070183224A1 (en) * 2005-12-19 2007-08-09 Andrei Erofeev Buffer configuration for a data replication system
US20070186020A1 (en) * 2006-02-06 2007-08-09 Standard Microsystems Corporation Method for changing ownership of a bus between master/slave devices
US20070198602A1 (en) * 2005-12-19 2007-08-23 David Ngo Systems and methods for resynchronizing information
US20070245141A1 (en) * 2005-07-05 2007-10-18 Viasat, Inc. Trusted Cryptographic Processor
EP1907937A2 (en) * 2005-07-05 2008-04-09 ViaSat, Inc. Synchronized high-assurance circuits
US20080275828A1 (en) * 2007-05-03 2008-11-06 Payton David W Method and system for independently observing and modifying the activity of an actor processor
US20090012828A1 (en) * 2007-03-09 2009-01-08 Commvault Systems, Inc. Computer systems and methods for workflow automation
US20090182963A1 (en) * 2003-11-13 2009-07-16 Anand Prahlad System and method for performing a snapshot and for restoring data
US20090230255A1 (en) * 2008-03-11 2009-09-17 Lemonovich John E Cab signal receiver demodulator employing redundant, diverse field programmable gate arrays
US20100049753A1 (en) * 2005-12-19 2010-02-25 Commvault Systems, Inc. Systems and methods for monitoring application data in a data replication system
US20100082541A1 (en) * 2005-12-19 2010-04-01 Commvault Systems, Inc. Systems and methods for performing replication copy storage operations
US20100094808A1 (en) * 2005-12-19 2010-04-15 Commvault Systems, Inc. Pathname translation in a data replication system
US20100122053A1 (en) * 2005-12-19 2010-05-13 Commvault Systems, Inc. Systems and methods for performing data replication
US20100179941A1 (en) * 2008-12-10 2010-07-15 Commvault Systems, Inc. Systems and methods for performing discrete data replication
US20110238621A1 (en) * 2010-03-29 2011-09-29 Commvault Systems, Inc. Systems and methods for selective data replication
CN102448823A (en) * 2009-06-12 2012-05-09 波音公司 Method and apparatus for wireless aircraft communications using fuselage stringers
US8204859B2 (en) 2008-12-10 2012-06-19 Commvault Systems, Inc. Systems and methods for managing replicated database data
US8352422B2 (en) 2010-03-30 2013-01-08 Commvault Systems, Inc. Data restore systems and methods in a replication environment
US20130163445A1 (en) * 2011-12-22 2013-06-27 Partha Majumdar Testing TCP Connection Rate
US8489656B2 (en) 2010-05-28 2013-07-16 Commvault Systems, Inc. Systems and methods for performing data replication
US8504515B2 (en) 2010-03-30 2013-08-06 Commvault Systems, Inc. Stubbing systems and methods in a data replication environment
US20130318263A1 (en) * 2012-05-24 2013-11-28 Infineon Technologies Ag System and Method to Transmit Data over a Bus System
US8726242B2 (en) 2006-07-27 2014-05-13 Commvault Systems, Inc. Systems and methods for continuous data replication
US8725698B2 (en) 2010-03-30 2014-05-13 Commvault Systems, Inc. Stub file prioritization in a data replication system
US9262435B2 (en) 2013-01-11 2016-02-16 Commvault Systems, Inc. Location-based data synchronization management
US9298715B2 (en) 2012-03-07 2016-03-29 Commvault Systems, Inc. Data storage system utilizing proxy device for storage operations
US9342537B2 (en) 2012-04-23 2016-05-17 Commvault Systems, Inc. Integrated snapshot interface for a data storage system
US9448731B2 (en) 2014-11-14 2016-09-20 Commvault Systems, Inc. Unified snapshot storage management
US9471578B2 (en) 2012-03-07 2016-10-18 Commvault Systems, Inc. Data storage system utilizing proxy device for storage operations
US9495251B2 (en) 2014-01-24 2016-11-15 Commvault Systems, Inc. Snapshot readiness checking and reporting
US9632874B2 (en) 2014-01-24 2017-04-25 Commvault Systems, Inc. Database application backup in single snapshot for multiple applications
US9639426B2 (en) 2014-01-24 2017-05-02 Commvault Systems, Inc. Single snapshot for multiple applications
US9648105B2 (en) 2014-11-14 2017-05-09 Commvault Systems, Inc. Unified snapshot storage management, using an enhanced storage manager and enhanced media agents
US9753812B2 (en) 2014-01-24 2017-09-05 Commvault Systems, Inc. Generating mapping information for single snapshot for multiple applications
GB2547914A (en) * 2016-03-02 2017-09-06 Advanced Risc Mach Ltd Data processing systems
US9774672B2 (en) 2014-09-03 2017-09-26 Commvault Systems, Inc. Consolidated processing of storage-array commands by a snapshot-control media agent
US9886346B2 (en) 2013-01-11 2018-02-06 Commvault Systems, Inc. Single snapshot for multiple agents
US10042716B2 (en) 2014-09-03 2018-08-07 Commvault Systems, Inc. Consolidated processing of storage-array commands using a forwarder media agent in conjunction with a snapshot-control media agent

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5434998A (en) * 1988-04-13 1995-07-18 Yokogawa Electric Corporation Dual computer system
US5473756A (en) * 1992-12-30 1995-12-05 Intel Corporation FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers
US5838894A (en) * 1992-12-17 1998-11-17 Tandem Computers Incorporated Logical, fail-functional, dual central processor units formed from three processor units

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5434998A (en) * 1988-04-13 1995-07-18 Yokogawa Electric Corporation Dual computer system
US5838894A (en) * 1992-12-17 1998-11-17 Tandem Computers Incorporated Logical, fail-functional, dual central processor units formed from three processor units
US5473756A (en) * 1992-12-30 1995-12-05 Intel Corporation FIFO buffer with full/empty detection by comparing respective registers in read and write circular shift registers

Cited By (115)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6625750B1 (en) * 1999-11-16 2003-09-23 Emc Corporation Hardware and software failover services for a file server
US6871102B2 (en) * 2000-12-07 2005-03-22 Lg Electronics Inc. Apparatus and method for verifying memory coherency of duplication processor
US20020073288A1 (en) * 2000-12-07 2002-06-13 Lg Electronics Inc. Apparatus and method for verifyng memory coherency of duplication processor
US6934898B1 (en) * 2001-11-30 2005-08-23 Koninklijke Philips Electronics N.V. Test circuit topology reconfiguration and utilization techniques
US7028218B2 (en) 2002-12-02 2006-04-11 Emc Corporation Redundant multi-processor and logical processor configuration for a file server
US20090182963A1 (en) * 2003-11-13 2009-07-16 Anand Prahlad System and method for performing a snapshot and for restoring data
US9405631B2 (en) 2003-11-13 2016-08-02 Commvault Systems, Inc. System and method for performing an image level snapshot and for restoring partial volume data
US8195623B2 (en) 2003-11-13 2012-06-05 Commvault Systems, Inc. System and method for performing a snapshot and for restoring data
US9208160B2 (en) 2003-11-13 2015-12-08 Commvault Systems, Inc. System and method for performing an image level snapshot and for restoring partial volume data
US20110066599A1 (en) * 2003-11-13 2011-03-17 Commvault Systems, Inc. System and method for performing an image level snapshot and for restoring partial volume data
US8886595B2 (en) 2003-11-13 2014-11-11 Commvault Systems, Inc. System and method for performing an image level snapshot and for restoring partial volume data
US8645320B2 (en) 2003-11-13 2014-02-04 Commvault Systems, Inc. System and method for performing an image level snapshot and for restoring partial volume data
US8190565B2 (en) 2003-11-13 2012-05-29 Commvault Systems, Inc. System and method for performing an image level snapshot and for restoring partial volume data
US9619341B2 (en) 2003-11-13 2017-04-11 Commvault Systems, Inc. System and method for performing an image level snapshot and for restoring partial volume data
US20070101059A1 (en) * 2004-03-17 2007-05-03 Naotaka Kobayashi Storage control system and control method for storage control which suppress the amount of power consumed by the storage control system
US7171524B2 (en) * 2004-03-17 2007-01-30 Hitachi, Ltd. Storage control system and control method for storage control which suppress the amount of power consumed by the storage control system
US20050210191A1 (en) * 2004-03-17 2005-09-22 Naotaka Kobayashi Storage control system and control method for storage control system
EP3447675A1 (en) * 2005-07-05 2019-02-27 ViaSat Inc. Trusted cryptographic processor
US20070245141A1 (en) * 2005-07-05 2007-10-18 Viasat, Inc. Trusted Cryptographic Processor
US8190877B2 (en) 2005-07-05 2012-05-29 Viasat, Inc. Trusted cryptographic processor
EP1907937A2 (en) * 2005-07-05 2008-04-09 ViaSat, Inc. Synchronized high-assurance circuits
US20070113230A1 (en) * 2005-07-05 2007-05-17 Viasat, Inc. Synchronized High-Assurance Circuits
US20070113224A1 (en) * 2005-07-05 2007-05-17 Viasat, Inc. Task Matching For Coordinated Circuits
US7802075B2 (en) 2005-07-05 2010-09-21 Viasat, Inc. Synchronized high-assurance circuits
EP1907937A4 (en) * 2005-07-05 2010-01-13 Viasat Inc Synchronized high-assurance circuits
US8527741B2 (en) 2005-07-05 2013-09-03 Viasat, Inc. System for selectively synchronizing high-assurance software tasks on multiple processors at a software routine level
US9002799B2 (en) 2005-12-19 2015-04-07 Commvault Systems, Inc. Systems and methods for resynchronizing information
US20100094808A1 (en) * 2005-12-19 2010-04-15 Commvault Systems, Inc. Pathname translation in a data replication system
US9298382B2 (en) 2005-12-19 2016-03-29 Commvault Systems, Inc. Systems and methods for performing replication copy storage operations
US7870355B2 (en) * 2005-12-19 2011-01-11 Commvault Systems, Inc. Log based data replication system with disk swapping below a predetermined rate
US20100082541A1 (en) * 2005-12-19 2010-04-01 Commvault Systems, Inc. Systems and methods for performing replication copy storage operations
US20100049753A1 (en) * 2005-12-19 2010-02-25 Commvault Systems, Inc. Systems and methods for monitoring application data in a data replication system
US7962709B2 (en) 2005-12-19 2011-06-14 Commvault Systems, Inc. Network redirector systems and methods for performing data replication
US7962455B2 (en) 2005-12-19 2011-06-14 Commvault Systems, Inc. Pathname translation in a data replication system
US8024294B2 (en) 2005-12-19 2011-09-20 Commvault Systems, Inc. Systems and methods for performing replication copy storage operations
US9208210B2 (en) 2005-12-19 2015-12-08 Commvault Systems, Inc. Rolling cache configuration for a data replication system
US8121983B2 (en) 2005-12-19 2012-02-21 Commvault Systems, Inc. Systems and methods for monitoring application data in a data replication system
US9020898B2 (en) 2005-12-19 2015-04-28 Commvault Systems, Inc. Systems and methods for performing data replication
US20100100529A1 (en) * 2005-12-19 2010-04-22 Commvault Systems, Inc. Rolling cache configuration for a data replication system
US9639294B2 (en) 2005-12-19 2017-05-02 Commvault Systems, Inc. Systems and methods for performing data replication
US9971657B2 (en) 2005-12-19 2018-05-15 Commvault Systems, Inc. Systems and methods for performing data replication
US20070198602A1 (en) * 2005-12-19 2007-08-23 David Ngo Systems and methods for resynchronizing information
US8935210B2 (en) 2005-12-19 2015-01-13 Commvault Systems, Inc. Systems and methods for performing replication copy storage operations
US20070183224A1 (en) * 2005-12-19 2007-08-09 Andrei Erofeev Buffer configuration for a data replication system
US8285684B2 (en) 2005-12-19 2012-10-09 Commvault Systems, Inc. Systems and methods for performing data replication
US20070186068A1 (en) * 2005-12-19 2007-08-09 Agrawal Vijay H Network redirector systems and methods for performing data replication
US8793221B2 (en) 2005-12-19 2014-07-29 Commvault Systems, Inc. Systems and methods for performing data replication
US8725694B2 (en) 2005-12-19 2014-05-13 Commvault Systems, Inc. Systems and methods for performing replication copy storage operations
US8463751B2 (en) 2005-12-19 2013-06-11 Commvault Systems, Inc. Systems and methods for performing replication copy storage operations
US8656218B2 (en) 2005-12-19 2014-02-18 Commvault Systems, Inc. Memory configuration for data replication system including identification of a subsequent log entry by a destination computer
US8655850B2 (en) 2005-12-19 2014-02-18 Commvault Systems, Inc. Systems and methods for resynchronizing information
US20100122053A1 (en) * 2005-12-19 2010-05-13 Commvault Systems, Inc. Systems and methods for performing data replication
US8271830B2 (en) 2005-12-19 2012-09-18 Commvault Systems, Inc. Rolling cache configuration for a data replication system
US20070186020A1 (en) * 2006-02-06 2007-08-09 Standard Microsystems Corporation Method for changing ownership of a bus between master/slave devices
US8185680B2 (en) * 2006-02-06 2012-05-22 Standard Microsystems Corporation Method for changing ownership of a bus between master/slave devices
US9003374B2 (en) 2006-07-27 2015-04-07 Commvault Systems, Inc. Systems and methods for continuous data replication
US8726242B2 (en) 2006-07-27 2014-05-13 Commvault Systems, Inc. Systems and methods for continuous data replication
US8290808B2 (en) 2007-03-09 2012-10-16 Commvault Systems, Inc. System and method for automating customer-validated statement of work for a data storage environment
US20090012828A1 (en) * 2007-03-09 2009-01-08 Commvault Systems, Inc. Computer systems and methods for workflow automation
US8799051B2 (en) 2007-03-09 2014-08-05 Commvault Systems, Inc. System and method for automating customer-validated statement of work for a data storage environment
US8428995B2 (en) 2007-03-09 2013-04-23 Commvault Systems, Inc. System and method for automating customer-validated statement of work for a data storage environment
US7877347B2 (en) 2007-05-03 2011-01-25 Payton David W Method and system for independently observing and modifying the activity of an actor processor
US20080275828A1 (en) * 2007-05-03 2008-11-06 Payton David W Method and system for independently observing and modifying the activity of an actor processor
US7850127B2 (en) * 2008-03-11 2010-12-14 Ansaldo Sts Usa, Inc. Cab signal receiver demodulator employing redundant, diverse field programmable gate arrays
US20090230255A1 (en) * 2008-03-11 2009-09-17 Lemonovich John E Cab signal receiver demodulator employing redundant, diverse field programmable gate arrays
US9047357B2 (en) 2008-12-10 2015-06-02 Commvault Systems, Inc. Systems and methods for managing replicated database data in dirty and clean shutdown states
US8666942B2 (en) 2008-12-10 2014-03-04 Commvault Systems, Inc. Systems and methods for managing snapshots of replicated databases
US9396244B2 (en) 2008-12-10 2016-07-19 Commvault Systems, Inc. Systems and methods for managing replicated database data
US20100179941A1 (en) * 2008-12-10 2010-07-15 Commvault Systems, Inc. Systems and methods for performing discrete data replication
US9495382B2 (en) 2008-12-10 2016-11-15 Commvault Systems, Inc. Systems and methods for performing discrete data replication
US8204859B2 (en) 2008-12-10 2012-06-19 Commvault Systems, Inc. Systems and methods for managing replicated database data
CN102448823B (en) * 2009-06-12 2015-06-10 波音公司 Method and apparatus for wireless aircraft communications using fuselage stringers
CN102448823A (en) * 2009-06-12 2012-05-09 波音公司 Method and apparatus for wireless aircraft communications using fuselage stringers
US8868494B2 (en) 2010-03-29 2014-10-21 Commvault Systems, Inc. Systems and methods for selective data replication
US8504517B2 (en) 2010-03-29 2013-08-06 Commvault Systems, Inc. Systems and methods for selective data replication
US20110238621A1 (en) * 2010-03-29 2011-09-29 Commvault Systems, Inc. Systems and methods for selective data replication
US8504515B2 (en) 2010-03-30 2013-08-06 Commvault Systems, Inc. Stubbing systems and methods in a data replication environment
US8352422B2 (en) 2010-03-30 2013-01-08 Commvault Systems, Inc. Data restore systems and methods in a replication environment
US9002785B2 (en) 2010-03-30 2015-04-07 Commvault Systems, Inc. Stubbing systems and methods in a data replication environment
US9483511B2 (en) 2010-03-30 2016-11-01 Commvault Systems, Inc. Stubbing systems and methods in a data replication environment
US8725698B2 (en) 2010-03-30 2014-05-13 Commvault Systems, Inc. Stub file prioritization in a data replication system
US8589347B2 (en) 2010-05-28 2013-11-19 Commvault Systems, Inc. Systems and methods for performing data replication
US8745105B2 (en) 2010-05-28 2014-06-03 Commvault Systems, Inc. Systems and methods for performing data replication
US8489656B2 (en) 2010-05-28 2013-07-16 Commvault Systems, Inc. Systems and methods for performing data replication
US8572038B2 (en) 2010-05-28 2013-10-29 Commvault Systems, Inc. Systems and methods for performing data replication
US20130163445A1 (en) * 2011-12-22 2013-06-27 Partha Majumdar Testing TCP Connection Rate
US8717925B2 (en) * 2011-12-22 2014-05-06 Ixia Testing TCP connection rate
US9928146B2 (en) 2012-03-07 2018-03-27 Commvault Systems, Inc. Data storage system utilizing proxy device for storage operations
US9471578B2 (en) 2012-03-07 2016-10-18 Commvault Systems, Inc. Data storage system utilizing proxy device for storage operations
US9298715B2 (en) 2012-03-07 2016-03-29 Commvault Systems, Inc. Data storage system utilizing proxy device for storage operations
US9898371B2 (en) 2012-03-07 2018-02-20 Commvault Systems, Inc. Data storage system utilizing proxy device for storage operations
US9342537B2 (en) 2012-04-23 2016-05-17 Commvault Systems, Inc. Integrated snapshot interface for a data storage system
US9928002B2 (en) 2012-04-23 2018-03-27 Commvault Systems, Inc. Integrated snapshot interface for a data storage system
US10142124B2 (en) * 2012-05-24 2018-11-27 Infineon Technologies Ag System and method to transmit data over a bus system
US20130318263A1 (en) * 2012-05-24 2013-11-28 Infineon Technologies Ag System and Method to Transmit Data over a Bus System
US9262435B2 (en) 2013-01-11 2016-02-16 Commvault Systems, Inc. Location-based data synchronization management
US9430491B2 (en) 2013-01-11 2016-08-30 Commvault Systems, Inc. Request-based data synchronization management
US9336226B2 (en) 2013-01-11 2016-05-10 Commvault Systems, Inc. Criteria-based data synchronization management
US9886346B2 (en) 2013-01-11 2018-02-06 Commvault Systems, Inc. Single snapshot for multiple agents
US9495251B2 (en) 2014-01-24 2016-11-15 Commvault Systems, Inc. Snapshot readiness checking and reporting
US10223365B2 (en) 2014-01-24 2019-03-05 Commvault Systems, Inc. Snapshot readiness checking and reporting
US9892123B2 (en) 2014-01-24 2018-02-13 Commvault Systems, Inc. Snapshot readiness checking and reporting
US9632874B2 (en) 2014-01-24 2017-04-25 Commvault Systems, Inc. Database application backup in single snapshot for multiple applications
US9753812B2 (en) 2014-01-24 2017-09-05 Commvault Systems, Inc. Generating mapping information for single snapshot for multiple applications
US9639426B2 (en) 2014-01-24 2017-05-02 Commvault Systems, Inc. Single snapshot for multiple applications
US9774672B2 (en) 2014-09-03 2017-09-26 Commvault Systems, Inc. Consolidated processing of storage-array commands by a snapshot-control media agent
US10042716B2 (en) 2014-09-03 2018-08-07 Commvault Systems, Inc. Consolidated processing of storage-array commands using a forwarder media agent in conjunction with a snapshot-control media agent
US10044803B2 (en) 2014-09-03 2018-08-07 Commvault Systems, Inc. Consolidated processing of storage-array commands by a snapshot-control media agent
US9921920B2 (en) 2014-11-14 2018-03-20 Commvault Systems, Inc. Unified snapshot storage management, using an enhanced storage manager and enhanced media agents
US9996428B2 (en) 2014-11-14 2018-06-12 Commvault Systems, Inc. Unified snapshot storage management
US9648105B2 (en) 2014-11-14 2017-05-09 Commvault Systems, Inc. Unified snapshot storage management, using an enhanced storage manager and enhanced media agents
US9448731B2 (en) 2014-11-14 2016-09-20 Commvault Systems, Inc. Unified snapshot storage management
GB2547914B (en) * 2016-03-02 2018-05-09 Advanced Risc Mach Ltd Data processing systems
GB2547914A (en) * 2016-03-02 2017-09-06 Advanced Risc Mach Ltd Data processing systems
US10210595B2 (en) 2016-03-02 2019-02-19 Arm Limited Producing and using data according to first and second different patterns in data processing systems

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