US6258672B1 - Method of fabricating an ESD protection device - Google Patents

Method of fabricating an ESD protection device Download PDF

Info

Publication number
US6258672B1
US6258672B1 US09/252,630 US25263099A US6258672B1 US 6258672 B1 US6258672 B1 US 6258672B1 US 25263099 A US25263099 A US 25263099A US 6258672 B1 US6258672 B1 US 6258672B1
Authority
US
United States
Prior art keywords
semiconductor substrate
source
esd
esd protection
parasitic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US09/252,630
Inventor
Jiaw-Ren Shih
Jian-Hsing Lee
Huey-Liang Hwang
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority to US09/252,630 priority Critical patent/US6258672B1/en
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY reassignment TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HWANG, HUEY-LIANG, LEE, JIAN-HSING, SHIH, JIAW-REN
Priority to US09/709,597 priority patent/US6441438B1/en
Application granted granted Critical
Publication of US6258672B1 publication Critical patent/US6258672B1/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H01L27/027—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements specially adapted to provide an electrical current path other than the field effect induced current path
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • This invention is related to the protection of integrated circuits on a semiconductor substrate from voltage overstress due to pulses resulting from electrostatic discharge (ESD). More particularly, this invention is related to semiconductor devices and structures for improved protection of the integrated circuits.
  • FIG. 1 a the N-channel metal oxide semiconductor (NMOS) field effect transistor (FET) 100 of the prior art is shown in an application, wherein it is configured as an ESD protection circuit.
  • the drain of the NMOS FET 100 is connected to the input pad 115 , the drain of the P-channel Metal Oxide Semiconductor (PMOS) FET 200 , and to the internal circuits 110 .
  • the source and the gate of the PMOS FET 200 are connected to the voltage supply VDD.
  • the source and gate of the NMOS FET 100 are connected to the substrate biasing voltage source Vss.
  • the collectors of the parasitic bipolar junction transistors (BJT's) 140 a , 140 b , 140 c , 140 d are structurally the drain of the NMOS FET 100 .
  • the emitters of the parasitic BJT's 140 a , 140 b , 140 c , 140 d are structurally the source of the NMOS FET 100 which is connected to the substrate biasing voltage source Vss.
  • the bases of the parasitic BJT's 140 a , 140 b , 140 c , 140 d are structurally the channel region of the NMOS FET 100 are connected to the parasitic resistors 145 a , 145 b , 145 c , 145 d that is formed by the bulk resistance of the semiconductor substrate.
  • the parasitic resistors 145 a , 145 b , 145 c , 145 d , and 150 a , 150 b , 150 c , 150 d form a resistive network connected to the ground reference.
  • a positive ESD source 120 such as the human body or electrostatically charged machinery is momentarily coupled to the input/output pad 115 .
  • the magnitude of a voltage pulse of the ESD source 120 is on the order of 1,000 volts or larger.
  • the gate to drain voltage of the NMOS FET 100 is exceeds the breakdown voltage.
  • the drain to the substrate junction starts to enter the avalanche breakdown condition and then starts to generate large amounts of electron - hole pairs.
  • the holes pass through the substrate bulk resistances 145 a , 145 b , 145 c , 145 d , and 150 a , 150 b , 150 c , 150 d .
  • the voltage drop across the substrate bulk resistances 145 a , 145 b , 145 c , 145 d , and 150 a , 150 b , 150 c , 150 d forward bias the source to substrate junction, causing it to emit electrons. This condition starts the parasitic BJT's 140 a , 140 b , 140 c , 140 d conducting.
  • the substrate bulk resistances, 145 a , 145 b , 145 c , 145 d , and 150 a , 150 b , 150 c , 150 d are configured such that the base current of parasitic BJT's 140 a and 140 b are much larger than the base current of BJT's 140 c and 140 d .
  • the currents of the parasitic BJT's 140 a and 140 b are much greater than the collector currents of the parasitic 140 c and 140 d .
  • This differential of the collector currents commonly called current crowding can cause BJT's 140 a and 140 b to fail due to excessive current.
  • FIGS. 1 b and 1 c illustrate the top surface and cross-section of the NMOS FET 100 of FIG. 11 a .
  • a P-type material is implanted to a low concentration into the surface of the semiconductor substrate 200 to form the P-well 205 .
  • the P-well 205 forms an expitaxial area that is connected to the substrate biasing voltage source Vss.
  • An N-type material is implanted to a high concentration to form the drain regions 210 a , 210 b , 210 c , 210 d of the NMOS FET 100 .
  • the N-type material is simultaneously implanted to a high concentration to form the source regions 215 a , 215 b , 215 c of the NMOS FET 100 .
  • the N-type material is further implanted to a very high concentration within the drain regions 210 a , 210 b , 210 c , 210 d and the source regions 215 a , 215 b , 215 c , to form respectively low resistivity drain contact points 220 a , 220 b , 220 c , 220 d and low resistivity source contact points 225 a , 225 b , 225 c.
  • An insulating material is deposited on the surface of the semiconductor substrate 200 in the channel regions 260 a , 260 b , 260 c , 260 d , 260 e , 260 f to form a gate oxide 265 a , 265 b , 265 c , 265 d , 265 e , 265 f .
  • a conductive material such as highly doped polycrystalline silicon is deposited to form the gates 230 a , 230 b , 230 c , 230 d , 230 e , 230 f of the NMOS FET 100 .
  • a second conductive material such as a aluminum is then deposited on the surface of the semiconductor substrate 200 to form the connecting lands 240 that connect the drain regions 210 a , 210 b , 210 c , 210 d to the input/output pad and the internal circuits through the low resistivity drain contacts 220 a , 220 b , 220 c , 220 d .
  • the second conductive material is also deposited on the surface of the semiconductor substrate 200 to form the connecting lands 245 from the source regions 215 a , 215 b , 215 c to the substrate biasing source Vss through the low resistivity source contacts 225 a , 225 b , 225 c.
  • the first conductive material is further deposited to form the connecting land 250 that connects the gates 230 a , 230 b , 230 c , 230 d , 230 e , 230 f to the substrate biasing voltage source Vss.
  • U.S. Pat. No. 5,237,395 describes an electrostatic discharge (ESD) protection circuit for protecting internal devices of an integrated circuit.
  • the ESD protection circuit of Lee is coupled between the power rails of the integrated circuits.
  • First and second current shunt paths between the power rails are maintained nonconductive during normal circuit operation.
  • the ESD protection circuit of Lee causes the first and second current shunt paths to be triggered to a conductive mode in response to an ESD event on the power rails.
  • a triggering circuit to trigger the first and second shunt paths employs a logic gate such as an inverter.
  • the input of the inverter is coupled to the positive power rails and will maintain a low level output during normal operation.
  • the inverter provides a high output in response to an ESD event on the power rail to trigger the first and second shunt paths.
  • U.S. Pat. No. 5,532,178 (Liaw et al.) teaches an improved process and integrated circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate with an NMOS electrostatic discharge circuit.
  • the NMOS ESD circuit is formed in a P well on the substrate.
  • the improvement includes an ESD NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes.
  • the undoped polysilicon gate electrode of the electrostatic discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.
  • U.S. Pat. No. 5,689,133 (Li et al.) describes an ESD protection circuit combines a split bipolar transistor with a transistor layout, which exhibits very high tolerance to ESD events.
  • the split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure.
  • Several splitting structures are disclosed.
  • the split bipolar transistor structures each combine a resistor in series with each segment to distribute current evenly.
  • the transistor takes advantage of the snapback effect to increase current carrying capacity.
  • Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current.
  • Another object of this invention is to provide an ESD protection device that has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits.
  • an ESD protection device is formed on a semiconductor substrate.
  • the ESD protection device connected between the junction of an input/output pad and internal circuitry with a reference voltage source.
  • the ESD protection device prevents damage to the internal circuitry during application of an ESD voltage source to the input/output pad by conducting an ESD current uniformly from the ESD voltage source to the reference voltage source.
  • the ESD protection device has at least one source region of a material of a first conductivity type implanted into the surface of the semiconductor substrate at a first distance and connected to the reference voltage source and at least one drain region of the material of the first conductivity type implanted into the surface the semiconductor substrate at a second distance from each other and between the plurality of source region, at a third distance from the source regions and connected to the junction of the input/output pad and the internal circuitry.
  • the ESD protection device further has at least one gate electrode formed by the deposition of a conductive material such as highly doped polycrystalline silicon upon an insulating material formed at the surface of the semiconductor substrate above a channel region.
  • the channel region is the region is between each of the source regions and the drain regions.
  • the gate electrodes are connected to the reference voltage source.
  • Each gate electrode has a gradually variable length and thus the channel region has a gradually variable length.
  • the ESD protection device has at least one parasitic bipolar transistor.
  • Each parasitic bipolar transistor having a collector that is a portion of one of the drain regions, an emitter that is a portion of one of the source regions adjacent to the one drain region, and a base that is a portion of the channel region between the one drain region and the one source region.
  • the ESD current is distributed uniformly over the channel region.
  • the ESD protection device also has at least one parasitic resistor formed of a bulk resistance of the semiconductor substrate and connected from the bases of the parasitic transistors connected to the reference voltage source.
  • the ESD protection device further optionally has a well of a material of the second conductivity type implanted into the surface of the semiconductor substrate and into which the plurality of source regions and the plurality drain regions are implanted.
  • the semiconductor substrate is of the material of the second conductivity type, and the ESD protection device is formed in the surface of the semiconductor substrate.
  • variable length of the gate electrodes varies from a minimum that is approximately a minimum feature size able to be formed on the semiconductor substrate to a maximum that is from approximately two times to approximately three times the minimum feature size.
  • FIG. 1 a is a schematic drawing of a model of an application of an ESD protection device of the prior art.
  • FIG. 1 b is a diagram of a top surface of a NMOS FET ESD protection device of the prior art.
  • FIG. 1 c is a diagram of a cross-section of the NMOS FET ESD protection device of the prior art.
  • FIG. 2 a is a diagram of the top surface of a NMOS FET ESD protection device of this invention.
  • FIG. 2 b is a diagram of the cross-section of the NMOS FET ESD protection device of this invention at a minimum gate length.
  • FIG. 2 c is a diagram of the cross-section of the NMOS FET ESD protection device of this invention at a maximum gate length.
  • FIG. 3 is a schematic diagram of a model representing the parasitic transistor structure of the NMOS FET ESD protection device of this invention during application of an ESD voltage source to an input/output pad.
  • FIG. 4 is a plot of ESD current versus distance from the point of application of the ESD voltage source of the prior art and of this invention.
  • the NMOS FET 1000 of this invention as shown in FIGS. 2 a , 2 b , and 2 c functionally replaces the NMOS FET 100 of the prior art in FIG. 1 a .
  • a P-well 305 is formed in the n-type substrate 300 by implanting a p-type material to a low concentration into the surface of the semiconductor substrate 300 .
  • An N-type material is then implanted to a high concentration into the surface of the semiconductor substrate to form the drain regions 310 a , 310 b , 310 c , 310 d.
  • the drain regions are placed at an equal distance from each other sufficient to allow the simultaneous implantation of the N-type material to a high concentration to form the source regions 315 a , 315 b , 315 c .
  • the source regions 315 a , 315 b , 315 c are equally spaced from the drain regions 310 a , 310 b , 310 c , 310 d to form separate fingers of rows of the drain regions 310 a , 310 b , 310 c , 310 d and the source regions 315 a , 315 b , 315 c .
  • the space within the semiconductor substrate 300 between each of the drain regions 310 a , 310 b , 310 c , 310 d and the source regions is one channel region of the group of channel regions 360 a , 360 b , 360 c , 360 d , 360 e , 360 f.
  • an insulating material such as silicon dioxide is formed to create the gate oxides 365 a , 365 b , 365 c , 365 d , 365 e , 365 f .
  • a conductive material such as highly doped polycrystalline silicon is deposited on the gate oxides 365 a , 365 b , 365 c , 365 d , 365 e , 365 f to form the gate electrode 330 a , 330 b , 330 c , 330 d , 330 e , 330 f.
  • the N-type material is implanted to a very high concentration to form respectively the drain contacts 320 a , 320 b , 320 c , 320 d and the source contacts 325 a , 325 b , 325 c within the drains 310 a , 310 b , 310 c , 310 d and the sources 315 a , 315 b , 315 c .
  • a second conductive material such as aluminum is deposited on the drain contacts 320 a , 320 b , 320 c to form the connective lands 340 that connect the drain regions 310 a , 310 b , 310 c , 310 d to the input/output pad and the internal circuitry.
  • the second conductive material is deposited on the source contacts 325 a , 325 b , 325 c to form the connective lands 345 that connect the source regions 315 a , 315 b , 315 c to the substrate biasing voltage source Vss.
  • the first conductive material is formed on the surface of the semiconductor substrate to form the connection 350 to the gates 330 a , 330 b , 330 c , 330 d , 330 e , 330 f together and to the substrate biasing voltage source Vss.
  • FIG. 2 b shows the cross-section of the NMOS FET ESD protection device where the gates 330 a , 330 b , 330 c , 330 d , 330 e , 330 f have a first length equal to L 1 .
  • FIG. 2 c shows the cross-section of the NMOS FET ESD protection device where the gates 330 a , 330 b , 330 c , 330 d , 330 e , 330 f have a second length equal to L 2 . As is shown in FIG.
  • the distance from where the gates 330 a , 330 b , 330 c , 330 d , 330 e , 330 f are at the first length L 1 and the second length L 2 is such that the gate length varies uniformly from the first length L 1 and the second length L 2 so as to avoid an abrupt change in gate length. Since the gate length L 1 and L 2 is uniformly variable, the length of the channel regions 360 a , 360 b , 360 c , 360 d , 360 e , 360 f is also varied in a nearly uniform manner from the minimum length L 1 to the maximum length L 2 .
  • the minimum length L 1 will approach the minimum feature size capable of the semiconductor processing. In the present technology, that is from approximately 0.25 ⁇ m to approximately 0.35 ⁇ m.
  • the maximum length L 2 is from approximately two to approximately three times the minimum feature size or from approximately 0.50 ⁇ m to approximately 1.05 ⁇ m.
  • the parasitic BJT's 140 a , 140 b , 140 c , 140 d , as described in FIG. 1 are formed similarly.
  • the drain regions 310 a , 310 b , 310 c , 310 d , 310 e , 310 f are the collectors of the parasitic transistors.
  • the source regions 315 a , 315 b , 315 c form the emitters of the parasitic transistors.
  • the channel regions 360 a , 360 b , 360 c , 360 d , 360 e , 360 f are the bases of the parasitic transistors.
  • the parasitic transistors 145 a , 145 b , 145 c , 145 d of FIG. 1 a represent the parasitic transistors formed between each of the drain regions 310 a , 310 b , 310 c , 310 d and each adjacent source region 315 a , 315 b , 315 c .
  • each parasitic transistor such as 145 a , 145 b , 145 c , 145 d of FIG.
  • the parasitic BJT's 440 a , 440 b , 440 c , 440 d 440 e have a base length that is equivalent to the channel length and varies in a uniform fashion from the maximum L 2 to the minimum L 1 as shown in FIGS. 2 a and 2 b.
  • X B 2 is the length of the base.
  • D B is the diffusion constant of the material of the base (channel region).
  • each of the parasitic BJT's 440 a , 440 b , 440 c , 440 d , 440 e will turn on at a different time.
  • the ESD current will arrive at the collectors of the parasitic BJT's 440 a , 440 b , 440 c , 440 d at various times.
  • the first parasitic BJT 440 a , 440 b to receive the ESD current will be those closest to the connecting lands 340 directly connected to the input/output pad.
  • the parasitic BJT's 440 a , 440 b will turn on slower than the parasitic BJT's 440 d , 440 e with a shorter channel length L 1 .
  • the parasitic BJT's 440 d , 440 e having the shortest base length are placed farthest from the ESD voltage source.
  • the mechanism for turning on the parasitic BJT's 440 a , 440 b , 440 c , 440 d , 440 e is as described above for FIG. 1 a .
  • the junction between the drain regions 310 a , 310 b , 310 c , 310 d and the substrate 300 begin avalanche breakdown generating an electron-hole current in the substrate 300 . This is represented by the current sources Jgen 442 a , 442 b , 442 c , 442 d , 442 e .
  • the current Jgen is divided to become the base current Jb for the parasitic transistors 440 a , 440 b , 440 c , 440 d , 440 e and the components Jsub and Jx of the substrate current Isub.
  • the voltage developed at the base of each of the parasitic transistors 440 a , 440 b , 440 c , 440 d , 440 e directly effects the magnitude of the collector current Jc.
  • the collector currents Jc of the remaining parasitic BJT's 440 c , 440 d , 440 e have a magnitude matching the collector currents Jc of the parasitic BJT's 440 a and 440 b . This avoids the above described current crowding and provides uniform current through out the NMOS FET ESD protection device.
  • FIG. 4 shows the distribution of collector current Jc of the parasitic BJT's versus their distance X from the input/output pad and the ESD voltage source.
  • the plot 500 of the current through the NMOS FET ESD protection device of the prior art has an excessively high current near the input/output pad and the ESD voltage source. This current then trails off to a marginal current 510 for those parasitic transistors farthest from the input/output pad.
  • the plot 550 shows that the current is relatively uniform across all of the parasitic BJT's.
  • the multiple parasitic BJT's 140 of FIG. 1 a having the NMOS FET 1000 of FIG. 2 a , have large base widths near the channel edges as shown in FIG. 2 a .
  • those parasitic BJT's with narrower base width turn-on faster than those with a wider base width near the channel edge.
  • the delay in turn-on of those parasitic BJT's near the channel edge causes the relatively uniform current distribution across all the parasitic bipolar transistors. The more uniform the current results in a sufficiently large ESD current to rapidly discharge the ESD voltage source having larger voltage levels than the prior art. This will prevent damage to internal circuits of an integrated circuit that is exposed to the larger voltage present on the ESD voltage source.
  • the semiconductor substrate 300 can be implanted with the p-type material to have an epitaxial area covering the entire semiconductor substrate 300 and the p-well 305 can be eliminated. Further, it will be apparent to those skilled in the art that the species of the implant materials can be reversed to crate a P-channel MOS FET. The P-channel MOS FET is then substituted for the PMOS FET 105 of FIG. 1 a.

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

An ESD protection structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, will protect internal circuits formed on the semiconductor substrate from over stress due to excessively high voltages of an ESD voltage source. The ESD protection structure has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits. The ESD protection device has at least one source region that is the emitters of parasitic transistors connected to the reference voltage source and at least one drain region that is the collectors of the parasitic transistors connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source. Each gate electrode has a variable length and thus the channel region has a variable length. The channel region is the base of the parasitic transistors formed by the ESD protection structure. The variable length of the channel region and thus the base of the parasitic transistors create an ESD current that is distributed uniformly over said ESD protection structure.

Description

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is related to the protection of integrated circuits on a semiconductor substrate from voltage overstress due to pulses resulting from electrostatic discharge (ESD). More particularly, this invention is related to semiconductor devices and structures for improved protection of the integrated circuits.
2. Description of the Related Art
In FIG. 1a the N-channel metal oxide semiconductor (NMOS) field effect transistor (FET) 100 of the prior art is shown in an application, wherein it is configured as an ESD protection circuit. The drain of the NMOS FET 100 is connected to the input pad 115, the drain of the P-channel Metal Oxide Semiconductor (PMOS) FET 200, and to the internal circuits 110. The source and the gate of the PMOS FET 200 are connected to the voltage supply VDD. The source and gate of the NMOS FET 100 are connected to the substrate biasing voltage source Vss. The collectors of the parasitic bipolar junction transistors (BJT's) 140 a, 140 b, 140 c, 140 d are structurally the drain of the NMOS FET 100. The emitters of the parasitic BJT's 140 a, 140 b, 140 c, 140 d are structurally the source of the NMOS FET 100 which is connected to the substrate biasing voltage source Vss. The bases of the parasitic BJT's 140 a, 140 b, 140 c, 140 d are structurally the channel region of the NMOS FET 100 are connected to the parasitic resistors 145 a, 145 b, 145 c, 145 d that is formed by the bulk resistance of the semiconductor substrate. The parasitic resistors 145 a, 145 b, 145 c, 145 d, and 150 a, 150 b, 150 c, 150 d form a resistive network connected to the ground reference.
A positive ESD source 120 such as the human body or electrostatically charged machinery is momentarily coupled to the input/output pad 115. The magnitude of a voltage pulse of the ESD source 120 is on the order of 1,000 volts or larger. As the voltage of the ESD source 120 is transferred through the metal connections to the drain of the NMOS FET 100, the gate to drain voltage of the NMOS FET 100 is exceeds the breakdown voltage. The drain to the substrate junction starts to enter the avalanche breakdown condition and then starts to generate large amounts of electron - hole pairs. The holes pass through the substrate bulk resistances 145 a, 145 b, 145 c, 145 d, and 150 a, 150 b, 150 c, 150 d. The voltage drop across the substrate bulk resistances 145 a, 145 b, 145 c, 145 d, and 150 a, 150 b, 150 c, 150 d forward bias the source to substrate junction, causing it to emit electrons. This condition starts the parasitic BJT's 140 a, 140 b, 140 c, 140 d conducting. The substrate bulk resistances, 145 a, 145 b, 145 c, 145 d, and 150 a, 150 b, 150 c, 150 d are configured such that the base current of parasitic BJT's 140 a and 140 b are much larger than the base current of BJT's 140 c and 140 d. Since the base currents are directly related to the collector currents until the parasitic BJT's reach saturation, the currents of the parasitic BJT's 140 a and 140 b are much greater than the collector currents of the parasitic 140 c and 140 d. This differential of the collector currents commonly called current crowding can cause BJT's 140 a and 140 b to fail due to excessive current.
FIGS. 1b and 1 c illustrate the top surface and cross-section of the NMOS FET 100 of FIG. 11a. A P-type material is implanted to a low concentration into the surface of the semiconductor substrate 200 to form the P-well 205. The P-well 205 forms an expitaxial area that is connected to the substrate biasing voltage source Vss. An N-type material is implanted to a high concentration to form the drain regions 210 a, 210 b, 210 c, 210 d of the NMOS FET 100. The N-type material is simultaneously implanted to a high concentration to form the source regions 215 a, 215 b, 215 c of the NMOS FET 100.
The N-type material is further implanted to a very high concentration within the drain regions 210 a, 210 b, 210 c, 210 d and the source regions 215 a, 215 b, 215 c, to form respectively low resistivity drain contact points 220 a, 220 b, 220 c, 220 d and low resistivity source contact points 225 a, 225 b, 225 c.
An insulating material is deposited on the surface of the semiconductor substrate 200 in the channel regions 260 a, 260 b, 260 c, 260 d, 260 e, 260 f to form a gate oxide 265 a, 265 b, 265 c, 265 d, 265 e, 265 f. Above the gate oxide 265 a, 265 b, 265 c, 265 d, 265 e, 265 f a conductive material such as highly doped polycrystalline silicon is deposited to form the gates 230 a, 230 b, 230 c, 230 d, 230 e, 230 f of the NMOS FET 100.
A second conductive material such as a aluminum is then deposited on the surface of the semiconductor substrate 200 to form the connecting lands 240 that connect the drain regions 210 a, 210 b, 210 c, 210 d to the input/output pad and the internal circuits through the low resistivity drain contacts 220 a, 220 b, 220 c, 220 d. Simultaneously, the second conductive material is also deposited on the surface of the semiconductor substrate 200 to form the connecting lands 245 from the source regions 215 a, 215 b, 215 c to the substrate biasing source Vss through the low resistivity source contacts 225 a, 225 b, 225 c.
The first conductive material is further deposited to form the connecting land 250 that connects the gates 230 a, 230 b, 230 c, 230 d, 230 e, 230 f to the substrate biasing voltage source Vss.
As above described, when an ESD voltage source 120 of FIG. 1a is coupled to the input/output pad 115, the current crowding that results from nonuniform currents can cause the damage 270 shown.
U.S. Pat. No. 5,237,395 (Lee) describes an electrostatic discharge (ESD) protection circuit for protecting internal devices of an integrated circuit. The ESD protection circuit of Lee is coupled between the power rails of the integrated circuits. First and second current shunt paths between the power rails are maintained nonconductive during normal circuit operation. The ESD protection circuit of Lee causes the first and second current shunt paths to be triggered to a conductive mode in response to an ESD event on the power rails. A triggering circuit to trigger the first and second shunt paths employs a logic gate such as an inverter. The input of the inverter is coupled to the positive power rails and will maintain a low level output during normal operation. The inverter provides a high output in response to an ESD event on the power rail to trigger the first and second shunt paths.
U.S. Pat. No. 5,532,178 (Liaw et al.) teaches an improved process and integrated circuit having CMOS (NMOS and/or PMOS) devices formed on a substrate with an NMOS electrostatic discharge circuit. The NMOS ESD circuit is formed in a P well on the substrate. The improvement includes an ESD NMOS circuit having an undoped polysilicon gate electrode, and the NMOS FET devices having n-type doped gate electrodes. The undoped polysilicon gate electrode of the electrostatic discharge transistor increases the gate oxide breakdown voltage thus making the ESD transistor able to withstand a greater voltage discharge and therefore providing better protection to the product devices.
U.S. Pat. No. 5,689,133 (Li et al.) describes an ESD protection circuit combines a split bipolar transistor with a transistor layout, which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed. The split bipolar transistor structures each combine a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snapback effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical comers are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.
SUMMARY OF THE INVENTION
It is an object of this invention to provide a NMOS FET device structure that when connected between an input/output pad on a semiconductor substrate and a reference voltage source, it will protect internal circuits formed on the semiconductor substrate from overstress due to excessively high voltages from an ESD voltage source.
Another object of this invention is to provide an ESD protection device that has a uniform discharge current to prevent damage to the ESD protection device thus allowing increased protection to the internal circuits.
To accomplish these and other objects an ESD protection device is formed on a semiconductor substrate. The ESD protection device connected between the junction of an input/output pad and internal circuitry with a reference voltage source. The ESD protection device prevents damage to the internal circuitry during application of an ESD voltage source to the input/output pad by conducting an ESD current uniformly from the ESD voltage source to the reference voltage source. The ESD protection device has at least one source region of a material of a first conductivity type implanted into the surface of the semiconductor substrate at a first distance and connected to the reference voltage source and at least one drain region of the material of the first conductivity type implanted into the surface the semiconductor substrate at a second distance from each other and between the plurality of source region, at a third distance from the source regions and connected to the junction of the input/output pad and the internal circuitry. The ESD protection device further has at least one gate electrode formed by the deposition of a conductive material such as highly doped polycrystalline silicon upon an insulating material formed at the surface of the semiconductor substrate above a channel region. The channel region is the region is between each of the source regions and the drain regions. The gate electrodes are connected to the reference voltage source. Each gate electrode has a gradually variable length and thus the channel region has a gradually variable length.
The ESD protection device has at least one parasitic bipolar transistor. Each parasitic bipolar transistor having a collector that is a portion of one of the drain regions, an emitter that is a portion of one of the source regions adjacent to the one drain region, and a base that is a portion of the channel region between the one drain region and the one source region. The ESD current is distributed uniformly over the channel region.
The ESD protection device also has at least one parasitic resistor formed of a bulk resistance of the semiconductor substrate and connected from the bases of the parasitic transistors connected to the reference voltage source.
The ESD protection device further optionally has a well of a material of the second conductivity type implanted into the surface of the semiconductor substrate and into which the plurality of source regions and the plurality drain regions are implanted. Or optionally, the semiconductor substrate is of the material of the second conductivity type, and the ESD protection device is formed in the surface of the semiconductor substrate.
The variable length of the gate electrodes varies from a minimum that is approximately a minimum feature size able to be formed on the semiconductor substrate to a maximum that is from approximately two times to approximately three times the minimum feature size.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1a is a schematic drawing of a model of an application of an ESD protection device of the prior art.
FIG. 1b is a diagram of a top surface of a NMOS FET ESD protection device of the prior art.
FIG. 1c is a diagram of a cross-section of the NMOS FET ESD protection device of the prior art.
FIG. 2a is a diagram of the top surface of a NMOS FET ESD protection device of this invention.
FIG. 2b is a diagram of the cross-section of the NMOS FET ESD protection device of this invention at a minimum gate length.
FIG. 2c is a diagram of the cross-section of the NMOS FET ESD protection device of this invention at a maximum gate length.
FIG. 3 is a schematic diagram of a model representing the parasitic transistor structure of the NMOS FET ESD protection device of this invention during application of an ESD voltage source to an input/output pad.
FIG. 4 is a plot of ESD current versus distance from the point of application of the ESD voltage source of the prior art and of this invention.
DETAILED DESCRIPTION OF THE INVENTION
The NMOS FET 1000 of this invention as shown in FIGS. 2a, 2 b, and 2 c functionally replaces the NMOS FET 100 of the prior art in FIG. 1a. A P-well 305 is formed in the n-type substrate 300 by implanting a p-type material to a low concentration into the surface of the semiconductor substrate 300. An N-type material is then implanted to a high concentration into the surface of the semiconductor substrate to form the drain regions 310 a, 310 b, 310 c, 310 d.
The drain regions are placed at an equal distance from each other sufficient to allow the simultaneous implantation of the N-type material to a high concentration to form the source regions 315 a, 315 b, 315 c. The source regions 315 a, 315 b, 315 c are equally spaced from the drain regions 310 a, 310 b, 310 c, 310 d to form separate fingers of rows of the drain regions 310 a, 310 b, 310 c, 310 d and the source regions 315 a, 315 b, 315 c. The space within the semiconductor substrate 300 between each of the drain regions 310 a, 310 b, 310 c, 310 d and the source regions is one channel region of the group of channel regions 360 a, 360 b, 360 c, 360 d, 360 e, 360 f.
Above each of the channel regions 360 a, an insulating material such as silicon dioxide is formed to create the gate oxides 365 a, 365 b, 365 c, 365 d, 365 e, 365 f. A conductive material such as highly doped polycrystalline silicon is deposited on the gate oxides 365 a, 365 b, 365 c, 365 d, 365 e, 365 f to form the gate electrode 330 a, 330 b, 330 c, 330 d, 330 e, 330 f.
The N-type material is implanted to a very high concentration to form respectively the drain contacts 320 a, 320 b, 320 c, 320 d and the source contacts 325 a, 325 b, 325 c within the drains 310 a, 310 b, 310 c, 310 d and the sources 315 a, 315 b, 315 c. A second conductive material such as aluminum is deposited on the drain contacts 320 a, 320 b, 320 c to form the connective lands 340 that connect the drain regions 310 a, 310 b, 310 c, 310 d to the input/output pad and the internal circuitry. Simultaneously, the second conductive material is deposited on the source contacts 325 a, 325 b, 325 c to form the connective lands 345 that connect the source regions 315 a, 315 b, 315 c to the substrate biasing voltage source Vss.
The first conductive material is formed on the surface of the semiconductor substrate to form the connection 350 to the gates 330 a, 330 b, 330 c, 330 d, 330 e, 330 f together and to the substrate biasing voltage source Vss.
The gates 330 a, 330 b, 330 c, 330 d, 330 e, 330 f each have a uniformly variable gate length. FIG. 2b shows the cross-section of the NMOS FET ESD protection device where the gates 330 a, 330 b, 330 c, 330 d, 330 e, 330 f have a first length equal to L1. FIG. 2c shows the cross-section of the NMOS FET ESD protection device where the gates 330 a, 330 b, 330 c, 330 d, 330 e, 330 f have a second length equal to L2. As is shown in FIG. 2a, the distance from where the gates 330 a, 330 b, 330 c, 330 d, 330 e, 330 f are at the first length L1 and the second length L2 is such that the gate length varies uniformly from the first length L1 and the second length L2 so as to avoid an abrupt change in gate length. Since the gate length L1 and L2 is uniformly variable, the length of the channel regions 360 a, 360 b, 360 c, 360 d, 360 e, 360 f is also varied in a nearly uniform manner from the minimum length L1 to the maximum length L2. The minimum length L1 will approach the minimum feature size capable of the semiconductor processing. In the present technology, that is from approximately 0.25 μm to approximately 0.35 μm. The maximum length L2 is from approximately two to approximately three times the minimum feature size or from approximately 0.50 μm to approximately 1.05 μm.
The parasitic BJT's 140 a, 140 b, 140 c, 140 d, as described in FIG. 1 are formed similarly. The drain regions 310 a, 310 b, 310 c, 310 d, 310 e, 310 f are the collectors of the parasitic transistors. The source regions 315 a, 315 b, 315 c form the emitters of the parasitic transistors. And the channel regions 360 a, 360 b, 360 c, 360 d, 360 e, 360 f are the bases of the parasitic transistors.
The parasitic transistors 145 a, 145 b, 145 c, 145 d of FIG. 1a represent the parasitic transistors formed between each of the drain regions 310 a, 310 b, 310 c, 310 d and each adjacent source region 315 a, 315 b, 315 c. However, due to the variability of the length of the channel regions 360 a, 360 b, 360 c, 360 d, 360 e, 360 f, each parasitic transistor such as 145 a, 145 b, 145 c, 145 d of FIG. 1a can be considered multiple parasitic transistors connected in parallel and having a uniformly variable base length as shown in FIG. 3. The parasitic BJT's 440 a, 440 b, 440 c, 440 d 440 e have a base length that is equivalent to the channel length and varies in a uniform fashion from the maximum L2 to the minimum L1 as shown in FIGS. 2a and 2 b.
It is well known in the art that the turn-on time τBF for a transistor is: τ BF = X B 2 2 D B Eq .   1
Figure US06258672-20010710-M00001
Where:
XB 2 is the length of the base.
DB is the diffusion constant of the material of the base (channel region).
Having a uniformly variable base length, each of the parasitic BJT's 440 a, 440 b, 440 c, 440 d, 440 e will turn on at a different time.
However, as the ESD current flows into the drain regions 310 a, 310 b, 310 c, 310 d, the ESD current will arrive at the collectors of the parasitic BJT's 440 a, 440 b, 440 c, 440 d at various times. The first parasitic BJT 440 a, 440 b to receive the ESD current will be those closest to the connecting lands 340 directly connected to the input/output pad. Therefore, if the channel length is longest L2 for the parasitic BJT's 440 a, 440 b nearest the input/output pad, the parasitic BJT's 440 a, 440 b, will turn on slower than the parasitic BJT's 440 d, 440 e with a shorter channel length L1. Thus the parasitic BJT's 440 d, 440 e having the shortest base length are placed farthest from the ESD voltage source. This arrangement of the parasitic BJT's 440 d, 440 e with shortest base length being farthest from the ESD voltage source, and the parasitic BJT 440 a, 440 b that have the longest base length being closest to the ESD voltage source, causes the parasitic BJT's 440 a, 440 b, 440 c, 440 d to turn on nearly simultaneously causing a uniform current through the NMOS FET ESD protection device.
The mechanism for turning on the parasitic BJT's 440 a, 440 b, 440 c, 440 d, 440 e is as described above for FIG. 1a. The junction between the drain regions 310 a, 310 b, 310 c, 310 d and the substrate 300 begin avalanche breakdown generating an electron-hole current in the substrate 300. This is represented by the current sources Jgen 442 a, 442 b, 442 c, 442 d, 442 e. The current Jgen is divided to become the base current Jb for the parasitic transistors 440 a, 440 b, 440 c, 440 d, 440 e and the components Jsub and Jx of the substrate current Isub. As described above, the voltage developed at the base of each of the parasitic transistors 440 a, 440 b, 440 c, 440 d, 440 e directly effects the magnitude of the collector current Jc. By delaying the turn on of the parasitic transistors 440 a, 440 b, the collector currents Jc of the remaining parasitic BJT's 440 c, 440 d, 440 e have a magnitude matching the collector currents Jc of the parasitic BJT's 440 a and 440 b. This avoids the above described current crowding and provides uniform current through out the NMOS FET ESD protection device.
FIG. 4 shows the distribution of collector current Jc of the parasitic BJT's versus their distance X from the input/output pad and the ESD voltage source. The plot 500 of the current through the NMOS FET ESD protection device of the prior art has an excessively high current near the input/output pad and the ESD voltage source. This current then trails off to a marginal current 510 for those parasitic transistors farthest from the input/output pad. The plot 550 shows that the current is relatively uniform across all of the parasitic BJT's.
The multiple parasitic BJT's 140 of FIG. 1a, having the NMOS FET 1000 of FIG. 2a, have large base widths near the channel edges as shown in FIG. 2a. According to Eq. 1, those parasitic BJT's with narrower base width turn-on faster than those with a wider base width near the channel edge. The delay in turn-on of those parasitic BJT's near the channel edge causes the relatively uniform current distribution across all the parasitic bipolar transistors. The more uniform the current results in a sufficiently large ESD current to rapidly discharge the ESD voltage source having larger voltage levels than the prior art. This will prevent damage to internal circuits of an integrated circuit that is exposed to the larger voltage present on the ESD voltage source.
Returning to FIGS. 2a and 2 b, it will be apparent to those skilled in the art that the semiconductor substrate 300 can be implanted with the p-type material to have an epitaxial area covering the entire semiconductor substrate 300 and the p-well 305 can be eliminated. Further, it will be apparent to those skilled in the art that the species of the implant materials can be reversed to crate a P-channel MOS FET. The P-channel MOS FET is then substituted for the PMOS FET 105 of FIG. 1a.
While this invention has been particularly shown and described with reference to the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of the invention.

Claims (4)

The Invention claimed is:
1. A method to fabricate an ESD protection device that prevents damage to internal circuitry formed on a semiconductor substrate during application of an ESD voltage source to said internal circuitry through an input/output pad connected the internal circuitry by conducting an ESD current uniformly through said ESD protection device to a reference voltage source, whereby said method to fabricate comprises the steps of:
providing said semiconductor substrate;
implanting a material of a first conductivity type to a low concentration into a surface of the semiconductor substrate to form an epitaxial area, whereby said epitaxial area has a bulk resistance that forms at least one parasitic resistor;
implanting a material of a second conductivity type to a high concentration into the surface of the semiconductor substrate within the epitaxial area to form at least one source region placed at a first distance from each other source region, whereby a portion of each source region forms an emitter of a parasitic transistor of at least one parasitic transistors;
implanting the material of the second conductivity type to a high concentration into the surface of the semiconductor substrate within the epitaxial area and between the plurality of source regions such that each drain region is a second distance from each source region, whereby a portion of each drain region forms a collector of the parasitic transistor of the plurality of parasitic transistors;
forming an insulating layer on the surface of said semiconductor substrate above a channel region that is between each of the source regions and the drain regions to form a gate oxide, whereby a portion of the channel region forms a base of the parasitic transistor of the plurality of parasitic transistors;
depositing a conductive material on the gate oxide to form a gate electrode, whereby each gate electrode and thus each channel region channel length varies gradually and not abruptly from a first length to a second length;
connecting each of the source regions to the reference voltage source;
connecting each of the drain regions to a junction of the input/output pad and the internal circuitry; and
connecting each of the gate electrodes to said reference voltage source.
2. The method of claim 1 whereby the epitaxial area is over the surface of the entire semiconductor substrate.
3. The method of claim 1 wherein the epitaxial area is a well within the surface of the semiconductor substrate, whereby the semiconductor substrate is implanted with the material of the second conductivity type to a low concentration.
4. The method of claim 1 wherein the first length is approximately a minimum feature size able to be formed on said semiconductor substrate and the second length is from approximately two times to approximately three times said minimum feature size.
US09/252,630 1999-02-18 1999-02-18 Method of fabricating an ESD protection device Expired - Lifetime US6258672B1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US09/252,630 US6258672B1 (en) 1999-02-18 1999-02-18 Method of fabricating an ESD protection device
US09/709,597 US6441438B1 (en) 1999-02-18 2000-11-13 ESD protect device structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/252,630 US6258672B1 (en) 1999-02-18 1999-02-18 Method of fabricating an ESD protection device

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US09/709,597 Division US6441438B1 (en) 1999-02-18 2000-11-13 ESD protect device structure

Publications (1)

Publication Number Publication Date
US6258672B1 true US6258672B1 (en) 2001-07-10

Family

ID=22956855

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/252,630 Expired - Lifetime US6258672B1 (en) 1999-02-18 1999-02-18 Method of fabricating an ESD protection device
US09/709,597 Expired - Lifetime US6441438B1 (en) 1999-02-18 2000-11-13 ESD protect device structure

Family Applications After (1)

Application Number Title Priority Date Filing Date
US09/709,597 Expired - Lifetime US6441438B1 (en) 1999-02-18 2000-11-13 ESD protect device structure

Country Status (1)

Country Link
US (2) US6258672B1 (en)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462389B2 (en) * 2000-01-27 2002-10-08 Hyundai Electronics Industries Co., Ltd. Semiconductor device
US6545322B2 (en) * 2000-11-01 2003-04-08 Seiko Instruments Inc. Semiconductor protection device
FR2831328A1 (en) * 2001-10-23 2003-04-25 St Microelectronics Sa Integrated circuit has metal oxide semiconductor transistors which are integrated in supply rail and below supply conductors, to short-circuit conductors for protection against electrostatic discharge and overvoltage
US6563175B2 (en) * 2001-09-24 2003-05-13 Texas Instruments Incorporated NMOS ESD protection device with thin silicide and methods for making same
US20040120085A1 (en) * 2002-12-19 2004-06-24 Renesas Technology Corp. Semiconductor device with surge protection circuit
US20050133871A1 (en) * 2003-12-22 2005-06-23 Vanguard International Semiconductor Corporation Electrostatic discharge protection device
US7078283B1 (en) 2002-08-07 2006-07-18 Taiwan Semiconductor Manufacturing Company Process for providing ESD protection by using contact etch module
US20090283832A1 (en) * 2008-05-16 2009-11-19 Kabushiki Kaisha Toshiba Semiconductor device
US7718480B1 (en) * 2005-05-26 2010-05-18 National Semiconductor Corporation ESD clamps and NMOS arrays with increased electrical overstress robustness
US9343457B2 (en) * 2013-03-06 2016-05-17 STI Semiconductor Corporation Semiconductor device
US9640527B2 (en) * 2015-06-02 2017-05-02 United Microelectronics Corp. Electrostatic discharge protection device with parasitic bipolar junction transistors
US10763205B2 (en) 2017-07-13 2020-09-01 Seagate Technology Llc Input/output cell wire connector
CN112987358A (en) * 2021-02-20 2021-06-18 Tcl华星光电技术有限公司 Driving chip and display device having the same

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7005708B2 (en) * 2001-06-14 2006-02-28 Sarnoff Corporation Minimum-dimension, fully-silicided MOS driver and ESD protection design for optimized inter-finger coupling
US6818955B1 (en) 2003-04-09 2004-11-16 Marvell International Ltd. Electrostatic discharge protection
US6987301B1 (en) 2003-04-09 2006-01-17 Marvell International Ltd. Electrostatic discharge protection
US6912150B2 (en) * 2003-05-13 2005-06-28 Lionel Portman Reference current generator, and method of programming, adjusting and/or operating same
US7157782B1 (en) * 2004-02-17 2007-01-02 Altera Corporation Electrically-programmable transistor antifuses
US7649229B2 (en) * 2006-03-31 2010-01-19 Oki Semiconductor Co., Ltd. ESD protection device

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5237395A (en) 1991-05-28 1993-08-17 Western Digital Corporation Power rail ESD protection circuit
US5410254A (en) * 1993-03-04 1995-04-25 Lsi Logic Corporation Method for optimizing the structure of a transistor to withstand electrostatic discharge
US5486716A (en) * 1991-05-14 1996-01-23 Seiko Instruments Inc. Semiconductor integrated circuit device with electrostatic damage protection
US5504362A (en) * 1992-12-22 1996-04-02 International Business Machines Corporation Electrostatic discharge protection device
US5532178A (en) 1995-04-27 1996-07-02 Taiwan Semiconductor Manufacturing Company Gate process for NMOS ESD protection circuits
US5546055A (en) * 1995-08-24 1996-08-13 Dallas Semiconductor Corp. Crystal oscillator bias stabilizer
US5654663A (en) * 1994-12-16 1997-08-05 Sgs-Thomson Microelectronics, Inc. Circuit for providing a compensated bias voltage
US5689133A (en) 1993-05-03 1997-11-18 Xilinx, Inc. ESD protection circuit

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2959528B2 (en) * 1997-06-09 1999-10-06 日本電気株式会社 Protection circuit
US6060752A (en) * 1997-12-31 2000-05-09 Siliconix, Incorporated Electrostatic discharge protection circuit
US6066879A (en) * 1999-05-03 2000-05-23 Taiwan Semiconductor Manufacturing Company, Ltd. Combined NMOS and SCR ESD protection device

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5486716A (en) * 1991-05-14 1996-01-23 Seiko Instruments Inc. Semiconductor integrated circuit device with electrostatic damage protection
US5237395A (en) 1991-05-28 1993-08-17 Western Digital Corporation Power rail ESD protection circuit
US5504362A (en) * 1992-12-22 1996-04-02 International Business Machines Corporation Electrostatic discharge protection device
US5410254A (en) * 1993-03-04 1995-04-25 Lsi Logic Corporation Method for optimizing the structure of a transistor to withstand electrostatic discharge
US5689133A (en) 1993-05-03 1997-11-18 Xilinx, Inc. ESD protection circuit
US5654663A (en) * 1994-12-16 1997-08-05 Sgs-Thomson Microelectronics, Inc. Circuit for providing a compensated bias voltage
US5532178A (en) 1995-04-27 1996-07-02 Taiwan Semiconductor Manufacturing Company Gate process for NMOS ESD protection circuits
US5546055A (en) * 1995-08-24 1996-08-13 Dallas Semiconductor Corp. Crystal oscillator bias stabilizer

Cited By (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6462389B2 (en) * 2000-01-27 2002-10-08 Hyundai Electronics Industries Co., Ltd. Semiconductor device
US20020195671A1 (en) * 2000-01-27 2002-12-26 Hyundai Electronics Industries Co., Ltd. Semiconductor device
US7091094B2 (en) * 2000-01-27 2006-08-15 Hynix Semiconductor Inc. Method of making a semiconductor device having a gate electrode with an hourglass shape
US6545322B2 (en) * 2000-11-01 2003-04-08 Seiko Instruments Inc. Semiconductor protection device
US6563175B2 (en) * 2001-09-24 2003-05-13 Texas Instruments Incorporated NMOS ESD protection device with thin silicide and methods for making same
FR2831328A1 (en) * 2001-10-23 2003-04-25 St Microelectronics Sa Integrated circuit has metal oxide semiconductor transistors which are integrated in supply rail and below supply conductors, to short-circuit conductors for protection against electrostatic discharge and overvoltage
US6818953B2 (en) 2001-10-23 2004-11-16 Stmicroelectronics S.A. Protection of an integrated circuit against electrostatic discharges and other overvoltages
EP1309005A1 (en) * 2001-10-23 2003-05-07 STMicroelectronics S.A. Protection of an integrated circuit against ESD and other overvoltages
US7078283B1 (en) 2002-08-07 2006-07-18 Taiwan Semiconductor Manufacturing Company Process for providing ESD protection by using contact etch module
US20040120085A1 (en) * 2002-12-19 2004-06-24 Renesas Technology Corp. Semiconductor device with surge protection circuit
US7129546B2 (en) 2003-12-22 2006-10-31 Vanguard International Semiconductor Corporation Electrostatic discharge protection device
US20050133871A1 (en) * 2003-12-22 2005-06-23 Vanguard International Semiconductor Corporation Electrostatic discharge protection device
US7718480B1 (en) * 2005-05-26 2010-05-18 National Semiconductor Corporation ESD clamps and NMOS arrays with increased electrical overstress robustness
US20090283832A1 (en) * 2008-05-16 2009-11-19 Kabushiki Kaisha Toshiba Semiconductor device
US8072030B2 (en) * 2008-05-16 2011-12-06 Kabushiki Kaisha Toshiba Semiconductor device
US9343457B2 (en) * 2013-03-06 2016-05-17 STI Semiconductor Corporation Semiconductor device
US9640527B2 (en) * 2015-06-02 2017-05-02 United Microelectronics Corp. Electrostatic discharge protection device with parasitic bipolar junction transistors
US10763205B2 (en) 2017-07-13 2020-09-01 Seagate Technology Llc Input/output cell wire connector
CN112987358A (en) * 2021-02-20 2021-06-18 Tcl华星光电技术有限公司 Driving chip and display device having the same
CN112987358B (en) * 2021-02-20 2022-09-09 Tcl华星光电技术有限公司 Driving chip and display device having the same

Also Published As

Publication number Publication date
US6441438B1 (en) 2002-08-27

Similar Documents

Publication Publication Date Title
US6258672B1 (en) Method of fabricating an ESD protection device
US6891230B2 (en) Bipolar ESD protection structure
CN102214655B (en) Integrated circuit and method for reduced trigger voltage ofstacked ESD protection circuit
KR100642651B1 (en) Semiconductor controled rectifier for electro-static discharge protecting
US7098510B2 (en) Multifinger-type electrostatic discharge protection element
US7985644B1 (en) Methods for forming fully segmented salicide ballasting (FSSB) in the source and/or drain region
US5717559A (en) Input/output protection device for use in semiconductor device
US6541824B2 (en) Modified source side inserted anti-type diffusion ESD protection device
US7277263B2 (en) Local ESD protection for low-capacitance applications
US8630072B2 (en) Circuits including a diode string comprised of bipolar stages having an adjustable pseudo beta for ESD protection
CN106030808B (en) Segmented NPN vertical bipolar transistor
US6645820B1 (en) Polycrystalline silicon diode string for ESD protection of different power supply connections
US20060097322A1 (en) Electrostatic discharge (ESD) protection circuit
TWI248193B (en) Electrostatic discharge device
US20050285200A1 (en) Device for electrostatic discharge protection
US10177136B2 (en) Electrostatic discharge protection device for high voltage
KR20060006036A (en) Low voltage silicon controlled rectifier (scr) for electrostatic discharge (esd) protection on silicon-on-insulator technologies
US7064358B2 (en) Triggered back-to-back diodes for ESD protection in triple-well CMOS process
US10600775B2 (en) Electrostatic discharge protection device
US9502399B1 (en) Diode string circuit configurations with improved parasitic silicon-controlled rectifier (SCR) conduction during electrostatic discharge (ESD) events
EP0703621B1 (en) Electrostatic discharge protection device for MOS integrated circuits
US20110266624A1 (en) Electrostatic discharge protection having multiply segmented diodes in proximity to transistor
US6469325B1 (en) Semiconductor integrated circuit device and its manufacture
US6825504B2 (en) Semiconductor integrated circuit device and method of manufacturing the same
US7449751B2 (en) High voltage operating electrostatic discharge protection device

Legal Events

Date Code Title Description
AS Assignment

Owner name: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, TAIWAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:SHIH, JIAW-REN;LEE, JIAN-HSING;HWANG, HUEY-LIANG;REEL/FRAME:009803/0528

Effective date: 19981224

STCF Information on status: patent grant

Free format text: PATENTED CASE

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12