US6209034B1 - Remote keyboard macros activated by hot icons - Google Patents

Remote keyboard macros activated by hot icons Download PDF

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Publication number
US6209034B1
US6209034B1 US08/543,788 US54378895A US6209034B1 US 6209034 B1 US6209034 B1 US 6209034B1 US 54378895 A US54378895 A US 54378895A US 6209034 B1 US6209034 B1 US 6209034B1
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United States
Prior art keywords
wireless interface
interface device
pen
system
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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US08/543,788
Inventor
S. Christopher Gladwin
James Y. Wilson
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NEC Corp
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NEC Corp
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Publication date
Priority to US08/300,500 priority Critical patent/US6292181B1/en
Application filed by NEC Corp filed Critical NEC Corp
Priority to US08/543,788 priority patent/US6209034B1/en
Assigned to ZENITH DATA SYSTEMS CORPORATION reassignment ZENITH DATA SYSTEMS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: WILSON, JAMES Y., GLADWIN, S. CHRISTOPHER
Assigned to PACKARD BELL NEC reassignment PACKARD BELL NEC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ZENITH DATA SYSTEMS CORPORATION
Assigned to NEC CORPORATION reassignment NEC CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PACKARD BELL NEC, INC.
Publication of US6209034B1 publication Critical patent/US6209034B1/en
Application granted granted Critical
Assigned to WARREN & LEWIS INVESTMENT CORPORATION reassignment WARREN & LEWIS INVESTMENT CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION
Anticipated expiration legal-status Critical
Assigned to NEC CORPORATION reassignment NEC CORPORATION NOTICE OF TERMINATION Assignors: WARREN & LEWIS INVESTMENT CORPORATION
Assigned to NEC CORPORATION reassignment NEC CORPORATION NUNC PRO TUNC ASSIGNMENT (SEE DOCUMENT FOR DETAILS). Assignors: COMMIX SYSTEMS, LCC, WARREN & LEWIS INVESTMENT CORPORATION
Assigned to NEC CORPORATION reassignment NEC CORPORATION CORRECTIVE ASSIGNMENT TO CORRECT THE SECOND CONVEYING PARTY NAME PREVIOUSLY RECORDED AT REEL: 037209 FRAME: 0592. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Assignors: COMMIX SYSTEMS, LLC, WARREN & LEWIS INVESTMENT CORPORATION
Application status is Expired - Lifetime legal-status Critical

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Abstract

The present invention relates to a wireless interface device and more particularly to a wireless interface device for interfacing with a host computer in a stand-alone configuration or either a wired or wireless local area network (LAN). The wireless interface device is a pen-based device and includes a passive stylus as an input device. In order to facilitate operation of the system, the wireless interface device is provided with one or more user-defined hot icons, which, in response to a pen-down event, can be used to activate a keyboard macro.

Description

CROSS-REFERENCE TO RELATED CASES

This case is a continuation-in-part of the following copending application: STRUCTURE AND METHOD FOR CONTROLLING A HOST COMPUTER USING A REMOTE HAND-HELD INTERFACE DEVICE, by B. R. Banerjee, S. C. Gladwin, A. Maskatia and A. Soucy, filed Sep. 2, 1994, Ser. No. 08/300,500. This case is also related to the following copending applications, all filed on even date: REMOTE CONTROL INTERFACE, by B. R. Banerjee, S. C. Gladwin, A. Maskatia and A. Soucy Ser. No. 08/543,700; RADIO FLASH UPDATE, by D. Bi, H. Hsiung and J. Wilson, Ser. No. 08/543,463; MOUSE EMULATION WITH PASSIVE PEN, by D. Bi, G. Cohen, M. Cortopassi, J. George, S.C. Gladwin, H. Hsiung, P. Lim, J. Parham, A. Soucy, D. Voegeli and J. Wilson, Ser. No. 08/543,786; RESUME ON PEN CONTACT, by M. Cortopassi, S. C. Gladwin and D. Voegeli, Ser. No. 08/543,510; SCREEN SAVER DISABLER, by D. Bi, S. C. Gladwin and J. Wilson, Ser. No. 08/543,698; IPX DRIVER FOR MULTIPLE LAN ADAPTERS, by D. Bi, Ser. No. 08/553,808; DISASTER RECOVERY JUMPER, by M. Cortopassi, J. George, J. Parham and D. Voegeli, Ser. No. 08/543,423; RC TIME CONSTANT, by M. Cortopassi, Ser. No. 08/543,697; DOUBLE PEN UP EVENT, by D. Bi and J. George, Ser. No. 08/543,787; REMOTE OCCLUSION REGION, by J. Wilson, Ser. No. 08/543,701; BROADCAST SEARCH FOR AVAILABLE HOST, by D. Bi, S. C. Gladwin and J. Wilson, Ser. No. 08/543,599; HOST/REMOTE CONTROL MODE, by M. Cortopassi, J. George, S. C. Gladwin, H. Hsiung, P. Lim, J. Parham, D. Voegeli and J. Wilson, Ser. No. 08/551,936; PASSWORD SWITCH TO OVERRIDE REMOTE CONTROL, by D. Bi, S. C. Gladwin and J. Wilson, Ser. No. 08/543,785; AUTOMATIC RECONNECT ON REQUIRED SIGNAL, by S. C. Gladwin and J. Wilson, Ser. No. 08/543,425; and PORTABLE TABLET, by G. Cohen, S. C. Gladwin, P. Lim, J. Smith, A. Soucy, K. Swen, G. Wong, K. Wood and G. Wu, Ser. No. 29/045,319.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a wireless interface device and more particularly to a wireless interface device for interfacing with a host computer. The wireless interface device takes control of the host computer and mirrors anything that the host computer is displaying on its own display. In order to facilitate use of the wireless interface device, one or more user-defined hot icons are provided which allow for keyboard macros over the wireless interface.

2. Description of the Prior Art

Both wired and wireless LAN systems are known in the art. Such systems enable various desktop and/or portable personal computers to be connected in a local area network in order to share resources. Wireless LAN systems are normally used in an office environment to enable the various users to share common resources while obviating the need for direct wire connections between the personal computers connected to the LAN.

The personal computers connected to a wireless LAN configuration are normally equipped with a wireless LAN card and a radio interface which typically includes a spread-spectrum type radio to reduce interference.

As mentioned above, portable personal computers have been known to be used in such wireless LAN systems. However, portable personal computers, even such notebook-size portable personal computers, are cumbersome to transport in an office environment. Unfortunately, the resources of the LAN system are often needed at locations other than where the personal computers connected to the LAN are located.

Pen-based personal computers can also be connected in a local area network. Such pen-based portable computers normally use a stylus as an input device. Thus, when such pen-based portable personal computers are utilized in facilities, such as keyboard macros, are unavailable.

SUMMARY OF THE INVENTION

It is an object to solve various problems with the prior art.

Briefly, the present invention relates to a wireless interface device for interfacing with either a host computer in a stand-alone configuration or either a wired or wireless local area network (LAN). The wireless interface device is a pen-based device and includes a passive stylus as an input device. In order to facilitate operation of the system, the wireless interface device is provided with one or more user-defined hot icons, which, in response to a pen-down event, can be used to activate a keyboard macro.

BRIEF DESCRIPTION OF THE DRAWING

These and other objects of the present invention will be readily understood upon consideration of the following detailed description and attached drawing, wherein:

FIG. 1 is a block diagram of the hardware configuration of a wireless interface device in accordance with the present invention and a host computer;

FIG. 2 is a block diagram illustrating the access of the wireless interface device in accordance with the present invention and a wired local area network;

FIG. 3 is a diagram illustrating the software structure for the wireless interface device in accordance with the present invention;

FIG. 4 is a block diagram showing one implementation of the wireless interface device of FIG. 1;

FIG. 5 is a state diagram illustrating the six internal power management states of the wireless interface device;

FIG. 6 is a block diagram illustrating the operational states of the wireless interface device under the control of dedicated Viewer Manager software in accordance with the present invention;

FIG. 7 is a block diagram of the software environment under which the wireless interface device and the host computer operate to provide remote control of the host computer;

FIG. 8 is a block diagram which shows in further detail the software environment in the host computer, running an application program under a Windows environment;

FIG. 9 is a block diagram which shows in further detail the software environment in the wireless interface device, running in a normal operation state;

FIG. 10 is a block diagram illustrating the method used in the wireless interface device to anticipate a pen/mouse mode decision;

FIGS. 11-30 are schematic diagrams of the wireless interface device in accordance with the present invention;

FIGS. 31-35 are flow charts relating to mouse emulation with a passive pen;

FIG. 36 is a plan view of the wireless interface device illustrating the hot icon area and viewing area of the display;

FIG. 37 illustrates the hot icons in the hot icon area of the display;

FIGS. 38, 39 and 40 are flow charts relating to a system for disabling the screen saver to reduce LAN traffic;

FIG. 40A is a flow chart relating to a host access protection password system;

FIGS. 41-43 are flow charts relating to a system for handling pen-up events;

FIG. 44 is a configuration diagram illustrating the wireless interface device interfacing with a wired LAN system;

FIG. 45 is a diagram of the software structure of a known network system;

FIG. 46 is a diagram of the software structure of network system which enables the wireless interface device to interface with the wired LAN system, illustrated in FIG. 44;

FIGS. 47-52 are flow charts relating to the seamless integration of wired and wireless LANS;

FIGS. 53-57 are illustrations of various set-up dialog boxes available on the wireless interface device;

FIG. 58 is a flow chart relating to the host control mode;

FIG. 59 is a flow chart relating to a system for broadcasting for available hosts;

FIGS. 60 and 61 are flow charts relating to a system for providing remote keyboard macros on the wireless interface device;

FIGS. 62A-62C, 63A and 63B are flow charts relating to a wireless flash ROM programmer;

FIGS. 64A and 64B are flow charts relating to a system for providing automatic reconnection of the host;

FIGS. 65A and 65B are flow charts relating to providing a remote occlusion region on the wireless interface device; and

FIGS. 66A-66D illustrate the various configurations of an on-screen keyboard available on the wireless interface device.

DETAILED DESCRIPTION OF THE INVENTION

1. General

The present invention relates to a system which allows wireless access and control of a remote host computer, which may be either a desktop, tower or portable computer to enable remote access of the various files and programs on the host computer. The system not only allows access to remote host computers that are configured as stand-alone units but also provides access to both wired and wireless local area networks (LAN).

The system includes a wireless interface device which includes a graphical user interface (GUI) which allows various types of input. In particular, input to the wireless interface device is primarily by way of a passive stylus, which can be used in a pen mode or a mouse mode. In a pen mode, a trail of ink tracking the path of the stylus (pen paradigm) provides visual feedback to the user by way of a pen digitizer. In a mouse mode, however, a cursor may be generated which follows the “tip” of the pen, but the path of cursor motion is not inked.

A virtual keyboard is also provided as part of the GUI. Activation of the keys on the virtual keyboard is by way of the stylus or by finger input. In addition, the system also supports a full-size external keyboard.

FIG. 1 illustrates a block diagram of the system 10 in accordance with the present invention. In particular, a wireless interface device 100, in accordance with the present invention, enables wireless access of a remote host computer 101, configured as either a stand-alone unit or as a part of a wired or wireless local area network (LAN). When the remote host computer 101 is in a stand-alone configuration, as illustrated in FIG. 1, communication between the remote host computer 101 and the wireless interface device 100 is by way of a wireless communication link, provided by a communication subsystem 118 in which the remote host computer 101 is provided with a transceiver 115 for radio communication with a transceiver 116 in the wireless interface device 100. For example, the desktop or remote host computer 101 can be provided with a PCMCIA interface which can be used with a wireless transceiver card to communicate with the transceiver 116 in the wireless interface device 100. Alternatively, an Industry Standard Architecture (ISA) card transceiver can be installed in the host computer 101 in a spare ISA expansion slot. In particular, the transceivers 115 and 116 may be implemented as 2.4 GHz radio frequency (RF) transceiver modules with a Wireless Media Access Control function, available from Proxim Inc., Mountain View, Calif., configured with either an ISA or PCMCIA interface.

As mentioned above, the wireless interface device 100 can also be used with a wireless LAN in a peer-to-peer network or a wired LAN. FIG. 2 illustrates the communication between the wireless interface device 100 and a wired LAN 114, which includes a server 108 in a, for example, Novell Netware or Microsoft LAN Manager environment. In this mode, the transceiver 116 in the wireless interface device 100 communicates with an access point 109 by way of a transceiver (not shown), which interfaces the wireless interface device 100 with a wired LAN 114 which includes a server 108. Alternatively, the wireless interface device 100 can be used in a wireless network in a Windows for Workgroups or Personal Netware environment, for example.

The configuration of the radio communication subsystem between the wireless interface device 100 and the remote host computer 101 or access point 109 conforms to the Open System Interconnection (OSI) reference model for data communications and implements the lower two layers of the seven-layer OSI model. In particular, with reference to FIG. 3, the physical layer 107 (WIRELESS PHY) may be a 2.4 GHz spread spectrum frequency hopping radio which replaces the LAN cable normally connected between workstations. The radio operates within the 2.4000-2.4835 GHz band, the unlicensed Industrial Scientific and Medial (ISM) band, and is divided into eighty-two 1 MHz channels. In a spread-spectrum, frequency-hopping radio, data is broadcast on one particular channel for a predetermined time (i.e. 400 msec); and then the system hops to another channel in a predetermined pattern to avoid interference.

The wireless media access control (WIRELESS MAC) 106 is used to interface to higher level software 105 (i.e. NOS SHELL, NOVELL, MICROSOFT) through network drivers 104 (i.e. LINK LEVEL INTERFACE (ODI, NDIS)). The MAC conforms to the industry standard protocol is in accordance with IEEE 802.11.

As shown in FIG. 1, the wireless interface device 100 includes a central processing unit (CPU) 112, a local memory system 111, a pen-based input subsystem (STYLUS) 110, a display subsystem 113 and a transceiver 116. As will be discussed in more detail below, the wireless interface device 100 includes a Viewer Manager software 200 (FIG. 6) which performs three (3) basic functions: (i) collecting and transmitting input positional information from a stylus input subsystem 110 to the host computer 101, (ii) receiving from the host computer 101 a video image to be displayed on the display subsystem 113, and (iii) managing the communications link between the wireless interface device 100 and the host computer 101.

The wireless interface device 100 is thus able to control and access various programs such as Windows and Windows application programs and files residing at the host computer 101 and display the results in its display 113.

2. Description of the Block Diagram

FIG. 4 is a block diagram of the wireless interface device 100. As shown in FIG. 4, the wireless interface device 100 has both a processor or “local bus” 150 and an ISA bus 151. The local bus 150 operates at the clock rate of the CPU 112, while the ISA bus 151 operates at the industry standard 8 MHz clock rate. The CPU 112 may be implemented by a microprocessor, which allows suspension and resumption of operation by halting and restarting the system clock to reduce battery consumption. Because power management in a portable device is important, the CPU 112 should preferably support power management functions, such as System Management Mode (SMM) and System Management Interrupt (SMI) techniques known in the industry. One example of a suitable microprocessor is the AMD386DXLV, available from Advanced Micro Devices, Inc., Sunnyvale, Calif., which operates at up to 25 MHz at a 3.0V supply voltage.

The CPU 112 interfaces over local bus 150 with a system controller 129. The system controller 129 manages (i) system operation, including the local and ISA buses 150 and 151, (ii) memory, and (iii) power to the system. The system controller 129 may be, for example, a Model No. 86C368 integrated circuit, available from PicoPower Technology, Inc., San Jose, Calif.

The present implementation takes advantage of the several levels of power management supported by the system controller 129. Power management in the present implementation is described in further detail below.

The system controller 129 provides a dynamic random access memory (DRAM) controller and a non-volatile random access memory (NVRAM) controller to control the DRAM 111A and a non-volatile RAM, NVRAM 111B, which form a portion of the memory subsystem 111 (FIG. 1) in the wireless interface device 100. As shown in FIG. 4, the DRAM 111A in the wireless interface device 100 may be provided by four 16-bit by 256K DRAM memory chips, to provide a total of 2 megabytes of memory, while the NVRAM 111B, used to store configuration data and passwords, for example, may be implemented using E2PROM technology to provide permanent storage.

All devices on the ISA bus 151 are managed by an integrated peripheral controller (IPC) 128. The IPC 128 provides various functions including direct memory access (DMA) control, interrupt control, a timer, a real time clock (RTC) controller, and a memory mapper for mapping peripheral devices to the system memory space as illustrated in Table 4 below. The IPC 128 may be implemented by a Model No. PT82C206 integrated circuit, also available from the aforementioned PicoPower Technology, Inc.

The stylus input subsystem 110 is implemented by a stylus, a pen controller 110A and a digitizer panel 110B. The pen controller 110A controls the digitizer panel 110B and provides positional information of pen or stylus contact. The pen controller 110A can be implemented, for example by a Model No. MC68HC705J2 microcontroller, available from Motorola, Inc. In this implementation, the digitizer panel 110B can be, for example, an analog-resistive touch screen, so that the stylus is sensed by mechanical pressure. Using a digitizer panel which senses mechanical pressure allows a “dumb” stylus, or even the human finger, to be used as an input device. When using a dumb stylus, switching between mouse and pen modes is accomplished by selecting an icon as discussed below. Alternately, other styli, such as a “light pen” or an electronic stylus with various operating modes, can also be used. In some electronic stylus', switching between pen and mouse modes can be achieved by pushing a “barrel button” (i.e. a switch located on the barrel of the stylus).

As mentioned above, the wireless interface device 100 includes a display subsystem 113 which, in turn, includes a liquid crystal display (LCD) 113C. The LCD 113C is controlled by a video controller 113A, and supported by video memory 113B. The video controller 113A can be implemented by a Model No. CL-GD6205 video controller, available from Cirrus Logic Corporation, Milpitas, Calif. The LCD 113C can be, for example, a monochrome display, such as the Epson EG9015D-NZ (from Epson Corporation), or an active matrix color display. The video memory 113B may be implemented as DRAMs, organized as 256K by 16 bits.

The video controller 113A communicates with video memory 113B over a separate 16-bit video bus 113D. In this implementation, the video controller 113A provides “backlighting” support through a backlight control pin BACKLITEON that is de-asserted to conserve power under certain power management conditions as discussed below.

As discussed above, the communication subsystem 118 allows communication with a remote host computer 101 in either a stand-alone configuration or connected to either a wired or wireless LAN. The communication system 118 includes the transceiver 116, an antenna 116A, and an RF controller 114A for interfacing with the local ISA bus 151.

The wireless interface device 100 also includes a keyboard controller 125 which performs, in addition to controlling an optional keyboard by way of a connector, various other functions including battery monitoring and LCD status control. The keyboard controller 125 can be implemented by a Model No. M38802M2 integrated circuit from Mitsubishi Corporation, Tokyo, Japan. Battery power to the wireless interface device 100 may be provided by an intelligent battery pack (IBP) 131, for example, as described in U.S. patent application Ser. No. 07/975,879, filed on Nov. 13, 1992, hereby incorporated by reference, connected to a system power supply module 133 by way of a battery connector 132. The IBP 131 maintains and provides information about the remaining useful battery life of IBP 131, monitored by keyboard controller 125. Upon the occurrence of a significant event relative to the IBP 130, e.g. battery remaining life falling below a preset value, the keyboard controller 125 generates an interrupt signal.

A serial port is provided and implemented by way of a universal asynchronous receiver transmitter (UART) 134, which can be accessed externally via a serial port connector 135. As will be discussed in more detail below, the serial port connector 135 allows for disaster recovery for the flash memory 117, which may be used to store the basic input/output (BIOS) for the CPU 112.

3. Power Management

In order to conserve battery power, the wireless interface device 100 incorporates power management. While a user of the wireless interface device 100 would normally only be aware of four power management states: “off”; “active”; “suspend”; and “sleep” modes, internally six power management states are implemented as shown in FIG. 5. More particularly, with reference to FIG. 5, before the wireless interface device 100 is powered up, the wireless interface device 100 is in an “off” state, indicated by the reference numeral 160. In an “off” state 160, no power is supplied to the system. A state 161 (the “active” state) is entered when the power switch (FIG. 28) to the wireless interface device 100 is turned to the “on” position. In the active state 161, all components of wireless interface device 100 are active. From active state 161, the wireless interface device 100 enters a “local standby” state 162. The local standby state 162 is transparent to the user of the wireless interface device 100. From the user's point of view, in the local standby state 162, the wireless interface device 100 is in active mode. In this state 162, specific inactive devices are each put into a static state after a predetermined time-out period of inactivity for that device. In a static state, each device consumes minimal power. In the local standby state 162, devices that can be put into static states include the CPU 112, the video controller 113A, the pen controller 110A, the UART 134, and the transceiver 116. Backlighting of the LCD video display is also disabled in local standby state 162. If not, input activities are detected by the keyboard controller 125 or pen controller 110A. After the later of their respective present time-out periods, these devices are placed in a static state. These devices emerge from the static state once an activity relevant to its operation is detected, e.g. a pen event is detected.

The user of the wireless interface device 100 can place the wireless interface device 100 in a “sleep” mode 163 by selecting an icon (FIG. 37) labelled “sleep” from the GUI as will be discussed below. Alternatively, the “sleep” mode may be entered from the active state 161 after a preset period of inactivity. In a “sleep” mode, corresponding to either “sleep” state 163 or “active sleep” state 164, the display subsystem 113 is switched off; and most devices are placed in static states. When a keyboard or pen event is detected, the sleep state 163 and active sleep state 164 are exited, and the wireless interface device 100 enters the active state 161. From the sleep state 163, an active sleep state 164 is entered when a communication packet is received from the host computer 101. Although the display subsystem 113 is turned off, the received communication packet can result in an update to an image stored in the video memory 113B. The CPU 112 handles the communication packet from the host computer 101 and activates the video controller 113A to update such an image. The active sleep state 164 is transparent to the user of the wireless interface device 100, since the updated image is not displayed on the LCD screen 113C. When the communication packet is handled, the wireless interface 100 returns to a sleep state 163. The device activities in wireless interface device 100 in “sleep” mode 163 are illustrated in Table 1 below.

TABLE 1 CLOCKS WAKEUP DEVICE STATE DISABLED COMMENTS SOURCE Microprocessor Static Clock Stop Static Mode Clock Restartcd Suspend Control by entered when and Controlled the system clock stopped by the system controller controller System Static Clock Activity on Controller Suspend Stopped/32 EXACT, KHz Left SWITCH, or on RING pins Peripheral Static 32 KHz Any Interrupts Controller Source Main Memory Slow System Memory Refresh controller Refreshed at 128 mS 38 KHz Video Static 14 MHz Controlled through When system is disconnected use of system resumed controller power management pins Video Memory Slow 32 KHz Memory Video Controller Refreshed at 128 mS Refresh automatically adjusts refresh rate depending on mode LCD Module OFF NA Power to Module will Controlled by never be applied Video controller in Sleep power up sequencing LCD Backlight OFF NA BackLight will never Controlled by be on in Sleep Video controlier power up sequencing UART Static 1.84 MHz Part has no direct power management UART Trans. Off NA Part turned off, until Access to serial port access to UART. Inactivity timer will start, and look for a time-out of two minutes before turning off transceiver ROM Static NA After ROM is shadowed, the CS and {overscore (OE)} line will be driven high to keep these parts in a static mode NVRAM Static NA After NVRAM is read, the CS line will be high which forces part into a static mode Pen Controller Sleep Own 4.0 Sleeps after each point is Pen Down wakes up Pen MHz processed as long as the controller. Pen controller pen is not pressing the asserts the PEN_ACTI- screen VITY signal which will wake up the entire system. Hook Active Own 32 Keeps the last display as NA KHz told by the keyboard controller Clock Generator Active All Clocks Clocks needed in order Running to wake system back up Radio Sleep Intemal Radio Handles its Wakes up on periodic basis own power management in order to keep SYNC. When a packet is ready, the Radio will assert the activity pin to the EXPACT input of the system controller which will wake up the system

Upon expiration of a timer, the wireless interface device 100 enters into an internal state “suspend” mode 165. In a suspend mode, the wireless interface device 100 is essentially turned off and communication packets from the host computer 101 are not handled. The wireless interface device 100 emerges from suspend state 165 into active state 161 when a pen event is detected.

As mentioned above, the video controller 113A supports various power management modes internal to the display subsystem 113. Power is conserved in display subsystem 113 by entering “standby” and “suspend” modes. In the video controller 113A's “standby” mode, which can be entered by (i) expiration of a timer internal to the video controller 113A, (ii) firmware in the video controller 113A, or (iii) a signal received from system controller 129 on the video controller 113A's “STANDBY” pin. In the video controller 113A's standby mode, the LCD 113C is powered down and the video clock is suspended. The video controller 113A exits the standby mode either under firmware control, or upon system controller 129's de-asserting video controller 113A's STANDBY pin. Upon exiting standby mode, the LCD 113C is powered and the video clock becomes active. In this implementation, the LCD 113C includes multiple power planes (“panels”). For reliability reasons, in a powering up or powering down operation, these panels in the LCD display are preferably powered in a predetermined sequence specified by the manufacturer.

Maximum power is conserved in the display subsystem 113 when video controller 113A enters the “suspend” mode. The suspend mode can be entered either by asserting a signal from the system controller 129 on the SUSPEND pin of video controller 113A, or under firmware control. In this implementation, if the suspend mode is entered from the SUSPEND pin, the CPU 112 is prevented from accessing the video RAM 113B and video bus 113D. In that state, the contents of configuration registers in the video controller 113A are saved, to be restored when suspend mode is exited. In the suspend mode, the video RAM 113B is refreshed using the lowest possible refresh clock rate.

4. General Description of Operation

FIG. 6 is a block diagram illustrating the operational states of wireless interface device 100 under the control of the Viewer Manager software 200. As shown in FIG. 6, on power up, the wireless interface device 100 enters into a “TABLET SECURITY” state 201, in which an optional security step is performed. In the state 201, either the device 100 automatically shuts off after an idle period or the user performs a “log on” procedure which, as a security measure, identifies and validates the user. Then, at decision point 202, the Viewer Manager software 200 then determines if a procedure to set up a communication link is preconfigured. If so, a communication link is established automatically with the host computer 101 and the Viewer Manager software 200 goes into the normal operation state 205, which is described in further detail below. If a communication link is not preconfigured, a manual procedure is performed in state 203, in which the desired host computer 101 is identified and connected. From state 203, either the device 100 automatically shuts off after an idle period or the user continues on and enters normal operation state 205.

In normal operation state 205, the wireless interface device 100 controls the program running in the host computer 101, in accordance with the input data received from stylus input subsystem 110. The positions of the stylus in stylus input subsystem 110 are delivered to the host computer 101, which generates display commands to the wireless interface device 100. The CPU 112 executes the display commands received, which may result in an update of the LCD 113C. In this embodiment, either a direct user command or inactivity over a predetermined time period causes the wireless interface device 100 to enter a “HOT-STANDBY” minimum power state (“sleep” mode), represented in FIG. 6 by block 204. In the minimum power state 204, to preserve battery power, the various operations of the wireless interface device 100's functional units are placed on standby status. If the status is put in contact with the digitizer panel, the wireless interface device 100 is reactivated, and control of the host computer 101 is resumed by re-entering state 205. Thereupon, wireless interface device 100 enters into a state 206, in which an auto-disconnect procedure is executed, which releases control of the host computer 101 and powers down the wireless interface device 100.

The user may also relinquish control of the host computer 101 from state 205 by selecting a manual disconnect function. When the manual disconnect function is selected, the wireless interface device 100 enters manual disconnect state 207, in which the connection to the host computer 101 is terminated. The wireless interface device 100 is then returned to state 201 to accept the next user validation.

FIG. 7 is a block diagram of the software environment 240 in which the wireless interface device 100 and the host computer 101 operate to provide the wireless interface device 100 remote control of the host computer 101. As shown in FIG. 7, a wireless communication system 250 is provided for communication between the host computer 101 and the wireless interface device 100. On the side of the wireless interface device 100, i.e. software environment 230A, a communication output manager software routine 252 controls transmissions of pen events over the wireless communication link 250 to a host communication input manager 262 in the host computer 101 (i.e. software environment 230B). The pen events include the position information of the stylus and tip-up and tip-down information. A pen event buffer 251 queues the pen events for transmission through a communications manager 252. In the software environment 230A, the communications input manager 254 receives from the wireless communication system 250 video events transmitted by host communication output manager 260 in the software environment 230B. These video events include graphical commands for controlling the LCD 113C. In the software environment 230A, the received video commands are queued in the video event buffer 256 to be processed by the CPU 112 as graphical instructions to the LCD 113C.

In the software environment 230B, i.e. in host computer 101, pen events are queued in pen event buffer 264, which may then be provided to the Pen Windows module 266. The Pen Windows module 266 processes the pen events and creates video events in a video event buffer 267, which is then transmitted to the wireless interface device 100 over wireless communication system 250.

FIG. 8 is a block diagram which shows in further detail the software environment 230B (FIG. 7) in the host computer 101; running an application program 270 under a Windows operating system 272. As shown in FIG. 8, the pen events queued in the pen event buffer 264 are provided to a pen event injector 274, which provides the pen events from the pen event buffer 264, one pen event at a time, to a buffer (“RC buffer”) 275 of the Recognition Context Manager module (the “RC manager”) 276 in Pen Windows. The RC buffer 275 holds a maximum of four pen events. The RC Manager 276 assumes that pen events are received at RC buffer 275 as they occur. Thus, if the Pen Windows system is presented with pen events faster than they are retrieved from RC buffer 275 without pen event injector 274, the pen events that arrive at RC buffer 275 when it is full are lost. The pen event injector 274 prevents such data loss. To provide this capability, the pen event injector 274 includes both Windows virtual device (V×D) and device driver (DRV) codes (not shown). The DRV portion removes a single pen event from pen event buffer 264 and delivers it to the RC buffer 275 using the normal Pen Windows add and process pen event mechanisms. Then the V×D portion reactivates the DRV code after a minimum time delay using a virtual machine manager service to retrieve the next pen event from pen event buffer 264. Those of ordinary skill in the art would appreciate that, under the terminology used in Windows, DRV code refers to a dynamically linked library in Windows which interacts with a hardware device (in this case, pen device buffer 264), and V×D code refers to a dynamically lined library which manages a sharable resource (in this case, the DRV code).

The RC Manager 276 examines each pen event in the RC buffer 275, and according to the context of the pen event in its possession, the RC Manager 276 determines whether the stylus is in the pen mode or in the mouse mode. In this embodiment, as will be discussed in more detail below, an icon allows the user to use the stylus as a “mouse” device. The icon, called “mouse button toggle”, allows the user to switch between a “left” button and a “right” button as used in an industry standard mouse device. The selected button is deemed depressed when the stylus makes contact with the pressure-sensitive digitizer panel. A rapid succession of two contacts with the display is read by the RC Manager 276 as a “double click”, and dragging the stylus along the surface of the display is read by the RC Manager 276 as the familiar operation of dragging the mouse device with the selected button depressed.

If the stylus is in the pen mode, the RC Manager 276 provides the pen event to a recognizer 277 to interpret the “gesture”. Alternatively, if the pen event is a mouse event, the RC Manager 276 provides the pen event as a mouse event for further processing in a module 278. The interpreted gestures or mouse events are further processed as input data to the Windows operating system 272 or the application program 270.

The output data from an application program, such as Windows 272 or application program 270, is provided to the video event buffer 267. These video events are transmitted to the host communications output manager 260 for transmission to the wireless interface device 100.

FIG. 9 is a block diagram which shows in further detail the software environment 230A in the wireless interface device 100 in the normal operation state 205 of the Viewer Manager 200. In FIG. 9, the stylus in the stylus input subsystem 110 and LCD video display 113C in the video display subsystem 113 are shown collectively as a digitizer-display device 279. In a normal operation state 205, the Viewer Manager 200 interacts with the application program 270 in the wireless interface device 100 by way of the Communications Output Manager 252 and the Communications Input Manager software 254. In addition, the Viewer Manager software 200 also receives digitized data from a digitizer 280, which, in turn, receives digitized data from stylus input subsystem 110. The Viewer Manager software 200 uses the digitized data to provide visual feedback to the user, which is discussed in further detail below. The Viewer Manager software 200 generates local video commands to a display driver 281. The display driver 281 also receives from video event buffer 256 video display commands from the host computer system 101.

At the core of the wireless interface device 100's user interface is the stylus's behavior under Pen Windows. Of significance in wireless interface device 100's design is the emulation of the natural “pen-and-shaper” interaction with the user. That is, in a pen mode, the stylus must leave ink as it moves across the surface of the screen in the same way that a pen leaves ink on paper. However, using Pen Windows software, the RC Manager 276, residing in the host computer 101, determines for each pen event whether the mouse or the pen mode is used.

If the wireless interface device 100 simplistically accesses the host computer 101 as a local device access, the wireless link between the host computer 101 and the wireless interface device 100 would be required to carry a minimum of 200 inking messages per second (100 stylus tip locations plus 100 line drawing commands). To maintain the pen-and-paper emulation, the wireless interface device 100 is further required to have a total processing delay (hence response time), including the overhead of the communication protocols, which is near or below the human perception level. In addition, noise in the transmission medium often leads to momentarily interruption of data transmission, or results in data corruption that requires re-transmission, thereby further reducing the throughput of the wireless link. To provide an acceptable level of performance, i.e., a high message-per-second communication rate and an acceptable propagation delay, a technique referred to as “local inking” is developed and applied to the wireless interface device 100's design, in accordance with the present invention. Without local inking, a high bandwidth communication link is required to meet the propagation delay requirement. Such a high bandwidth communication link is impractical, both in terms of cost and its impact on the portability of the resulting wireless access device.

With local inking, the Viewer Manager software 200 provides inking on the LCD 113C locally before the corresponding inking video events are received from the host computer 101. In this manner, visual feedback is provided virtually immediately without requiring either highly complex networking equipment, or very high performance and costly components in both the wireless interface device 100 and the host computer 101. Local inking provides both a real time response and an orderly handling of the stylus's data stream. Since local inking reduces the need for processing at the peak pen event rate of the stylus's data stream, the host computer 101 can thus apply normal buffering techniques, thereby reducing the bandwidth requirement on the communication network.

In one proposed industry standard for a stylus or pen-based system, namely the Microsoft Windows for Pen Computing system (“Pen Windows”), the pen mode requires (i) a pen driver that can deliver stylus tip locations every five to ten milliseconds (100 to 200 times per second), so as to achieve a resolution of two hundred dots per inch (200 dpi), and (ii) a display driver than can connect these dots in a timely manner. By these requirements, Pen Windows attempts to provide a real time response to maintain the pen paradigm. The Windows for Pen Computing system is promoted by Microsoft Corporation, Redmond, Wash. Details of the Pen Windows system are also provided in Windows version 3.1 Software Developer Kit obtainable from Microsoft Corporation. Under one implementation of the Pen Windows, a maximum of four stylus locations can be stored in a buffer of a module called “PENWIN.DLL” (for “Pen Window Dynamically Linked Library”). Consequently, in that implementation, the maximum latency allowed is twenty to forty milliseconds before any queue tip location is written. Each time the system fails to process a pen event within twenty to forty milliseconds of queuing, a stylus tip location is lost and there is a corresponding impact on the accuracy of the line being traced.

As mentioned above, the stylus is used in both pen mode and mouse mode. Since the RC Manager 276, running on the host computer 101, rather than a software module on the wireless interface device 100, determines whether a given pen event is a mouse mode event or a pen mode event, the Viewer Manager software 200 must anticipate which of these modes is applicable for that pen event. Further, should the anticipated mode prove to be incorrect, the Viewer Manager software 200 is required to correct the incorrectly inked image in video display subsystem 113.

FIG. 10 illustrates the method used in the wireless interface device 100 to anticipate the RC Manager 276's mode decision and to correct the image in the video display subsystem 113 when a local inking error occurs. As shown in FIG. 10, when the normal operational state 205 is entered, a pen control program (represented by the state diagram 282) in the Viewer Manager software 200 is initially in the mouse mode in state 283. However, even in the mouse mode, the trajectory of the stylus in contact with the pen digitizer is stored in the pen event buffer 284 until a mode message is received from the host computer 101. The pen event buffer 284 is separate from pen event buffer 251, which is used to transmit the pen events to the host computer 101. If the RC Manager 276 confirms that the stylus 110 is in a mouse mode, the accumulated pen events are discarded and the pen control program 282 waits for the last point on which the pen tip is in contact with the pen digitizer. Then the pen control program 282 returns to a state 283, in which the trajectory of the pen is again accumulated in the pen event buffer 284 until receipt of a mode message from the host computer 101. In state 283, the control program 282 assumes that the stylus will continue to be in the mouse mode.

Alternatively, while in state 283, if a mode message is received indicating the stylus is in the pen mode, the control program 282 enters state 288, in which the accumulated pen events are drawn locally onto the LCD screen of the video display subsystem 113 in accordance with the line style and color specified in the mode message. After all accumulated pen events in the pen event buffer 284 are drawn, the control program 282 enters a state 289, in which control program 282 continues to ink the trajectory of the tip of the stylus for as long as contact with the pen digitizer is maintained. Once the tip of the stylus breaks contact with the pen digitizer, the control program 282 enters state 287.

In state 287 the control program 282 assumes that the stylus will continue to be in the pen mode. Thus, local ink will follow the trajectory of the stylus while the top of the stylus remains in contact with the pen digitizer, or until a mode message is received from the host computer 101, whichever arrives earlier. Since the initial policy decision is a guess, the local inking is drawn using a single pixel-wide style and an XOR (“exclusive OR”) operation, in which the pixels along the trajectory of the stylus are inverted. While in state 287, the pen events associated with the trajectory of the stylus are accumulated in the pen event buffer 284.

If the mode message received in state 287 indicates that the stylus is in mouse mode, i.e. the policy decision was wrong, the control program 282 then enters a state 290, in which the accumulated pen events in pen event buffer 284 are used to erase the stylus stroke. Since the initial draw is accomplished by a bit XOR (“exclusive OR”) operation at the appropriate positions of the frame buffer, erasure is simply provided by the same XOR operation at the same positions of the frame buffer. The control program 282 then enters state 286. However, if the mode message received in state 287 confirms that the stylus is in pen mode, the accumulated pen events of pen event buffer 284 are used to redraw on the LCD 113C, using the line style and color specified on the mode message.

Under a convention of the Pen Windows software, starting a stroke of the stylus with the barrel button depressed (for active stylus systems) indicates an erase ink operation in pen mode. The control program 282 recognizes this convention and refrains from inking during this stroke without waiting for confirmation from the host computer 101. In addition, the control program 282 does not change modes across an erasing stroke: i.e., if the stylus is in the pen mode prior to the erase stroke, the stylus remains in the pen mode after the erase stroke; conversely, if the stylus is in the mouse mode prior to the erase stroke, the stylus remains in the mouse mode after the erase stroke.

Since all the pen events used in local inking on the wireless interface device 100 are also processed in the host computer 101, the trajectory of local inking must coincide identically with the line drawn at the host computer 101. Because of local inking, processing by the host computer 101 within the human perceptual response time is rendered unnecessary. Thus, in the host computer 101, the pen events can be queued at pen event buffer 264, to be retrieved one at a time by pen event injector 274. Hence, when pen event buffer 264 is suitably sized, data loss due to overflow by RC buffer 275 is prevented.

Alternatively, the control program 282 can also be implemented to follow a “retractable ball-point pen” paradigm. Under this paradigm, the user controls a local stylus mode of the stylus, such that inking occurs when the stylus is set to be in the local pen mode, and no inking occurs when the stylus is in the local mouse mode. If the local stylus mode conforms with the mode expected by Pen Windows, the image seen on the LCD display of the video display subsystem 113 is the same as described above with respect to state 287 of the control program 282. If the local stylus mode is the mouse mode, and Pen Windows software expects stylus 110 to be in the pen mode, the subsequent video events from host computer 101 would provide the required inking. Finally, if the local stylus mode is the pen mode and Pen Windows software expects the stylus to be in the mouse mode, inking would be left on the screen of video display subsystem 113. Under this paradigm, the user would eliminate the erroneous inking by issuing a redraw command to Pen Windows.

5. Detailed Description of the Schematic Diagrams

One embodiment of the invention is illustrated in the schematic drawings, FIGS. 11-30. Referring to FIG. 11, the system may include a CPU 112, such as an AMD Model No. AM386DXLV microprocessor. The CPU 112 includes a 32-bit data bus D[0..31] as well as a 32-bit address bus A[2..31]. Both the data bus D[0..31] as well as the address bus A[2..31] are connected to the processor bus 150 (FIG. 4), for example, an AT bus. As will be discussed in more detail below, the system controller 129 (FIG. 4) performs various functions including management of the processor bus 150. In order to conserve power, a 3-volt microprocessor may be used for the CPU 112. As such, a 3-volt supply 3V CPU is applied to the power supply VCC pins on the CPU 112. The 3-volt supply 3V_CPU is available from a DC-to-DC converter 300 (FIG. 26) by way of a ferrite bead inductor 302. In particular, the DC-to-DC converter 300 includes a 3-volt output, 3V_CORE. This output, 3V_CORE, is applied to the ferrite bead inductor 302 and, in turn, to the power supply pins VCC of the CPU 112. In order to prevent noise and fluctuations in the power supply voltage from affecting the operation of the CPU 112, the power supply voltage 3V CPU is filtered by a plurality of bypass capacitors 304 through 330.

The 3-volt supply 3V_CPU is also used to disable unused inputs as well as to pull various control pins high for proper operation. For example, the 3-volt power supply 3V_CPU is applied to the active low N/A and BS16 pins of the CPU 112 by way of a pull-up resistor 332. In addition, the signals BE[0..3], W/R, D/C, M/IO and ADS are pulled up by a plurality of pull-up resistors 334 through 348.

The CPU 112 is adapted to operate at 25 megahertz (MHz) at 3.0 volts. A 25 MHz clock signal, identified as CPU CLK, available from a clock generator 398 (FIG. 13), is applied to a clock input CLK2 on the CPU 112 by way of a resistor 349 and a pair of capacitors 351 and 353. The AMD Model No. AMD386DXLV microprocessor supports a static state, which enables the clock to be halted and restarted at any time.

The wireless interface device 100 includes a speaker 355. The speaker 355 is under the control of the system controller 129 (FIG. 12). In particular, a speaker control signal SPKR from the system controller 129 is applied to a source terminal of a field-effect transistor (FET) 357 for direct control of the speaker 355. The drain terminal is connected to the speaker 355 by way of a current-limiting resistor 359 and a bypass capacitor 371. Normally, the speaker 355 is active all the time. In particular, the gate terminal of the FET 357 is connected to the system ground by way of a resistor 373. The gate terminal of the FET 357 is also under the control of a speaker disable signal SPKRDISABLE, available from the keyboard controller 125 (FIG. 15). The speaker disable signal SPKRDISABLE is active high. Thus, when the speaker disable signal SPKRDISABLE signal is low, the FET 357 is turned on to enable the speaker signal SPKR from the system controller 129 to control the speaker 355. When the speaker disable signal SPKRDISABLE is high, the FET 357 is turned off to disable the speaker 355.

Referring to FIG. 12, the system controller 129 is connected between the local processor or AT bus 150 and the system ISA bus 151. The system controller 129 performs a variety of functions including that of system controller, DRAM controller, power management, battery management and management of the local AT bus 150. The system controller 129, preferably a PicoPower Pine Evergreen 3, Model No. 86C368 system controller, is a 208-pin device that operates at 33 MHz with a full 5-volt input or a hybrid 5-volt/3.3-volt input. At 3.3 volts the system controller 129 is adapted to reliably operate at 20 Mhz and perhaps up to 25 Mhz.

The system controller 129 includes several system features including support of several clock speeds from 16 to 33 MHz. In addition, the system controller 129 includes two programmable non-cacheable regions and two programmable chip selects, used for universal asynchronous receiver transmitter (UART) interface 134 and the radio interface 114B as discussed below.

The system controller 129 supports both fast GATE A20 and a fast reset control of the CPU 112. In particular, the system controller 129 includes a 32-bit address bus A[0..31] that is connected to the local AT bus 150. The address line A[20] is used to develop a signal CPUA20, which is applied to the A20 pin on the CPU 112 and also applied to an AND gate 379 (FIG. 11) to support a port 92H for a fast GATE A20 signal. A fast reset signal RSTCPU is also generated by the system controller 129. The fast reset signal RSTCPU is applied to the reset pin RESET of the CPU 112 for fast reset control.

The system controller 129 also provides various other system level functions. For example, the system controller 129 includes a register at address 300H. By setting bit 12 of this register, a ROM chip select signal ROMCS is generated, which enables writes to the flash memory system 117 (FIG. 25), which will be discussed below. A keyboard controller chip select signal KBDCS for the keyboard controller 125 (FIG. 15), as well as general purpose chip select signals GPCS1 and GPCS2 for selecting between the RF controller 114A, the UART 134 (FIG. 16) or the pen controller 110A (FIG. 21), are generated by the system controller 129.

The system controller 129 is connected to the system ISA bus 151 by way of a 16-bit system data bus SD[0..15] and a 24-bit system address bus SA[0..23] of which only 8-bits SA[0..7] are used. The system controller 129 is also connected to the 32-bit local processor data bus D[0..31], as well as the local processor address bus A[0..31].

All of the ground pins GND on the system controller 129 are tied to the system ground. Both 3-volt and 5-volt power supplies are applied to the system controller 129. In particular, a 5-volt supply 5V_EG is applied to the power supply pins VDD of the system controller 129. The 5-volt supply 5V_EG is available from DC-to-DC converter 300 (FIG. 26) by way of a ferrite bead inductor 381 (FIG. 12). More particularly, a 5-volt supply signal 5V_CORE from the DC-to-DC converter is applied to the ferrite bead inductor 381, which, in turn, is used to generate the 5-volt supply signal 5V_EG. In order to stabilize the 5-volt supply signal 5V_EG, a plurality of bypass capacitors 1101-1111 (FIG. 13) are connected between the 5-volt supply 5V_EG and system ground.

A 3-volt power supply 3V_EG is also applied to the system controller 129 and, in particular, to the power supply pins VDD/3V. This 3-volt supply 3V_EG is also obtained from the DC-to-DC converter 300 (FIG. 26) by way of a ferrite bead inductor 358. More particularly, 3-volt supply 3V_CORE, available at the DC-to-DC converter 300, is applied to the ferrite bead inductor 358, which, in turn, is used to generate the 3-volt power supply signal 3V-EG. A plurality of bypass capacitors 360, 362 and 364 are connected between the 3-volt supply 3V_EG and system ground for stabilizing.

The system controller 129 is reset by a reset signal RCRST (FIG. 20) on power up. The reset signal RCRST is developed by the 3-volt power supply 3V_EG, available from the DC-to-DC converter 300 (FIG. 26) and circuitry which includes a resistor 359, a capacitor 361 and a diode 363. Initially on power up, the capacitor 361 begins charging up from the 3-volt supply 3V_EG through the resistor 359. During this state, the diode 363 is non-conducting. As the capacitor charges, the level of the reset signal RCRST rises to reset the system controller 129. Should the system be turned off or the 3-volt supply 3V_EG be lost, the diode 363 provides a discharge path for the capacitor 361.

In order to assure proper operation of the system controller 129, a number of signals are pulled up to either five volts or three volts or pulled down by way of various pull-down resistors. More specifically, the signals IOCS16, MASTER, MEMCS16, REFRESH, ZWS, IOCHCK, GPI01/MDDIR and GPI02/MDEN are pulled up to the 5-volt supply 5V_EG by way of a plurality of pull-up resistors 1113-1129, respectively. Similarly, the signals BUSY, FERR, LOCAL, SMIADS and RDY are pulled up by a plurality of pull-up resistors 1131 through 1139. In addition, the general purpose chip select signals GPCS1 and GPCS2 are pulled up to the 5-volt power supply signal 5V_EG by way of a pair of pull-up resistors 375 and 377. Certain signals are pulled low by way of pull-down resistors in order to assure their operating state. In particular, the signals KBC-PO4, LB/EXTACT, RING, EXTACT/VLCLK and HRQ206 are pulled down by the pull-down resistors 388 to 396. The signal BLAST is tied directly to the system ground.

As mentioned above, the system controller 129 is capable of running at different clock frequencies, depending upon the voltage applied, while supplying a clock signal to the CPU 112. Even though the system controller 129 can supply either a 1X or a 2X clock signal to the CPU 112, the system controller 129 requires a 2X clock for proper operation. Thus, a 2X clock signal CLK2IN, available from a clock generator circuit 398 (FIG. 13), is applied to the clock 2X pin CLK2IN of the system controller 129. In addition, 32 kilohertz (KHz) and 14 megahertz (MHz) clock signals are also applied to the system controller 129, available from the clock generator circuit 398, for proper operation. The system controller 129, in turn, provides a CPU clock signal CPUCLK to the CPU 112 and in particular to its clock 2-pin CLK2 by way of a resistor 1141 and the capacitors 1143 and 1145.

The system controller 129 is adapted to be configured during an RC-RESET mode. In particular, the DRAM memory address lines MA[0..10], normally used for addressing the DRAM 111A (FIGS. 18 and 24), are pulled high or low in order to configure the system controller 129. More particularly, the DRAM memory address lines MA[0..10] are applied to either pull-up or pull-down resistors for configuration as illustrated in FIG. 17. Table 2 below illustrates the configuration shown.

TABLE 2 System Controller Configuration Table NAME FUNCTION DEFAULT STATE MA0 386 Select (Low = 46) High MA1 Low Power Select (High Selects Intel LP Low CPU, Low For Other) IX CPU Clock Select Low Low = 2X CPU CLK MA3 Not Used Low MA4 Not Used Low MAS 368 Pin Select (Low = pin High compatible with 268) MA6 Miscellaneous Configuration - 0 Low MA7 Not Used High MA8 Not Used Low MA9 Not Used Low MA10 Not Used Low

As shown, the DRAM memory address lines MA[0..10] are shown with bits MA0, MA5 and MA7 pulled high to the 3-volt power supply voltage 3V_EG by way of a plurality of pull-up resistors 400, 402 and 404. The remaining DRAM address line bits MA1, MA2, MA3, MA4, MA6, MA8, MA9 and MA10 are pulled low by a plurality of pull-down resistors 406 through 420, respectively. The DRAM memory address lines MA[0..8] are also coupled to a plurality of coupling resistors 422 to 438 form a 9-bit DRAM address bus BMA[0..8].

The system controller 129 functions as a DRAM controller and is capable of supporting up to 64 megabytes of memory, divided among one of four banks and can support 256K, 512K, 1M, 2M and 4M of memory in any width. The system controller 129 includes a pair of registers associated with each bank of DRAM. The first register stores the total amount of DRAM connected to the system while the second identifies the starting address for each bank. Referring to FIGS. 18 and 24, two 1 Mbyte banks are connected to the DRAM memory address bus BMA[0..8] and to the processor data bus 150, D[0..31].

In order to conserve power, 3-volt DRAM 111A is used. The 3-volt power supply 3V_RAM is applied to the VCC terminals of each of the DRAMS 111A. The 3-volt power supply 3V_RAM is available from the DC-to-DC converter 300 (FIG. 26) by way of a ferrite bead inductor 440 (FIG. 18). In particular, a 3-volt supply 3V_CORE available at the DC-to-DC converter 300 is applied to the ferrite bead inductor 440 to generate the 3-volt DRAM supply 3V_RAM. A plurality of bypass capacitors 425-439 (FIG. 18) are connected between the DRAM supply voltage 3V_RAM and system ground.

The system controller 129 generates the appropriate row address strobes (RAS) and column address strobes for the DRAM 111A. In particular, the column address strobe lines CAS0[0..3] are applied to the upper and lower column address strobe pins (UCAS and LCAS) on the DRAM 111A by way of a plurality of coupling resistors 442 to 450 (FIG. 12). Similarly, the row address signals RAS0 and RAS1 are applied to the row address strobe pins on the DRAM 111A by way of a plurality of coupling resistors 448 and 450. Writing to the DRAMS 111A is under the control of a DRAM write enable signal BRAMW, applied to the write enable pin WE on the DRAM 111A. The DRAM write enable signal BRAMW is generated by the system controller 129 by way of a coupling resistor 452.

An EEPROM or NVRAM 111B (FIG. 12) may be used to maintain system configuration parameters when the system is powered off. All user changeable parameters are stored in the EEPROM 111B. For example, pen calibration data and passwords, used during boot up, may be used in the EEPROM 452. The contents of the EEPROM 111B may be shadowed into a CMOS memory when the system is active. Communication with the EEPROM 111B is under the control of the system controller 129 and in particular, a pair of programmable input/output pins GPI01 and GPI02. The GPI01 provides a clock signal to the EEPROM 111B while the pin GPI02 is used for data transfer.

As discussed above, the wireless interface device 100 also includes the flash memory 117 (FIG. 25), which is used for storing the BIOS. The system controller 129 allows for direct shadowing of the BIOS by enabling the appropriate address space to read the FLASH/DRAM write mode which allows all reads to come from the flash device with writes to the DRAM 111A memory devices.

A main memory map as well as an I/O memory map are provided in Tables 3 and 4.

TABLE 3

Figure US06209034-20010327-C00001

TABLE 4 I/O MEMORY MAP Memory Space Description Memory Locations (HEX) DMA Controller #1 00-0F Not Used 10-1F Interrupt Controller #1 20-21 Not Used 22-23 Evergreen Configuration Address 24 Not Used 25 Evergreen Configuration Data 26 Not Used 27-3F Counter/Timer 40-43 Not Used 44-5F Keyboard Controller 60 Port B 61 Not Used 62-63 Keyboard Controller 64 Not Used 65-6F NMI Enable, Real-Time Clock 70, 71 Not Used 72-7F DMA Page Registers 80-8F Not Used 90-91 Port A 92 Not Used 93-9F Interrupt Controller #2 A0-A1 Not Used A2-CF DMA Controller #2 D0-DE Not Used DF-2FF Pen Controller 300 Not Used 301-3AF Graphics Controller 3B0-3DF RF Controller 3E0-3E7 UART COM1 3E8-3EF Not Used 3F0-3FF

In addition to system control features and DRAM control, the system controller 129 provides various other functions. The power management function and NVRAM controller have been discussed above. The system controller 129 also controls all operations on the local AT bus 150. The AT bus clock is derived from the clock CLK2IN pin that is divided to achieve an 8 MHz bus rate.

The system controller 129 also includes a number of programmable pins which enhance its flexibility. For example, four general purpose input/output pins GPIO[0..3] are provided; each of which may be independently set for input or output. The GPIO1 and GPIO2 pins are used for the EEPROM 111B as discussed above. The GPIO0 pin and GPIO3 pin may be used for various purposes. In addition to the programmable input/output pins, the system controller 129 includes two general purpose chip select pins GPCS1 and GPCS2 as well as a plurality of programmable output pins PC[0..9]. The programmable chip selects GPCS1 and GPCS2 are used for the pen controller 110A, UART 134 and the radio interface 114B.

Peripheral devices connected to the system ISA bus 151 are controlled by an integrated peripheral controller 128 as discussed above. The integrated peripheral controller 128 may be a PicoPower Model No. PT82C206F which can be operated at either 3.3 or 5 volts. As will be discussed in more detail below, the integrated peripheral controller 128 includes several subsystems such as: DMA Control; Interrupt Control; Timer Counter; RTC Controller; CMOS RAM and Memory Mapper.

The IPC 128 includes two type 8259A compatible interrupt controllers which provide 16 channels of interrupt levels, one of which is used for cascading. The interrupt controller processes all incoming interrupts in order as set forth in Table 5.

TABLE 5 INTERRUPT TABLE INTERRUPT DESCRIPTION Level 0 Timer Channel 0 Level 1 Keyboard Controller 2 Cascade Level 2 Second Interrupt Controller Level 3 Not Used Level 4 COM1 Level 5 Pen Controller Level 6 Not Used Level 7 Not Used Level 8 RTC Controller Level 9 Not Used Level 10 Radio Controller Level 11 Not Used Level 12 Not Used Level 13 Not Used Level 14 Not Used Level 15 Not Used

The integrated peripheral controller (IPC) 128 (FIG. 14) is connected to the system data bus SD[0..15]. Addressing of the IPC 128 is accomplished by two bits SA0 and SA1 from the system address bus SA[0..23] and eight bits A[2..9] from the local address bus A[0..31]. The address bits from the local address bus A[2..8] are converted to 5 volts by way of a 3- to 5-volt signal converter 453 (FIG. 14) to develop the 5-volt address signals XA[2..8]. A 32-kilohertz clock signal 32-KHz from the clock generator 398 (FIG. 13) is applied to the clock input OSC1 of the IPC 128.

Referring to FIG. 20, in order to prevent spurious operation of the IPC 128 before the system power supply is stabilized, a power good signal PWRGOOD is applied to a power good pin PWRGD. The power good signal PWRGOOD is a delayed signal which assures that the 5-volt power supply has stabilized before the IPC 128 is activated. In particular, a 5-volt power supply 5V_CORE is applied to a delay circuit which includes a resistor 454, a diode 456 and a capacitor 458. Initially, the 5-volt power supply signal 5V_CORE is dropped across the resistor 454. While the capacitor 458 is charging, the diode 456 is in a non-conducting state. As the capacitor 458 begins to charge, the voltage at the anode of the diode 456 increases as a function of the RC time constant. When the capacitor 458 is fully charged, it approaches the value of the power supply voltage 5V_CORE. When the capacitor 458 becomes fully charged, the power good signal PWRGOOD is applied to a power good pin PWRGD at the IPC 128 for enabling the IPC 128 after the power supply has stabilized. The diode 456 provides a discharge path for the capacitor 458 when the power supply is shut off. The power good signal PWRGOOD is also used to reset the keyboard controller 125.

A 5-volt power supply 5V_CORE from the DC-to-DC converter 300 (FIG. 26) is applied to a ferrite bead inductor 460 (FIG. 13) to develop a 5-volt power supply 5V_206, which, in turn, is applied to the power supply pins VCC of the IPC 128. In order to delay application of the 5-volt power supply 5V_206 as discussed below, a charging circuit which includes a serially coupled resistor 462 and a capacitor 464 are connected between the power supply voltage 5V_206 and the system ground. A power supply reset signal PSRSTB, an active low signal, is applied to the junction between the resistor 462 and the capacitor 464 to discharge the capacitor 464 when the power supply is reset. Moreover, in order to stabilize the voltage of the power supply 5V_206, a plurality of bypass capacitors 466 and 468 are connected between the power supply 5V_206 and system ground.

In order to assure proper operation of the circuit, various pins of the IPC 128 are pulled low while various other pins are pulled high. In particular, the input/output read and write signals IOR and IOW are pulled up to the power supply voltage 5V_206 by a pair of pull-up resistors 470 and 472. In addition, the interrupt request pin IRQ10 is pulled up to the power supply voltage 5V_CORE by a pull-up resistor 474. The signals OUT2, REFREQ, AEN16 and AEN8 are pulled low by pull-down resistors 455-461 while the signal TEST_MODE2 is pulled up to the supply voltage 5V_CORE by a pull-up resistor 463.

Even though the IPC 128 includes a direct memory access (DMA) controller, this function is not required by the system. As such, the direct memory access request pins DREQ[0..7] are pulled low by a pull-down resistor 476 to system ground. In addition, as set forth in Table 5 above, various interrupt levels are unused. For example, as shown in Table 5, interrupt levels IRQ3, IRQ6, IRQ7, IRQ9, IRQ11, IRQ12, IRQ14, and IRQ15 are not used. Thus, these interrupt levels are pulled low by a pull-down resistor 478.

As illustrated in Table 5, interrupt levels IRQ4 and IRQ5 are used for the COM1 and pen controller interrupt levels, IRQ4 and IRQ5. To assure that these levels are proper, the IRQ4 and IRQ5, which are active high, are pulled low by pull-down resistors 480 and 482.

Interrupts by the system controller 129 and IPC 128 INTR_EG and INTR206 are applied to the CPU 112 by way of a diode 479 and pull-up resistor 481 (FIG. 14). In particular, the interrupt signals INTR_EG and INTR206 from the system controller 129 and IPC 128, respectively, are applied to the cathode of the diode 479 while the anode is pulled up to the power supply voltage 3V_CORE by the pull-up resistor 481. The logic level of the anode is set by the interrupt signal INTR, which is applied to the CPU 112. When the interrupt signals INTR206 and INTR_EG are high, the diode 479 does not conduct and the CPU 112 interrupt signal INTR will be high. When either of the interrupt signals INTR_EG or INTR206 are low, the diode 479 conducts, forcing the CPU 112 interrupt signal INTR low.

The IPC 128 also includes a type 8254 compatible counter/timer which, in turn, contains three 16-bit counters that can be programmed to count in either binary or binary-coded decimal. The zero counter output is tied internally to the highest interrupt request level IRQ0 so that the CPU 112 is interrupted at regular intervals. The outputs of the timers 1 and 2 are available for external connection. In particular, internal timer 1 generates one signal, OUT1, which is used to generate a DRAM refresh request signal REFREQ to the CPU 112. The internal timer 2 generates an output signal OUT2 that is used to generate speaker timing. All three internal timers are clocked from a timer clock input TMRCLK at 1.2 megahertz from the system controller 129.

As mentioned above, the IPC 128 includes a real time clock (RTC) controller which maintains the real time. The real operational time is maintained in a CMOS RAM that can be accessed through registers 70H and 71H. The memory map for the CMOS memory is provided in Table 6 as shown below:

TABLE 6 CMOS MEMORY MAP INDEX FUNCTION 00H Seconds 01H Seconds Alarm 02H Minutes 03H Minutes Alarm 04H Hours 05H Hours Alarm 06H Day of Week 07H Day of Month 08H Month 09H Year 0AH Registry 0BH Register B 0CH Register C 0DH Register D {overscore (0E)}H-7EH User RAM

The area designated as User RAM is used by the system BIOS to save the status of the system configuration registers. The alarm bytes may be used to set and generate an interrupt at a specific time. When periodic interrupt is required, the two most significant bits in the alarm register can be set high.

The various clock signals used for the system are provided by the clock generator circuit 398 (FIG. 13). The clock circuit 398 includes a clock generator, for example, an Integrated Circuit Designs Model No. ICD2028. A 14.318 MHz crystal 484 and a 32.768 KHz crystal 486 are applied to the clock generator 488. In particular, the crystal 484 is applied to a pair of X1 and X2 input pins along with a plurality of capacitors 489, 490, 492 and an input resistor 494. Similarly, the crystal 486 is applied to input pins XSYSB1 and XSYSB2. A pair of capacitors 496 and 498 are connected across the crystal 486.

The clock generator IC 488 provides three clock outputs CLKA, CLKB and CLKD. The clock A output CLKA is used to develop an 8-MHz clock signal for the keyboard controller 125 by way of a resistor 500 and capacitors 502 and 504. The clock B output CLKB is used to develop a clock 2X output signal CLK2IN for the system controller 129 by way the resistors 506, 508 and 510 and a pair of capacitors 512 and 514. The clock D output signal CLKD is used to generate a 1.84 MHz signal for use by the Universal Asynchronous Receiver Transmitter (UART) 134 by way of a resistor 516 and capacitors 518 and 520. As mentioned above, the system controller 129 also requires a 14 MHz clock signal. This clock signal is developed by way of a system bus output pin SYSBUS, a resistor 522 and a pair of capacitors 524 and 526.

Selection of the various clock output signals is available by way of the select pins S0, S1 and S2. These pins S0, S1 and S2 are pulled up to the 3-volt power supply 3V_CORE by way of pull-up resistors 521, 523 and 525. The 3-volt power supply signal 3V_CORE is available from the DC-DC converter 300 (FIG. 26).

The clock generator 488 utilizes a 3-volt power supply CLOCK_VCC (FIG. 13). The 3-volt power supply CLOCK_VCC is available from the DC-to-DC converter 300 (FIG. 26) by way of an in-line ferrite bead inductor 530. In particular, the 3-volt power supply 3V_CORE is applied to the ferrite bead inductor 530 to generate the power supply for the CLOCK_VCC for the clock generator 488. This power supply CLOCK_VCC is applied to the power supply pin VDD. The power supply signal CLOCK_VCC is also used as analog supply AVDD to the clock generator IC 488 and is applied to the analog supply AVDD by way of the resistor 532 and a pair of capacitors 534 and 536. The power supply signal CLOCK_VCC is also applied to the battery pin VBATT of the clock generator IC 488 by way of a diode 537 to prevent any back feeding.

A number of the circuits in the system operate at either 3.3 volts or 5 volts. Thus, a plurality of bi-directional signal level translators 542 and 544 (FIG. 14) are provided, as well as the translator 453 previously discussed. The signal level translators 453, 542 and 544 may be as supplied by Integrated Circuit Technology, Model No. FCT164245T. Each of the signal level translators 453, 542 and 544 includes a 3-volt supply 3V_CORE and a 5-volt supply 5V_CORE, available from the DC-to-DC converter 300 (FIG. 26). In order to stabilize the voltage of the 3- and 5-volt power supplies, 3V_CORE and 5V_CORE, a plurality of bypass capacitors are utilized. In particular, the bypass capacitors 546 through 552 are connected between the 3-volt supply 3V_CORE and system ground. Similarly, the bypass capacitors 554 through 560 are connected between the 5-volt supply 5V_CORE and system ground. The ground terminals of each of the signal level translators 542, 544 and 453 are also tied to system ground.

Each of the signal level translators 542, 544 and 453 includes two 8-bit programmable input/output pins. More particularly, the first 8-bit group 1A/1B[1..8] is under the control of an operate/enable pin 1{overscore (OE)}, which is active low, while the second bank 2A/2B[1..8] is under the control of an output/enable pin 2{overscore (OE)}, also active low. The direction of the input pins and output pins (i.e., A relative to B) is under the control of direction pins 1DIR and 2DIR. The direction pin 1DIR controls the direction of the pins 1A/1B[1..8], while the pin 2DIR controls the direction of the pins 2A/2B[1..8].

The signal level translator 453 is used to convert the local data bus bits D[16..31] and the system data bus bits SD[0..15]. Both the local data bus D[16..31] as well as the system data bus SD[0..15] are bi-directional. In this application the processor bus 150 data bits D[31...16] are being mapped to the system data bus bits SD[15...0].

The direction of the signal level translator 542 is under the control of a signal direction signal SDIR, available at the system controller 129. The signal direction signal SDIR is applied to both the direction control pins 1DIR and 2DIR of the signal level translator 542. The operate/enable inputs 1{overscore (OE)} and 2{overscore (OE)} are under the control of system data enable inputs signals, SDEN3 and SDEN2, respectively; also under the control of the system controller 129.

The signal level translator 544 is used to map the signal levels of the local address bus bits A[23...8] to the system address bus bits SA[23...8]. More particularly, the local address bits A[23..16] are applied to pins 1A[1..8] while the local address bits A[15..8] are applied to the pins 2A[1..8]. Similarly, the system address bits SA[23..16] are connected to the pins 1B[1..], while the system address bits SA[15..8] are applied to the pins 2B[1..8]. In this case, the operate/enable pins 1{overscore (OE)} and 2{overscore (OE)}, both active low, are connected to system ground in order to permanently enable the signal level translator 544. The direction control pins 1DIR and 2DIR are permanently set such that the data always flows from A to B. In particular, the directional pins 1DIR and 2DIR are connected to the 3-volt power supply 3V_CORE by way of a pull-up resistor 562.

The signal level translator 542 is used to convert the signal levels of the 3-volt clock output signals 14 Mhz, 1.85 Mhz, 32 Khz and 8 Mhz to 5-volt levels, as well as to convert the 3-volt local address bits A[2..8] to 5-volt address bits XA[2..8] for use by the IPC 128, as discussed above. More particularly, the system address bits, A[2..8] are applied to the pins 1A[1..8]. The clock signals 14 MHz, 1.85 MHz, 32 KHz and 8 MHz are applied to the pins 2A1, 2A3, 2A6 and 2A8, respectively, to produce corresponding 5-volt level signals 14 MHz5V, 1.84 MHz5V, 32 KHz5V and 8 MHz5V signals at pins 2B1, 2B3, 2B6 and 2B8, respectively. The unused pins 1A8 and 2B8 are pulled low by way of pull-down resistors 564 and 565, respectively. The operate/enable pins 1{overscore (OE)} and 2{overscore (OE)} are tied to system ground to permanently enable the signal level translator 542. The directional pins 1DIR and 2DIR are pulled up to the 3-volt power supply voltage 3V_CORE by way of a pull-up resistor 566 to permanently force the direction from A to B.

Referring to FIG. 15, the system includes a keyboard controller 125, which performs several functions, including battery monitoring, LCD status control, brightness and contrast control, as well as keyboard control. In addition, the system also maintains the status of the remaining battery life, and also provides information to the system controller 129 when the battery voltage is low or other critical battery condition has occurred. In operation, the keyboard controller 125 will maintain the current status of the battery level until data is requested. When a critical battery condition event occurs, the keyboard controller 125 generates an SMI interrupt. As discussed above, the intelligent battery pack (IBP) 130 provides an indication of the percentage of remaining battery capacity. Communication between the IBP 130 and the keyboard controller 125 is by way of a bi-directional serial data bus, which includes a clock line BATCLK and a data line BATDATA. The data line BATDATA is a bi-directional line, which allows for bi-directional communication with the IBP 130. The clock line BATCLK is driven by the IBP 130, but may be pulled low by the keyboard controller 125.

The bi-directional serial data bus is connected to the port pins P4.2 and P4.3 on the keyboard controller 125. In particular, the port pin P4.2 is used for the serial battery data BATTDATA. An NPN transistor 570 is connected to the port pin P4.2 to disconnect the keyboard controller 125 from the IBP 130 during power down. In particular, the collector terminal of the NPN transistor 570 is connected to the port pin P4.2, while the emitter terminal forms a battery data signal BATTDATA. The base of the NPN transistor 570 is biased on by way of a biasing resistor 572 that is connected to a 5-volt power supply 5V_KBD. The collector is pulled high by way of a pull-up resistor 574 connected to the 5-volt power supply 5V_KBD.

Similarly, the battery clock signal BATTCLK is connected to the port 4.3 on the keyboard controller 125 by way of an NPN transistor 576. The collector terminal of the NPN transistor 576 is connected to the port 4.3 as well as to a pull-up resistor 578 and the 5-volt power supply 5V_KBD. The NPN transistor 576 is turned on anytime the power supply to the keyboard 5V_KBD is powered up by way of a biasing resistor 580. The emitter of the NPN transistor 576 forms the battery clock signal BATTCLK.

In addition to battery management, the keyboard controller 125 also supports an external PS/2-type keyboard, as well as a PS/2-type bar code reader, connected to a keyboard connector 140 (FIG. 29). Communication between the keyboard or bar code reader (not shown) is by way of a standard type PS-2 two-wire bus connected to serial ports P4.6 and P4.7. In particular, the keyboard data KDATA is pulled up to the 5-volt voltage supply 5V_CORE by way of a pull-up resistor 582 while the keyboard clock signal KCLK is pulled up the 5-volt supply 5V_CORE by way of a pull-up resistor 584.

Referring to FIG. 29, the keyboard connector 140 may be a 6-pin MINI-DIN connector or a DB-8 connector as shown. Pins 6-9 are connected to system ground. Pin 4 of the connector 140 is pulled up to the power supply voltage 5V_CORE by way of a fuse 579 and is filtered by a capacitor 581 and an inductor 583. The data signal KDATA is applied to pin 1 by way of a current-limiting resistor 585, while the clock signal KCLK is applied to pin 5 by way of a current-limiting resistor 587 and a pair of capacitors 589 and 591. These clock and data signals KCLK and KDATA are connected to the ports P4.6 and P4.7, respectively, for serial communication with an external keyboard or bar code reader.

Additionally, the keyboard controller 125 may be used to control the brightness level as well as the contrast level of the LCD display. More particularly, referring to FIG. 27, a contrast signal CONTRAST, available at port 0, pin 1 of the keyboard controller 125 (FIG. 15) is used to adjust the contrast level of the LCD display. The contrast signal CONTRAST is applied to an adjustment terminal ADJ of a negative 24-volt DC voltage supply, which can be incrementally adjusted in steps by a 24-volt DC supply 586 (FIG. 27), for example, a Maxim Model No. 749, which provides for 64-step adjustment. Thus, each high pulse will increment the contrast of the LCD display by one step. With a 64-step device, sixty-three pulses rolls the counter over and decreases the contrast by 1. The 24-volt DC supply 586 is under the control of an enable signal ENAVEE, available from the video controller 113A (FIG. 19).

In order to assure proper operation, the 24-volt supply 586 is connected in a circuit as shown in FIG. 27, which includes a plurality of capacitors 588, 590, 592, 594; a plurality of resistors 596, 598, 600 an inductor 602; a PNP transistor 604; and a zener diode 606. The output of the circuitry is a nominal negative 24-volt signal LCDVEE, which is adjustable in 64 increments by way of the CONTRAST signal, as discussed above, to vary the contrast level of the LCD display.

The keyboard controller 125 also controls the brightness of the LCD display. In particular, brightness adjustment signals BRIGHTNESS_UP, BRIGHTNESS_DOWN (FIG. 15) are available at port 1, pins 6 and 7. These signals BRIGHTNESS_UP and BRIGHTNESS_DOWN are normally pulled up to the 5-volt supply 5V_KBD by way of a pair of pull-up resistors 608 and 610. These signals BRIGHTNESS_UP and BRIGHTNESS_DOWN are applied to a digital output potentiometer 612 (FIG. 27), for example a Dallas Semiconductor Model No. DS1669-5O. The digital output potentiometer 612 is powered by a 5-volt power supply 5V_CORE, which is also used to pull up an unused output terminal, RH.

The brightness control signals BRIGHTNESS_UP and BRIGHTNESS_DOWN are applied to the increment and decrement terminals, UC and DC of the digital output potentiometer 612. The output of the digital output potentiometer 612 is a variable resistance signal, which forms the brightness control signal BRIGHTNESS. This brightness control signal BRIGHTNESS is pulled down by a pull-down resistor 614.

The brightness control signal BRIGHTNESS from the digital output potentiometer 612, as well as a backlight control signal BACKLITEON and a backlight power signal BACKLITEPOWER are connected to the system by way of a 6-pin connector 615 (FIG. 27). The