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US6101115A - CAM match line precharge - Google Patents

CAM match line precharge Download PDF

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US6101115A
US6101115A US09130747 US13074798A US6101115A US 6101115 A US6101115 A US 6101115A US 09130747 US09130747 US 09130747 US 13074798 A US13074798 A US 13074798A US 6101115 A US6101115 A US 6101115A
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match
voltage
precharge
memory
line
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US09130747
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Mark Ross
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Cisco Technology Inc
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Cisco Technology Inc
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C15/00Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
    • G11C15/04Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements

Abstract

The invention provides a method and system for improved CAM match line precharge, in which the amount of power consumed by match line precharge and discharge is significantly reduced. An independent match precharge voltage is introduced to the CAM, which is used to separately precharge the match line and is available for use by comparison circuits to attempt to match the input tag. The match precharge voltage is selected so as to reduce the relative power consumption for match line precharge and discharge by a factor of about five. Optionally, sense amplifiers in the comparison circuits are disposed so as to compare each discharged match line with the match precharge voltage itself.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates to CAM match line precharge.

2. Related Art

A CAM (content addressable memory) is sometimes used in a computer system or device for storing and retrieving information. CAMs have the advantage that they can rapidly link associated data with known tags; it is thus possible to perform rapid lookup of the associated data once the tag is known. Known CAMs include comparison circuits for matching an input tag with each tag recorded in the CAM, so as to determine which if any of the row or lines in the CAM matches the tag.

In some known CAMs each row or line includes a set of memory cells, each of which includes a recorded match bit for comparison with the input tag. The comparison circuits operate by precharging a match line and coupling that match line to circuits for all the recorded match bits. If any recorded match bit is not the same as the input tag, the match line is discharged. Thus, most match lines are discharged, even though the CAM does not deliver the data associated with the unmatched tag.

One problem in the known art is that power consumption from precharging and discharging the match line is relatively high. This problem is exacerbated when the CAM is relatively large, that is, when the number of bits to be matched in the tag is relatively large. In addition to the amount of power consumed by precharge and discharge of the match line, the process of precharging and discharging the match line can be time consuming relative to the total time for the CAM to respond to the input tag. It would be advantageous to reduce both the relative amount of power consumption and the relative time required for operation of the CAM.

Accordingly, it would be desirable to provide a method and system for improved CAM match line precharge. This advantage is achieved in an embodiment of the invention in which the amount of power consumed by match line precharge and discharge is significantly reduced by use of a relatively lower discharge voltage. This has two further advantages: (1) discharging from a lower voltage is relatively faster, and (2) use of the lower voltage as an input to the sense amplifier speeds up comparisons.

SUMMARY OF THE INVENTION

The invention provides a method and system for improved CAM match line precharge, in which the amount of power consumed by match line precharge and discharge is significantly reduced. An independent match precharge voltage is introduced to the CAM, which is used to separately precharge the match line and is available for use by comparison circuits to attempt to match the input tag. In a preferred embodiment, the match precharge voltage is selected so as to reduce the relative power consumption for match line precharge and discharge by a factor of about five.

In a preferred embodiment, sense amplifiers in the comparison circuits are disposed so as to compare each discharged match line with the match precharge voltage itself, or to take advantage of the lower signal swing to speed up single-ended sensing schemes.

BRIEF DESCRIPTION OF THE DRAWINGS

The figure shows a block diagram of an improved system for CAM match line precharge.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the following description, a preferred embodiment of the invention is described with regard to preferred process steps and data structure would recognize after perusal of this application that embodiments of the invention can be implemented using circuits adapted to particular process steps and data structures described herein, and that implementation of the process herein would not require undue experimentation or further invention.

System Elements

The figure shows a block diagram of an improved system for CAM match line precharge.

Operation of CAM

A CAM 100 includes an input port 101, a plurality of CAM lines 102, and an output port 103. Each one CAM line 102 is disposed to match an input value from the input port 101 to a tag value recorded at the CAM line 102, and to output a logical match bit indicating whether the input value is equal to the tag value. An accumulator (not shown) collects the logical match bits and selects at least one stored value associated with the one tag value that matches the input value. In an ordinary binary CAM, there will be one such matched stored value, while in a ternary CAM, there can be multiple such matched stored values.

Each CAM line 102 includes a plurality of CAM cells 120, one for each bit of the tag value. Each CAM cell is coupled to a bit line 130 BL (and an inverted bit line 121 BL-bar), and to a match line 140 MATCH. In alternative embodiments, the CAM cells 120 may be coupled to independent compare lines.

Each CAM cell 110 includes a set of four transistors Q1, Q2, Q3, Q4 respectively shown in FIG. 1 as 111, 112, 113, 114, that collectively form, for all CAM cells 110 in a CAM line 102, a wired-XNOR circuit 150. The wired-XNOR circuit 150 thus has a plurality of inputs (one for each CAM cell 110), and a single output (not shown). Each input is responsive to whether the single CAM cell 110 matches the input value for the CAM 110 to the tag value for that CAM line 102.

Although a preferred embodiment uses a four-transistor wired-XNOR circuit 150, those skilled in the art will recognize, after perusal of this application, that many other alternatives are possible that can achieve the same or a similar result, and that such alternatives would not require further invention or undue experimentation. Such alternatives are within the scope and spirit of the invention.

In a preferred embodiment, the wired-XNOR circuit 150 is coupled to the match line 140 MATCH. The match line 140 MATCH is precharged with a match line voltage, and the bit line 130 BL (and the inverted bit line 121 BL-bar) are enabled for those bits of the input value that are logical "1." The wired-XNOR circuit 150 discharges the match line 140 MATCH at each CAM cell 110 for those bits of the input value that do not match the corresponding bit of the tag value at that CAM cell 110. If any bit of the wired-XNOR circuit 150 discharges the match line 140 MATCH, the match line 140 MATCH discharges and presents a logical "0" for the output of the wired-XNOR circuit 150.

Thus, the amount of power consumed by precharging and discharging the match lines 140 MATCH is given by equation 201:

P=nCv.sup.2 f                                              (201)

where

P=power consumed,

n=number of match lines,

C=capacitance of each match line,

v=voltage swing for each match line, and

f=frequency of CAM operations.

A sense amplifier 160 is coupled to each match line 140 MATCH, and is disposed for comparing a voltage for the match line 140 MATCH with a threshold voltage. An input value that is nearly equal to the tag value for will cause the match line 140 MATCH to discharge nearly, but not entirely. The sense amplifier 160 is sensitive to slight changes in the voltage on the match line 140 MATCH.

Match Precharge Voltage

An independent match line precharge voltage (IMPV) 202 is coupled to each match line 140 MATCH to precharge the match line 140 MATCH. In a preferred embodiment, the IMPV 202 is supplied to the CAM 100 from an external source.

As shown above in equation 201, the power consumption of the CAM 100 is proportional to (IMPV)2. In a first preferred embodiment, the expected operating voltage of the CAM 100 is about 2.5 volts, and the (IMPV) 202 is selected to be substantially less, such as about 1.8 volts. In a second preferred embodiment, the expected operating voltage of the CAM 100 is about 1.8 volts, and the (IMPV) 202 is selected to be substantially less, such as about 1.0 volts. In either case, power consumption is substantially less than if the operating voltage of the CAM 100 were used instead of the (IMPV) 202.

Those skilled in the art will recognize, after perusal of this application, that power consumption using the (IMPV) 202 is about 20% to about 50% of when using the operating voltage as the match precharge voltage.

The (IMPV) 202 may be coupled to each sense amplifier 160 for use as the selected threshold voltage. This promotes recognition of relatively small voltage changes in each match line 140 MATCH. In a preferred embodiment, the (IMPV) 202 is selected so as to provide a sufficient noise margin at the sense amplifier 160, so that the noise margin is above the switching point of a single-ended sense amplifier 160.

Application to CAM Design

Those skilled in the art will recognize, after perusal of this application, that the invention is well suited for use in different types of CAM, including both binary CAMs and ternary CAMs.

In a ternary CAM, each CAM cell 110 includes both a tag value and a mask value. The mask value determine whether the input value for the CAM 100 includes bits for which matching is not attempted, that is, for which the CAM cell 110 is considered to match the input value regardless of the actual corresponding tag value bit.

In a CAM, it is expected that a majority of the CAM cells 110 will not match regardless of the actual corresponding tag value bit. Accordingly, it would be advantageous to reduce power consumption in a ternary CAM.

Alternative Embodiments

Although preferred embodiments are disclosed herein, many variations are possible which remain within the concept, scope, and spirit of the invention, and these variations would become clear to those skilled in the art after perusal of this application.

Claims (39)

I claim:
1. An independent match-line precharge voltage within a content addressable memory, including
an input port disposed for receiving a selected match precharge voltage substantially independent of an operating voltage of said memory;
wherein said selected match precharge voltage provide for relatively lower power consumption of said memory when said selected match precharge voltage is substantially less than said operating voltage.
2. A memory as in claim 1, wherein said memory includes a mask value for at least some lines of said memory.
3. A memory as in claim 1, wherein said memory includes a ternary content addressable memory.
4. A memory as in claim 1, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage greater than about 2.00 volts.
5. A memory as in claim 1, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage substantially equal to said operating voltage.
6. A memory as in claim 1, wherein said selected match precharge voltage is about 1.8 volts.
7. A memory as in claim 1, wherein said selected match precharge voltage is about 1.0 volt.
8. A memory as in claim 1, wherein said selected match precharge voltage is less than about 2.0 volts.
9. A memory as in claim 1, including a sense amplifier; wherein said selected precharge voltage provides a noise margin substantially above a switching point for said sense amplifier.
10. An independent match line precharge voltage within a content addressable memory, including
an input port disposed for receiving a selected match precharge voltage substantially independent of an operating voltage of said memory;
a set of sense amplifiers each coupled to at least one match line of said memory, each said sense amplifier being responsive to said selected match precharge voltage.
11. A memory as in claim 10, wherein said memory includes a mask value for at least some lines of said memory.
12. A memory as in claim 10, wherein said memory includes a ternary content addressable memory.
13. A memory as in claim 10, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage greater 2.0 volts.
14. A memory as in claim 10, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage substantially equal to said operating voltage.
15. A memory as in claim 10, wherein said selected match precharge voltage is about 1.8 volts.
16. A memory as in claim 10, wherein said selected match precharge voltage is about 1.0 volt.
17. A memory as in claim 10, wherein said selected match precharge voltage is less than about 2.0 volts.
18. A memory as in claim 10, including a sense amplifier; wherein said selected precharge voltage provides a noise margin substantially above a switching point for said sense amplifier.
19. An independent match-line precharge voltage within a content addressable memory, including
an input port disposed for receiving a selected match precharge voltage substantially independent of an operating voltage of said memory;
a set of sense amplifiers each coupled to at least one match line of said memory, each said sense amplifier being responsive to said selected match precharge voltage;
wherein said selected match precharge voltage provides for relatively lower power consumption of said memory when said selected match precharge voltage is substantially less than said operating voltage.
20. A memory as in claim 19, wherein said memory includes a mask value for at least some lines of said memory.
21. A memory as in claim 19, wherein said memory includes a ternary content addressable memory.
22. A memory as in claim 19, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage greater than about 2.0 volts.
23. A memory as in claim 19, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage substantially equal to said operating voltage.
24. A memory as in claim 19, wherein said selected match precharge voltage is about 1.8 volts.
25. A memory as in claim 19, wherein said selected match precharge voltage is about 1.0 volt.
26. A memory as in claim 19, wherein said selected match precharge voltage is less than about 2.0 volts.
27. A memory as in claim 19, wherein said selected precharge voltage provides a noise margin substantially above a switching point for said set of sense amplifiers.
28. A method of operating a content addressable memory, said method including steps for
receiving a selected match precharge voltage substantially independent of an operating voltage of said memory; and
consuming relatively lower power during operating of said memory responsive to said selected match precharge voltage, when said selected match precharge voltage is substantially less than said operating voltage.
29. A method as in claim 28, including steps for matching, for at least some lines of said memory, an input value for said memory against a mask value.
30. A method as in claim 28, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage greater than about 2.0 volts.
31. A method as in claim 28, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage substantially equal to said operating voltage.
32. A method of operating a content addressable memory, said method including steps for
receiving a selected match precharge voltage substantially independent of an operating voltage of said memory; and
matching at least one match line of said memory responsive to selected match precharge voltage.
33. A method as in claim 32, including steps for matching, for at least some lines of said memory, an input value for said memory against a mask value.
34. A method as in claim 32, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage greater than about 2.0 volts.
35. A method as in claim 32, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage substantially equal to said operating voltage.
36. A method of operating a content addressable memory, said method including steps for
receiving a selected match precharge voltage substantially independent of an operating voltage of said memory; and
matching at least one match line of said memory responsive to selected match precharge voltage;
consuming relatively lower power during operating of said memory responsive to said selected match precharge voltage, when said selected match precharge voltage is substantially less than said operating voltage.
37. A method as in claim 36, including steps for matching, for at least some lines of said memory, an input value for said memory against a mask value.
38. A method as in claim 36, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage greater 2.0 volts.
39. A method as in claim 36, wherein said power consumption is between about 20% to about 50% of that for a match precharge voltage substantially equal to said operating voltage.
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Cited By (23)

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US6879532B1 (en) 2002-04-10 2005-04-12 Integrated Device Technology, Inc. Content addressable and random access memory devices having high-speed sense amplifiers therein with low power consumption requirements
US6965519B1 (en) 2003-06-18 2005-11-15 Integrated Device Technology, Inc. Content addressable memory (CAM) devices that utilize dual-capture match line signal repeaters to achieve desired speed/power tradeoff and methods of operating same
US6967856B1 (en) 2002-04-10 2005-11-22 Integrated Device Technology, Inc. Content addressable memory (CAM) devices that utilize segmented match lines and word lines to support pipelined search and write operations and methods of operating same
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