US5963461A  Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization  Google Patents
Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization Download PDFInfo
 Publication number
 US5963461A US5963461A US08926589 US92658997A US5963461A US 5963461 A US5963461 A US 5963461A US 08926589 US08926589 US 08926589 US 92658997 A US92658997 A US 92658997A US 5963461 A US5963461 A US 5963461A
 Authority
 US
 Grant status
 Grant
 Patent type
 Prior art keywords
 result
 product
 instruction
 significands
 shift
 Prior art date
 Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
 Expired  Lifetime
Links
Images
Classifications

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
 G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using noncontactmaking devices, e.g. tube, solid state device; using unspecified devices
 G06F7/483—Computations with numbers represented by a nonlinear combination of denominational numbers, e.g. rational numbers, logarithmic number system, floatingpoint numbers
 G06F7/487—Multiplying; Dividing
 G06F7/4876—Multiplying

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
 G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using noncontactmaking devices, e.g. tube, solid state device; using unspecified devices

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
 G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using noncontactmaking devices, e.g. tube, solid state device; using unspecified devices
 G06F7/483—Computations with numbers represented by a nonlinear combination of denominational numbers, e.g. rational numbers, logarithmic number system, floatingpoint numbers
 G06F7/485—Adding; Subtracting

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F9/00—Arrangements for programme control, e.g. control unit
 G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
 G06F9/30—Arrangements for executing machineinstructions, e.g. instruction decode
 G06F9/30003—Arrangements for executing specific machine instructions
 G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
 G06F9/3001—Arithmetic instructions
 G06F9/30014—Arithmetic instructions with variable precision

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F9/00—Arrangements for programme control, e.g. control unit
 G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
 G06F9/30—Arrangements for executing machineinstructions, e.g. instruction decode
 G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
 G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling, out of order instruction execution

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F9/00—Arrangements for programme control, e.g. control unit
 G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
 G06F9/30—Arrangements for executing machineinstructions, e.g. instruction decode
 G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
 G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F9/00—Arrangements for programme control, e.g. control unit
 G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
 G06F9/30—Arrangements for executing machineinstructions, e.g. instruction decode
 G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
 G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
 G06F9/3873—Variable length pipelines, e.g. elastic pipeline

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F9/00—Arrangements for programme control, e.g. control unit
 G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
 G06F9/30—Arrangements for executing machineinstructions, e.g. instruction decode
 G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
 G06F9/3867—Concurrent instruction execution, e.g. pipeline, look ahead using instruction pipelines
 G06F9/3875—Pipelining a single stage, e.g. superpipelining

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F9/00—Arrangements for programme control, e.g. control unit
 G06F9/06—Arrangements for programme control, e.g. control unit using stored programme, i.e. using internal store of processing equipment to receive and retain programme
 G06F9/30—Arrangements for executing machineinstructions, e.g. instruction decode
 G06F9/38—Concurrent instruction execution, e.g. pipeline, look ahead
 G06F9/3885—Concurrent instruction execution, e.g. pipeline, look ahead using a plurality of independent parallel functional units

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F2207/38—Indexing scheme relating to groups G06F7/38  G06F7/575
 G06F2207/3804—Details
 G06F2207/3808—Details concerning the type of numbers or the way they are handled
 G06F2207/3812—Devices capable of handling different types of numbers
 G06F2207/382—Reconfigurable for different fixed word lengths

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F2207/38—Indexing scheme relating to groups G06F7/38  G06F7/575
 G06F2207/3804—Details
 G06F2207/386—Special constructional features
 G06F2207/3884—Pipelining

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
 G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using noncontactmaking devices, e.g. tube, solid state device; using unspecified devices
 G06F7/499—Denomination or exception handling, e.g. rounding, overflow
 G06F7/49905—Exception handling
 G06F7/4991—Overflow or underflow

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
 G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using noncontactmaking devices, e.g. tube, solid state device; using unspecified devices
 G06F7/499—Denomination or exception handling, e.g. rounding, overflow
 G06F7/49942—Significance control
 G06F7/49947—Rounding
 G06F7/49957—Implementation of IEEE754 Standard
Abstract
Description
This application is a division of application Ser. No. 08/719,115, filed Sep. 24, 1996, now U.S. Pat. No. 5,844,830 which is a continuation of application Ser. No. PCT/RU96/00210 designating the United States of America, filed Aug. 5, 1996 by V. Y. Gorshtein et al. and entitled "APPARATUS AND METHODS FOR EXECUTION OF COMPUTER INSTRUCTIONS".
The present invention relates to execution of computer instructions.
An important goal in computer design is increasing the computer throughput, that is, the number of computer instructions completed per clock cycle. Another important goal is reducing the instruction execution latency.
In the past, throughput and latency have been improved by parallelism, that is, by making instruction execution units perform different operations in parallel. For example, in some floating point multipliers, generation of the exponent of the result is done in parallel with multiplication of the significands of the operands. It is desirable to further increase parallelism in order to improve throughput and latency.
In the past, multiplication involving denormalized numbers required special processing which was done by software. Software processing reduced multiplier speed. To increase the speed, some multipliers replaced denormalized numbers by zero. This, however, resulted in a loss of precision. Therefore, it is desirable to do full processing of denormalized numbers by hardware to achieve a high speed without a loss of precision.
The invention provides a floating point multiplier with increased parallelism. More particularly, in some embodiments, generation of shift amounts for normalization or denormalization is performed in parallel with multiplication of the significands of the operands. Consequently, the multiplication latency is reduced.
In some floating point multiplier embodiments, parallelism is increased by making the rounding operation overlap with carrypropagate addition that converts the sum of the partial products of the significands from carrysave form to one vector form.
In some embodiments, the floating point multiplier conforms to IEEE Standard 754 and can handle denormalized numbers. Both multiplication by a denormalized number and gradual underflow are implemented by hardware without pipeline disruption. (Gradual underflow means that in case of underflow the multiplier can generate a denormalized result rather than zero.)
In many computers, the same execution unit executes instructions that require different amounts of processing. Because instructions require different amounts of processing, some of the instructions could be executed faster than other instructions. For example, in a floating point multiplier, some instructions do not need a shift for normalization or they need a shift by at most one digit. Such instructions could be executed faster than instructions requiring longer shifts. The slower instructions requiring longer shifts can delay fast instructions and subsequent slower instructions. As a result, throughput is reduced and latency is increased.
The present invention provides in some embodiments instruction execution units that execute variableexecutiontime instructions and have high throughput and low latency.
In some embodiments, the improved throughput and latency are achieved as follows. Instructions executed by the execution unit are divided into two or more categories. Instructions in the same category can be executed in the same amount of time, for example, the same number of clock cycles. Instructions in different categories may require different time for their execution. Thus, some categories are "faster" (i.e., include instructions that can be executed faster) than other categories.
The execution unit includes a separate execution path for each category of instructions. Different paths share circuitry to achieve lower cost and circuit area. Slower execution paths, which execute slower instructions, are pipelined. In some embodiments, all execution paths are pipelined.
Instructions of a fast category are initially executed by a fast execution path. When a slower instruction is encountered, it is executed by a slower path. If the slower instruction is immediately followed by a fast instruction, the fast instruction is also executed by the slower path rather than waiting in the fast path for the slower instruction. Consequently, the fast instruction does not block the circuitry shared by the two paths, and the instruction flow arriving at the execution unit does not have to be suspended. The execution unit throughput is increased as a result, and the latency is reduced.
In some embodiments, the execution unit is a floating point multiplier. The multiplication instructions executed by the multiplier are divided into two categories: "usual" instructions and "unusual" instructions. The usual instruction category includes only instructions for which normalization may require a shift by at most one digit, and denormalization is not required. (Normalization is a left shift eliminating leading nonsignificant digits or a right shift performed to correct the result for overflow. Denormalization is a right shift performed to increase the exponent of the result up to a minimal value.) For example, in some embodiments the usual instructions include instructions in which both operands are normalized and the sum of the operands' exponents, when adjusted for the exponent bias, is greater than the minimal exponent of a normalized number. In some embodiments, the usual instructions include also instructions in which any operand is infinity or zero. The unusual instructions are instructions for which normalization may require a shift by more than one digit or denormalization is required. The unusual instructions take more clock cycles to execute. In some embodiments, an unusual instruction takes four cycles, and a usual instruction takes three cycles; a new instruction can be started every cycle. The two execution paths for the usual and unusual instructions share circuitry that multiplies the operands' significands. The slow path (for the unusual instructions) includes a shifter that can perform normalization/denormalization shifts by more than one digit. The shifter is not part of the fast execution path. The usual instructions immediately following an unusual instruction are executed in the slow execution path (with the shifter performing a shift by zero digits) not to block the shared circuitry and thus to allow a new instruction to start every cycle. When a cycle occurs in which no instruction is started, usual instructions immediately following that cycle are executed by the fast execution path.
In many applications, most instructions are usual instructions. Therefore, in many applications only a small portion of instructions is executed by the slow execution path.
Other features and advantages of the invention are described below. The invention is defined by the appended claims.
FIG. 1 is a block diagram of a floating point multiplier according to the present invention.
FIG. 2 is a table illustrating instruction execution timing in the multiplier of FIG. 1.
FIG. 3 is a circuit diagram of a portion of the multiplier of FIG. 1.
FIG. 4 is a block diagram of a portion of the multiplier of FIG. 1.
FIG. 5 is a table illustrating how signals generated by the circuit of FIG. 4 are related to each other and to the result of the multiplication.
FIG. 6 is a diagram of a portion of the multiplier of FIG. 1.
FIG. 7 is a timing diagram for the signals of the circuit of FIG. 6.
FIGS. 810 are tables of signals in the multiplier of FIG. 1.
FIG. 11 is a block diagram of an adder of the multiplier FIG. 1.
FIG. 12 illustrates input signals and operations in the adder of FIG. 11.
FIG. 13 is a table of signals in the adder of FIG. 11.
FIG. 1 is a block diagram of pipelined floatingpoint multiplier 110 which includes two execution paths. The fast execution path executes instructions for which normalization requires a shift by at most one digit and no denormalization is required. The slow execution path executes the remaining instructions. The circuitry shared by the two paths includes: 1) a circuit which multiplies the operands' significands and which includes Booth circuit 142, Wallace tree adder 122, and significand adder 134; 2) result multiplexer 146 which selects the result from the fast or slow execution path and which performs a onedigit normalization shift when needed; 3) result multiplexer control circuit 710; 4) exponent adder and shift control ("EASC") circuit 126 which generates the result exponents and also generates the shift direction and shift amount for normalization/denormalization shifter 150; and 5) operand analyzer 414. The slow execution path includes also: 1) significand shifter 150 which can perform normalization or denormalization shifts by more than one digit; and 2) rounding adder 154.
Both execution paths are pipelined. The registers defining the pipeline stages include: 1) input register 114 which includes registers 114.1 through 114.6; 2) registers 118, including registers 118.1, 118.2 at the outputs of adder 122 and EASC 126, respectively; 3) registers 130, including registers 130.1, 130.2 at the outputs of significand adder 134 and register 118.2 respectively; and 4) result register 138. These registers are clocked by the same clock CLK.
The first pipeline stage includes circuitry between register 114 and registers 118. In this stage, Booth circuit 142 receives the significands of operands OP1, OP2 from input registers 114.2, 114.3 and generates partial products of the significands. In the same stage, Wallace carrysave adder 122 adds the partial products and generates carrysave vectors SP, CP.
In the second pipeline stage, significand adder 134 connected to the output of register 118.1 adds the two carrysave vectors and provides their sum FAD to result multiplexer 146 and to pipeline register 130.1.
Result multiplexer 146 selects the output of fraction adder 134 only when result normalization requires a shift by at most one digit and denormalization is not required. Result multiplexer 146 performs such a onedigit normalization shift if needed, and provides the result to result register 138. Rounding is performed by adder 134 taking this shift into account. Thus, only two pipeline stages are used to generate the result, and the result is provided on the output Rs in the third clock cycle after the operands appear on the inputs of register 114 (the first clock cycle being the cycle in which adder 122 perform the addition). The third pipeline stage used for longer normalization shifts and for denormalization shifts is omitted.
In the third pipeline stage, significand shifter 150 shifts the output of adder 134 to perform normalization or denormalization. Rounding adder 154 rounds the output of shifter 150 and provides the rounded result RAD to result multiplexer 146. If result multiplexer 146 selects the output RAD of adder 154, the result Rs is provided in the fourth clock cycle.
In some embodiments, some instructions with at most 1digit normalization shifts are placed in the slow category to simplify the circuitry that determines whether the instruction is to be executed in 3 or 4 cycles. This circuitry is part of EASC 126 and is described below.
Fast instructions immediately following a slow instruction are executed in four cycles not to block the pipeline. More particularly, if a fast instruction immediately follows a slow instruction, significand adder 134 provides the significand product FAD for the fast instruction at the same time as rounding adder 154 provides the significand product RAD for the slow instruction. Result multiplexer 146 selects the output RAD of rounding adder 154. To free the significand adder 134 for the next instruction, the output FAD of adder 134 is latched by register 130.1 and goes through the third pipeline stage. Thus, all the instructions immediately following a slow instruction are executed in four cycles. As a result, multiplier 110 is able to start a new instruction every clock cycle. For fourcycle instructions, an instruction termination signal (not shown) is delivered to the processor control circuitry (not shown) one cycle later than for threecycle instructions.
When a clock cycle occurs in which no multiplication instruction is started, subsequent fast instructions are executed again in three cycles until a slow instruction occurs.
In some embodiments, the fast category includes all the instructions for which 1) both operands OP1, OP2 are normalized and 2) the sum of the operands' exponents is greater than the minimum exponent. (In the previous sentence, the sum of the exponents means the sum adjusted for the exponent bias if a biased exponent format is used.) Such instructions need a 1digit normalization shift or no shift at all. In many applications, most multiplication instructions are such instructions. Hence, most multiplication instructions can be performed in three clock cycles, and only a small portion of multiplication instructions is performed in four cycles.
An example timing for one such embodiment is given in FIG. 2. In FIG. 2, fast instructions are called "usual", and slow instructions are called "unusual". In clock cycle 1, adder 122 performs a carrysave addition for a usual instruction. In cycle 2, significand adder 134 performs addition and rounding for the same instruction. In cycle 3, the result of the instruction will be provided on output Rs (this is not shown in FIG. 2). In cycle 2, another usual instruction goes through the carrysave addition stage. This instruction will be completed in 3 cycles like the previous instruction.
In cycle 3, an unusual instruction goes through the carrysave addition stage. For that instruction, significand adder 134 performs the addition in cycle 4, and shifter 150 and rounding adder 154 perform, respectively, shifting and rounding in cycle 5. The result will be provided on output Rs in cycle 6.
In cycle 4, another usual instruction is in the carrysave addition stage. This instruction will take four cycles because it immediately follows an unusual instruction.
No instruction is in the carrysave addition stage in cycle 5. Therefore, a usual instruction which is in the carrysave addition stage in cycle 6 will be completed in 3 cycles.
The throughput increase and the latency reduction are illustrated by the following Tables 1 and 2. Table 1 shows the instruction timing for the multiplier 110 of FIG. 1. Table 2 shows the instruction timing for a similar multiplier in which a usual instruction immediately following an unusual instruction does not go through the third stage but waits until the unusual instruction is completed. In Tables 1 and 2, unusual instruction UN1, usual instruction US1, and unusual instruction UN2 are started in respective cycles 1, 2 and 3. In Table 1, instruction US1 goes through all the three pipeline stages because it immediately follows an unusual instruction. The instructions' results appear on output Rs in respective cycles 5, 6 and 7.
In Table 2, during cycle 5, the result of instruction UN1 is provided on the output Rs. Instruction US1 does not go through the third stage but waits in the second stage. Therefore, instruction UN2 has to wait in the first stage in cycle 5 rather than going through the second stage as in Table 1. Hence the result of instruction UN2 appears on output Rs one cycle later than in Table 1. Thus, the throughput is reduced and the execution latency of instruction UN2 is increased. In Table 2, no new instruction is started in cycle 5. Therefore, the instructions immediately following the instruction UN2 will also be delayed.
TABLE 1______________________________________ Pipeline stages cycle input 1st 2nd 3rd output______________________________________ UN1 12 US1 UN13 UN2 US1 UN14 UN2 US1 UN15 UN2 US1 UN16 UN2 US17 UN2______________________________________
TABLE 2______________________________________ Pipeline stages cycle input 1st 2nd 3rd output______________________________________ UN1 12 US1 UN13 UN2 US1 UN14 UN2 US1 UN15 UN2 US1 UN16 UN2 US17 UN2 8 UN2______________________________________
To reduce the execution time, the right and left shift amounts for shifter 150 are generated by EASC 126 in the first pipeline stage in parallel with generation of vectors SP, CP by circuits 142, 122. The shift amounts are latched by register 118.2, and then by register 130.2 which provides them to shifter 150 at the start of the instruction's third cycle.
EASC 126 provides to multiplexer 146 possible result exponents ResExp, ResExp1. See FIG. 3 illustrating a portion of multiplexer 146. The actual result exponent will depend on whether multiplexer 146 will perform a onedigit normalization shift. The two possible exponents are latched by register 118.3 and then by register 130.3. The outputs of registers 118.3, 130.3 are connected to data inputs of multiplexer 310. The select input of multiplexer 310 receives a signal sout indicating whether the result multiplexer 146 is executing a 3cycle or a 4cycle instruction. If the instruction is a 3cycle instruction, multiplexer 310 selects the output of register 118.3. Otherwise, multiplexer 310 selects the output of register 130.3. Registers 118.3, 130.3 are clocked by signal CLK.
Some embodiments have different numbers of pipeline stages and/or pipeline resisters. The exact position of pipeline registers is also different in some embodiments. While in multiplier 110 of FIG. 1 all instructions are divided into two categoriesfast and slowin some other embodiments the instructions are divided into more than two categories. Instructions in different categories may require a different number of clock cycles for their execution. For example, in some embodiments, one category may include fast instructions in which: 1) normalization or denormalization may require a shift by at most one digit, or by at most two digits, or by at most some other number of digits, and/or 2) rounding is not required or requires at most a simple operation such as truncation. Other categories include slower instructions in which normalization, denormalization, and/or rounding are more complex. The fast instructions initially follow a fast execution path (such as the path from adder 134 directly to multiplexer 146 in FIG. 1). When a slower instruction is encountered, the execution is switched to a slower path for the slower instruction and for subsequent instructions in the same and faster categories. If a still slower instruction is encountered, the execution is switched to a still slower path. When a sufficient number of clock cycles accumulate in which no instruction is started, the execution is switched to a faster path. If possible, the execution is switched to the fastest possible path.
The operation of multiplier 110 will now be illustrated on the example of IEEE Standard 754 described in "IEEE Standard for Binary FloatingPoint Arithmetic" (American National Standards Institute 1985) hereby incorporated herein by reference. Multiplier 110 performs "single format" multiplication instructions on single format operands and "double format" instructions on double format operands, and provides respectively a single or double format result Rs. In both formats, a floating point number (1)^{s} 2^{E} (h.f) is represented in a computer memory by 1bit sign s immediately followed by biased exponent e which is immediately followed by fraction f. Hidden bit h is not included in the representation. For normalized numbers:
h=1,
e=E+BIAS, 1<e<ExpMax, where BIAS and ExpMax are predefined constants.
If a number is too small in magnitude to be represented as a normalized number, it is represented as either a denormalized number or 0. In both cases:
h=0,
E=1BIAS, e=0.
For denormalized numbers, the fraction f≠s 0. For zero numbers, f=0.
In the double format, each number is represented in a 64bit field: fraction f is 52 bits long, and exponent e is 11 bits long. BIAS=1023, and ExpMax=2046. In the single format, f is 23 bits long, e is 8 bits long, BIAS=127, and ExpMax=254. In both formats the value e=ExpMax+1 is used to represent infinity or NaN ("not a number"), as described in "IEEE Standard for Binary FloatingPoint Arithmetic", cited above.
In FIG. 1, operand registers 114.2, 114.3 are 64bit registers. Singleformat operands are represented in a 64bit field as follows. The sign s is in the most significant bit, i.e., bit 63 (bits are numbered starting from the least significant bit which is bit number 0). The exponent e occupies the next eleven bits 62:52!. The exponent is aligned so that the least significant bit of the exponent is in the least significant bit 52 of the 11bit field. Fraction f occupies the remaining 52 bits. The most significant bit of the fraction is in the most significant bit 51 of the 52bit field.
Opcode register 114.4 receives opcode OPC which specifies whether the instruction is a single or double format instruction. Register 114.5 receives the rounding mode RM which is one of the four modes specified by IEEE Standard 754 ("round to nearest", "round toward plus infinity", "round toward minus infinity", or "round toward 0").
Booth circuit 142 generates 27 partial products of 53bit significands hf of operands OP1, OP2 according to the radix4 Booth method. Each partial product is 57 bits long. The 57 bits include: 54 bits for a possibly shifted multiplier significand, two sign bits, and one least significant bit (LSB) appended for the case when the previous partial product was negative. In addition, there is a hidden zero bit between the LSB and the other 56 bits of the partial product. Of the two signed bits, the less significant bit is an exclusive OR of the signs of the partial product itself and all the previous partial products (if any). The more significant sign bit is an OR of the sign of the partial product itself and the signs of all the previous partial products (if any). If the immediately preceding partial product is negative, the 54 bits of the immediately preceding partial product that follow the sign bits are complemented, and the LSB of the current partial product is set to 1. Otherwise, the LSB is 0.
Adder 122 adds the partial products and generates two 106bit vectors SP, CP. Significand adder 134 adds SP and CP and generates onevector significand product FAD. If the instruction is to be completed in 3 cycles adder 134 rounds the product. If the instruction is to be completed in 4 cycles, adder 134 does not round the product; rounding will be performed by rounding adder 154.
FIG. 4 is a block diagram of a portion 126.1 of EASC 126 of FIG. 1. Circuit 126.1 generates the possible result exponents ResExp, ResExp1 and also generates rightshiftamount signal RSHIFT and leftshiftamount signal LSHIFT for significand shifter 150. Circuit 126.1 operates in the first pipeline stage.
In circuit 126.1, multiplexer 410 generates signal Exp1 representing the exponent of operand OP1. The select input of multiplexer 410 receives signal dnrml indicating whether operand OP1 is denormalized. If dnrml is deasserted, the operand is normalized, and multiplexer 410 selects the operand's exponent OP1 62:52!. If dnrm1 is asserted, multiplexer 410 selects Exp1=1. Signal dnrm1 is generated by operand analyzer 414 (FIG. 1) using methods known in the art.
Similarly, based on signal dnrm2 generated by operand analyzer 414, multiplexer 418 selects Exp2=OP2 62:52! if operand OP2 is normalized, and Exp2=1 if not.
ExpMax/BIAS generator 422 receives from OPC register 114.4 a signal double indicating whether the instruction in the first pipeline stage is a doubleformat instruction. Generator 422 generates the maximum exponent ExpMax and the signal BIAS according to the following Table 3. BIAS is in two's complement form. In the description of EASC 126, two's complement form is assumed unless stated otherwise.
TABLE 3______________________________________ single formatat______________________________________ 7fe (hex)M x 0fe (hex)BIAS 401 (hex) 781 (hex)______________________________________
A row of full adders 426 performs bitwise addition and generates the carry and sum vectors for
Exp1+Exp2BIAS
Adder 430 sets the least significant bit of the carry vector to 1 and adds the sum vector, thus generating
SUM=Exp1+Exp2+1BIAS.
Adder 434 adds the carry and sum vectors and thus generates
SUM1=Exp1+Exp2BIAS.
SUM will be the result exponent if the result Rs is normalized and FAD 105!=1. In this case, FAD 105! is the hidden bit of the result significand, and FAD 104! is the most significant bit of the result fraction. SUM1 is the result exponent if: (i) the result Rs is normalized, (ii) FAD 105!=0, and (iii) FAD 104!=1. In this case, multiplexer 146 shifts FAD left by one bit.
Multiplexer 438 generates a signal ZAM indicative of the number of leading zeroes in the significand product FAD. ZAM is selected from signals Lzero1, Lzero2 generated by operand analyzer 414. Lzero1 is the number of leading zeroes in the significand hf of operand OP1. Lzero2 is the number of leading zeroes in the significand of operand OP2. The select inputs of multiplexer 438 receive signals dnrm1, dnrm2. The output ZAM of multiplexer 438 is equal to the input Lzero1 or Lzero2 corresponding to a denormalized operand. If both operands are normalized, ZAM=0. If both operands are denormalized, ZAM is the OR of Lzero1 and Lzero2 and thus is at least as large as Lzero1 and Lzero2; an "extreme underflow" occurs, and result multiplexer 146 selects the result based on the sticky bit, the operands' signs, and the rounding mode RM. The result is generated in four cycles. The sign of the result is the exclusive OR of the signs of the operands. The result is the smallest positive denormalized number if the result sign is plus, the rounding mode is "toward plus infinity", and the sticky bit is 1. The result is the largest negative denormalized number (the smallest in magnitude negative denormalized number) if the result sign is minus, the rounding mode is "toward minus infinity", and the sticky bit is 1. In the remaining cases, the result is 0.
Adders 442, 446 generate respectively the signals DIF, DIF1 which are possible exponent values for the case when the multiplication result Rs is normalized whether or not the operands are normalized. More particularly, adder 442 receives SUM and ZAM and generates
DIF=SUMZAM.
If the result Rs is normalized, DIF is the result exponent in the case MSBP=1 where MSBP is the most significant bit of the product of the significant portions of the significands of the operands OP1, OP2. For 3cycle instructions, MSBP=MSBF where:
MSBF=FAD 105!.
For 4cycle instructions:
MSBP=MSBR=RAD 53!.
Adder 446 receives SUM1 and ZAM and generates DIF1=(SUM1)ZAM.
If the result Rs is normalized, DIF1 is the result exponent if MSBP=0.
Comparator 450 receives ExpMax, SUM and SUM1 and generates the following signals:
1) SUM<1 which means that the product significand has to be shifted right by shifter 150.
2) SUM>0 which means that FAD may be shifted left by zero or more bits if needed.
3) OF=(SUM>ExpMax).
Comparator 454 receives DIF and generates the following signals:
1) Extreme underflow signal EU=(DIF<1fcc (hex)). 1fcc (hex)=52 (decimal) in two's complement form. EU means that no significant digits of FAD will appear in the result if the result is shifted right to bring the exponent up to its minimum value of 1. In some embodiments, comparator 450 receives also the signal double and generates EU=(DIF<1fcc (hex)) for double format instructions and EU=(DIF<f9 (hex)=23 (decimal)) for single format instructions.
2) DIF>0 means that the result is possibly normalized whether or not both operands are normalized.
3) UNF=(DIF<2). UNF means an underflow or a conditional underflow. A conditional underflow is the condition DIF 1. If DIF=1, then: (a) if MSBP=0, the result is not normalized, (b) if MSBP=1 the result is normalized.
Adder 458 receives SUM1 and generates the possible right shift amount 1SUM. This shift amount is generated by complementing "SUM1" and adding 1 to the complement.
Multiplexer 462 generates the right shift amount RSHIFT. If signal EU is reset, RSHIFT is set to the output "1SUM" of adder 458. If EU is set (an extreme underflow), RSHIFT is set to 37 (hex). The shift amount of 37(hex) guarantees that FAD will be shifted out of the fraction field of the result even in a double format instruction.
Multiplexer 462 also generates the right shift flag FRSHIFT that a right shift is needed. FRSHIFT is set to output "SUM<1" of comparator 450.
Multiplexer 466 receives signals ZAM, "SUM1", "DIF>0" and "SUM>0". Multiplexer 466 generates the left shift amount LSHIFT and the flag FLSHIFT="SUM>0" that a left shift by zero or more digits may be performed if needed. If DIF>0, LSHIFT=ZAM. If not, LSHIFT=SUM1.
Multiplexer 470 generates the result exponent signal ResExp for the case MSBP=1. Multiplexer 474 generates the result exponent signal "ResExp1" for the case MSBP=0. The two result exponents are generated in accordance with FIG. 5. The data inputs of multiplexer 470 are ExpMax+1, 0, and DIF. The data inputs of multiplexer 474 are ExpMax, 0, "DIF1". The select inputs of each multiplexer receive OF="SUM>ExpMax" and "DIF>0".
FIG. 6 shows a circuit generating the signal sout controlling the result multiplexer 146. The circuit of FIG. 6 is a portion of EASC 126. If sout=0, multiplexer 146 selects the output RAD of rounding adder 154, and the instruction completes in four cycles. If sout=1, multiplexer 146 selects the output FAD of adder 134, and the instruction completes in three cycles.
As shown in FIG. 6, operand analyzer 414 generates signals nrm1, nrm2 which are set if the respective operand OP1 or OP2 is normalized. Thus, nrm1=1 means
ExpMax≧OP1 62:52!>0.
Similarly, nrm2=1 means
ExpMax≧OP2 62:52!>0.
AND gates 610, 620 generate respective products "dnrm1 & nrm2", "nrm1 & dnrm2". NOR gate 624 generates the signal
short=NOT(dnrm1 & nrm2nrm1 & dnrm2UNF). "&" is logical AND, "" is logical OR. If short=1, the instruction is usual and can be executed in three cycles. If short=0, the instruction is unusual.
Signal short is delivered to one input of AND gate 628.
Signal start is asserted at the start of a multiplication instruction. This signal is latched in register 114.7 which is part of input register 114. Signal start is latched simultaneously with operands OP1, OP2 for the same instruction. The output start_{} d1 of register 114.7 is inverted by inverter 632. The outputs of inverter 632 and AND gate 628 are ORed by OR gate 634 whose output s1 is latched by masterslave flipflop 638. The flipflop's output, labelled s2, is ANDed with short by AND gate 628.
AND gate 642 generates s3=s1 & s2. Signal s3 is latched by masterslave flipflop 646 whose output provides sout. All the registers 114.i and flipflops 638, 646 are masterslave flipflops triggered by the positive edge of the same clock CLK.
If start=0, on the next cycle s1=1, and two cycles later sout=1. When start is asserted in a clock cycle n to indicate the beginning of an instruction, short becomes valid for the instruction on the next cycle n+1, that is, on the same cycle on which the adder 122 (FIG. 1) performs the addition for the instruction. If s2 has remained at 1 since before start was asserted, then si becomes equal to short. In the same cycle n+1, s3 becomes equal to short. On the next cycle, that is, in the second pipeline stage, sout becomes equal to short.
When start is asserted and short becomes 0, s2 becomes 0 on the next cycle and holds s1, s2, s3 and sout at 0 until start is deasserted.
FIG. 7 illustrates the timing for the circuit of FIG. 6 for the instruction sequence {s1s1ss}, where "s" denotes a usual instruction, "1" denotes an unusual instruction, and "" denotes no instruction. Boxes "res3" and "res4" at the bottom indicate when respectively a 3cycle or 4cycle result is selected by result multiplexer 146. Dashed diagonal lines connect each box to the portion of the start signal for the same instruction. The signals change on the falling edge of clock CLK because the registers and flipflops in FIG. 6 are masterslave flipflops.
FIGS. 810 illustrate the operation of result multiplexer 146 and result multiplexer control circuit 710. Circuit 710 generates 3bit control signal RMC to result multiplexer 146. Circuit 710 receives the following input signals:
1) Result type signals:
a) res_{} nrm=NOT (DIF<2) AND NOT OF. This signal means that the result is normalized. This signal is generated by EASC 126.
b) res_{} inf means that the result is infinity. This signal is asserted by operand analyzer 414 if one of the operands OP1, OP2 is infinity and the other operand is not zero.
c) res_{} zero is asserted by operand analyzer 414 if one of the operands OP1, OP2 is zero and the other operand is not infinity.
Signals res_{} nrm, res_{} inf, res_{} zero are generated in the second pipeline stage. Their respective delayed versions res_{} nrm_{} d1, res_{} inf_{} d1, res_{} zero_{} d1 are delayed by one cycle. Signal res_{} nrm_{} d1 is generated by EASC 126. Signals res_{} inf_{} d1, res_{} zero_{} d1 are generated by operand analyzer 414.
Other input signals of result multiplexer control circuit 710 are as follows.
2) sout
3) Overflow and underflow signals generated by EASC 126:
a) OVF=(SUM>ExpMax+1) generated by EASC 126 means an overflow.
b) OVF_{} c=(SUM=ExpMax+1) means a overflow, that is, an overflow occurs if MSBP=1 but no overflow occurs if MSBP=0. Signals OVF, OVF_{} c are generated in the second pipeline stage.
c) OVF_{} d1 and OVF_{} c_{} d1 are generated in the third pipeline stage. These signals are delayed versions of respectively OVF, OVF_{} c.
d) UNF_{} d1=(DIF<1) means an underflow. This signal is generated in the third pipeline stage.
e) UNF_{} c_{} d1=(DIF=1) means a conditional underflow. This signal is generated in the third pipeline stage.
4) MSBF, MSBR.
5) "excep" means an unmasked exception. This signal is generated from OVF 754 (overflow), UNF_{} 754 (underflow), INEX (inexact result) and INV (invalid operands) which are four exception signals in accordance with IEEE Standard 754. OVF_{} 754 and UNF_{} 754 are generated by EASC 126. INEX is generated by adder 134 for fast instructions and adder 154 for slow instructions. INV (which means a signal NaN operand or a multiplication of zero by infinity) is generated by operand analyzer 414. Signal "except" is set if any of the four exceptions occurs and the corresponding exception mask in register 114.6 is "1".
Of note, no more than one signal in each of the following two groups can be set in any given clock cycle:
Group I: res_{} nrm, res_{} inf, res_{} zero, OVF, OVF_{} c;
Group II: res_{} nrm_{} d1, res_{} inf_{} d1, res_{} zero_{} d1, OVF_{} d1, OVF_{} c_{} d1, UNF_{} d1, UNF_{} c_{} 1.
FIG. 8 illustrates signals in result multiplexer control circuit 710 and result multiplexer 146 when sout=1, that is, for 3cycle instructions. FIG. 9 illustrates signals in circuits 710, 146 when sout=0. In the tables of FIGS. 8 and 9, RMC is the signal generated by result multiplexer control circuit 710. Column "Result" shows the result generated by multiplexer 146 in response to signal RMC. "FAD<<1" means FAD shifted left by one bit. "RAD<<1" means RAD shifted left by one bit. OVFL means an overflow. "x" means "don't care."
FIG. 10 shows the exponent and fraction portions of signal Rs generated by multiplexer 146 for each value in the "Result" column in FIGS. 8 and 9.
FIG. 11 is a block diagram of significand adder 134. FIG. 12 illustrates operations performed by adder 134. If sout=1, that is, the instruction will be completed in three cycles, adder 134 performs both addition and rounding. If sout=0, adder 134 performs the addition but not rounding; rounding is performed by adder 154.
To make rounding faster, the bit positions 105:0! are divided into the following groups: group 810 of result bits which will be included in the significand of the result Rs of the instruction; group 814 of dropped bits not included in the significand of the result; and group 818 of boundary bits S1, S0, G0. Bit S0 is the least significant bit of the significand of the result Rs if MSBF=0. If MSBF=1, the least significant bit of Rs is S1. G0 is a guard bit, which is not included in the result.
The position of the result bits, the dropped bits and the boundary bits is determined based on the assumption that MSBF=FAD 105! and the result Rs will be normalized, because the adder 134 performs rounding only when this assumption is true. Thus, the least significant bit ResL of result bits 810 is bit 54 for double format instructions and bit 83 for single format instructions.
In fraction adder 134, the rounding overlaps with the addition so that the delay compared to the addition without rounding is only a halfadder delay.
When CP, SP are added, two carries can be generated into result bits 810: a carry from the addition of boundary bits 818 and dropped bits 814, and a carry from the addition of rounding bit RB to bit S0 (if MSBF=0) or S1 (if MSBF=1). The addition of SP and CP is performed as follows. The result bits SP 105:ResL!, CP 105:ResL! are delivered to a row of halfadders 822 which perform bitwise addition and generate a sum vector SPP 105:ResL! and a carry vector CPP 105:ResL+1!. At the same time, adder 826 adds the boundary bits 818 of vectors SP, CP and generates the sum SB and a carry CB which is placed in CPP ResL!.
To add SPP 105:ResL! and CPP 105:ResL!, the result bits are divided into subgroups for conditional sum generation. For each subgroup, a respective adder 830 generates two conditional sums of the respective bits of SPP, CPP. One of the two sums assumes that the carry into the subgroup is 0. The other sum assumes the carry into the subgroup is 1. Operation of subgroup adders 830 is similar to the operation performed in conventional conditionalsum adders such as described, for example, in A. R. Omondi, "Computer Arithmetic Systems: Algorithms, Architecture and Implementation", 1994, pp. 7689 hereby incorporated herein by reference.
The conditional sums for each subgroup are delivered to the data inputs of a respective multiplexer 834. The select input of the multiplexer receives a respective carry GC into the subgroup. The multiplexer selects the sum corresponding to the carry GC, as in a conventional conditionalsum adder. However, the subgroup carries GC take into account the rounding carry RB and the carry Cin from the dropped bits 814.
The carries GC are generated as follows. The addition of carry Cin and rounding carry RB to the boundarybit sum SB can generate at most one carry Cout into the result bits. See FIG. 12. Logic expressions for the carry Cout can be constructed from truth tables, such as Tables 4 and 5 below, which express Cout in terms of: 1) bits S1, S0, G0 of boundary sum SB; 2) MSBF; 3) Cin; 4) sticky bit ST; 5) the result sign SN; and 6) the rounding mode. SN is the exclusive OR of the signs of the operands OP1, OP2. Sticky bit ST=1 if, and only if, at least one dropped bit in the product FAD is 1. ST is generated before FAD by circuit 838 (FIG. 1) as follows. Circuit 838 determines the total number SLSBZ of the least significant zeroes of the significands of operands OP1, OP2, where the significands of singleformat operands are represented in a 53bit field as described above. If SLSBZ<ResL3, then ST is set to 1. Otherwise, ST is set to 0. Of note, ResL3 is the position of guard bit G0.
ST and SN are delivered to adder 134 in the second pipeline stage.
Tables 4 and 5 are truth tables for the carry Cout for the rounding mode "round to nearest". In Table 4, Cin=0. In Table 5, Cin=1. ST and SN are omitted because they do not influence Cout in the "round to nearest" mode.
TABLE 4______________________________________ Cin = 0 MSBF S1 S0 G0 Cout______________________________________ 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 00 1 0 0 00 1 0 1 00 1 1 0 00 1 1 1 11 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 01 1 0 0 01 1 0 1 01 1 1 0 1______________________________________
TABLE 5______________________________________Cin = 1MSBF S1 S0 G0 Cout______________________________________0 0 0 0 00 0 0 1 00 0 1 0 00 0 1 1 00 1 0 0 00 1 0 1 00 1 1 0 10 1 1 1 11 0 0 0 01 0 0 1 01 0 1 0 01 0 1 1 01 1 0 0 01 1 0 1 11 1 1 0 11 1 1 1 1______________________________________ From Tables 4 and 5, we obtain:Cout = S1&S0&G0  (1)0 if Cin = 0,Cout = S1&S0  MSBF&S1&G0 if Cin = 1.
Expressions for Cout in the remaining rounding modes can be obtained similarly.
To reduce the delay due to rounding, adder 134 is constructed similarly to a nonrounding conditionalsum cyclic adder. (A cyclic adder is an adder that adds the endaroundcarry to the least significant bit.) Carry Cout is generated as:
Cout=CoutgMSBF & Coutp. (2)
In a nonrounding cyclic adder, Coutg would be a carry generate signal for the boundary bits 818, Coutp would be a carry propagate signal for the boundary bits, and MSBF would be the endaround carry into the boundary bits. In adder 134, signals Coutg, Coutp have a different meaning defined below. However, because the carry expression (2) is the same as for a nonrounding adder, the delay of adder 134 is equal to the delay of a nonrounding adder plus one halfadder delay of adders 822.
Signal Coutg is the value of Cout when MSBF=0. Coutp is the value of Cout when MSBF=1. Each circuit 842.1 through 842.4 generates Coutg, Coutp for a respective one of the four rounding modes "to nearest", "toward plus infinity", "toward minus infinity", and "toward zero" in accordance with FIG. 13. The expressions of FIG. 13 can be obtained as follows. Obtain expressions for Cout such as expressions (1) above. In the expressions for Cout, set MSBF=0 to obtain expressions for Coutg, and set MSBF=1 to obtain expressions for Coutp. Each circuit 842.i generates Coutg, Coutp for Cin=0 and Cin=1. Multiplexer 846 selects carries Coutg, Coutp based on the rounding mode signal RMODE generated from the rounding mode signal RM (FIG. 1).
Subgroup carry generator circuit 850 receives the carry signals Coutg, Coutp from multiplexer 846 and also receives from circuit 854 carry generate and carry propagate signals for the subgroups of result bits 810. Carry generator circuit 850 generates subgroup carries GC for the cases Cin=0 and Cin=1. The subgroup carries for each of the two Cin values are generated as in a conventional nonrounding conditionalsum adder.
Operating in parallel with circuits 842.i, 846, 850, 826, 822, and 830, circuit 858 adds the dropped bits 814 of operands CP, SP and generates 1) the dropped bits of FAD, and 2) the carry Cin from the dropped bits. Based on the carry Cin, multiplexer 862 selects the respective subgroup carries GC generated by circuit 850. The dropped bits of FAD may become part of the result in 4cycle instructions.
Circuit 866 receives boundary sum SB, sticky bit ST, result sign SN, and rounding mode RMODE. For each value of Cin, circuit 866 generates the result bits S1, S0 by adding the rounding bit RB to bit S0 (if MSBF=0) or S1. Circuit 866 generates MSBF signals for the cases Cin=0 and Cin=1 from: 1) the possible carries, for Cin=0 and 1, into the most significant subgroup of result bits 810; these carries are generated by circuit 850; and 2) carry propagate and carry generate signals for the most significant subgroup; these signals are generated by circuit 854.
Multiplexer 870 selects the appropriate boundary bits of FAD based on the value Cin.
If sout=0, then the rounding mode signal RMODE in adder 134 is set to "round toward zero" regardless of the value RM. Rounding bit RB in adder 134 is set to zero. The rounding is performed by rounding adder 154 using methods known in the art. See, for example, R. K. Yu et al., "167 MHz Radix4 Floating Point Multiplier", Proceedings of the Twelfth Symposium on Computer Arithmetic (IEEE 1995), pages 149154, hereby incorporated herein by reference. The sticky bit for adder 154 is generated by circuit 874 (FIG. 1) as follows. The sticky bit is 1 if and only if
SLSBZRSHIFT+LSHIFT<ResL3
The sticky bit is pipelined to reach the rounding adder in the third pipeline stage.
Exception mask register 114.6 (FIG. 1) receives a 4bit exception mask with one bit for each of the exceptions "Invalid Operation", "Overflow", "Underflow", "Inexact" specified by the IEEE Standard 754. Exception generator 878 receives the mask from register 114.6 and also receives: 1) MSBF and MSBR from respective adders 134, 154; 2) OVF, OVF_{} c, UNF, and UNF_{} c from EASC 126; inexact exception signals INEX from adders 134, 154; 4) INV from operand analyzer 414; and 5) the signal sout from EASC 126. Exception generator 878 generates two 4bit exception signals. Each signal has one bit for each of the four exceptions. One of the 4bit signals takes into account the exception mask, and the other one of the 4bit signals does not. To provide the exception signals on the same clock cycle on which the corresponding result Rs is generated, 878 uses register/multiplexer circuitry similar to that of FIG. 3.
Diagnostic information register 114.1 receives the instruction number and provides it to diagnostic information multiplexer 882. Multiplexer 882 receives the signal sout from EASC 126. Diagnostic information multiplexer 882 provides the diagnostic information to result multiplexer 146.
The invention is not limited by the embodiments described above. In particular, the invention is not limited by any floating point format or by any circuitry or fabrication technology. In some embodiments, a new instruction cannot be started every clock cycle but can only be started every 2 cycles or some other number of cycles. In some embodiments, multiplication instructions are part of combined multiplyadd instructions or other instructions, and a floating point multiplier of the invention is a part of a multiplyadd unit or a unit for executing other instructions that incorporate multiplication. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.
Claims (47)
Priority Applications (3)
Application Number  Priority Date  Filing Date  Title 

PCT/RU1996/000210 WO1998006029A1 (en)  19960807  19960807  Apparatus and methods for execution of computer instructions 
US08719115 US5844830A (en)  19960807  19960924  Executing computer instrucrions by circuits having different latencies 
US08926589 US5963461A (en)  19960807  19970904  Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization 
Applications Claiming Priority (2)
Application Number  Priority Date  Filing Date  Title 

US08926589 US5963461A (en)  19960807  19970904  Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization 
US09082440 US6099158A (en)  19960807  19980520  Apparatus and methods for execution of computer instructions 
Related Parent Applications (1)
Application Number  Title  Priority Date  Filing Date  

US08719115 Division US5844830A (en)  19960807  19960924  Executing computer instrucrions by circuits having different latencies 
Related Child Applications (1)
Application Number  Title  Priority Date  Filing Date 

US09082440 Division US6099158A (en)  19960807  19980520  Apparatus and methods for execution of computer instructions 
Publications (1)
Publication Number  Publication Date 

US5963461A true US5963461A (en)  19991005 
Family
ID=26653676
Family Applications (3)
Application Number  Title  Priority Date  Filing Date 

US08719115 Expired  Lifetime US5844830A (en)  19960807  19960924  Executing computer instrucrions by circuits having different latencies 
US08926589 Expired  Lifetime US5963461A (en)  19960807  19970904  Multiplication apparatus and methods which generate a shift amount by which the product of the significands is shifted for normalization or denormalization 
US09082440 Expired  Fee Related US6099158A (en)  19960807  19980520  Apparatus and methods for execution of computer instructions 
Family Applications Before (1)
Application Number  Title  Priority Date  Filing Date 

US08719115 Expired  Lifetime US5844830A (en)  19960807  19960924  Executing computer instrucrions by circuits having different latencies 
Family Applications After (1)
Application Number  Title  Priority Date  Filing Date 

US09082440 Expired  Fee Related US6099158A (en)  19960807  19980520  Apparatus and methods for execution of computer instructions 
Country Status (1)
Country  Link 

US (3)  US5844830A (en) 
Cited By (32)
Publication number  Priority date  Publication date  Assignee  Title 

US6173299B1 (en) *  19970902  20010109  Intrinsity, Inc.  Method and apparatus for selecting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations 
US6175847B1 (en) *  19980722  20010116  Intrinsity, Inc.  Shifting for parallel normalization and rounding technique for floating point arithmetic operations 
US6185593B1 (en) *  19970902  20010206  Intrinsity, Inc.  Method and apparatus for parallel normalization and rounding technique for floating point arithmetic operations 
US6397239B2 (en) *  19980406  20020528  Advanced Micro Devices, Inc.  Floating point addition pipeline including extreme value, comparison and accumulate functions 
US20020178198A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Comparator unit for comparing values of floating point operands 
US20020178200A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Circuit for selectively providing maximum or minimum of a pair of floating point operands 
US20020178201A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  System and method for extracting the high part of a floating point operand 
US20020178199A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Floating point status information testing circuit 
US20020178204A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Floating point status information accumulation circuit 
US20020178197A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  System and method for generating an integer part of a logarithm of a floating point operand 
US20020178202A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Floating point multiplier for delimited operands 
US20020184283A1 (en) *  20010525  20021205  Sun Microsystems, Inc.  Floating point system with improved support of interval arithmetic 
US20020198918A1 (en) *  20010525  20021226  Steele Guy L.  Floating point unit for detecting and representing inexact computations without flags or traps 
US20020198917A1 (en) *  20010525  20021226  Sun Microsystems, Inc.  Floating point adder with embedded status information 
US20030005012A1 (en) *  20010525  20030102  Sun Microsystems, Inc.  System and method for forcing floating point status information to selected values 
US20030005013A1 (en) *  20010525  20030102  Sun Microsystems, Inc.  Floating point system that represents status flag information within a floating point operand 
US20030005014A1 (en) *  20010525  20030102  Sun Microsystems, Inc.  Floating point divider with embedded status information 
US20030009500A1 (en) *  20010525  20030109  Sun Microsystems, Inc.  Floating point remainder with embedded status information 
US20030014455A1 (en) *  20010525  20030116  Sun Microsystems, Inc.  Floating point multiplier with embedded status information 
US20030014454A1 (en) *  20010525  20030116  Sun Microsystems, Inc.  Floating point square root provider with embedded status information 
US20030041081A1 (en) *  20010525  20030227  Sun Microsystems, Inc.  System and method for performing floating point operations involving extended exponents 
US20030126173A1 (en) *  20010525  20030703  Sun Microsystems, Inc.  Total order comparator unit for comparing values of two floating point operands 
US6629120B1 (en) *  20001109  20030930  Sun Microsystems, Inc.  Method and apparatus for performing a maskdriven interval multiplication operation 
US6633896B1 (en) *  20000330  20031014  Intel Corporation  Method and system for multiplying large numbers 
US20040117421A1 (en) *  20021217  20040617  Sun Microsystems, Inc.  Methods and systems for computing floatingpoint intervals 
US20040117420A1 (en) *  20021217  20040617  Sun Microsystems, Inc.  Methods and systems for computing the quotient of floatingpoint intervals 
US20060004990A1 (en) *  20040702  20060105  Seagate Technology Llc  Distributed processing in a multiple processing unit environment 
US20060218380A1 (en) *  20050324  20060928  Stexar Corporation  Addshiftround instruction with dualuse source operand for DSP 
US20070061391A1 (en) *  20050914  20070315  Dimitri Tan  Floating point normalization and denormalization 
US20090249039A1 (en) *  19971009  20091001  Mips Technologies, Inc.  Providing Extended Precision in SIMD Vector Arithmetic Operations 
US9092256B2 (en)  20121206  20150728  International Business Machines Corporation  Vector execution unit with prenormalization of denormal values 
US9817662B2 (en)  20151024  20171114  Alan A Jorgensen  Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof 
Families Citing this family (15)
Publication number  Priority date  Publication date  Assignee  Title 

US6490607B1 (en) *  19980128  20021203  Advanced Micro Devices, Inc.  Shared FP and SIMD 3D multiplier 
US6345286B1 (en) *  19981030  20020205  International Business Machines Corporation  6to3 carrysave adder 
US20040098439A1 (en) *  20000222  20040520  Bass Stephen L.  Apparatus and method for sharing overflow/underflow compare hardware in a floatingpoint multiplyaccumulate (FMAC) or floatingpoint adder (FADD) unit 
US6697833B2 (en) *  20010118  20040224  International Business Machines Corporation  Floatingpoint multiplier for denormalized inputs 
US7558816B2 (en) *  20011121  20090707  Sun Microsystems, Inc.  Methods and apparatus for performing pixel average operations 
US7028167B2 (en) *  20020304  20060411  HewlettPackard Development Company, L.P.  Core parallel execution with different optimization characteristics to decrease dynamic execution path 
US7949701B2 (en)  20060802  20110524  Qualcomm Incorporated  Method and system to perform shifting and rounding operations within a microprocessor 
US7937568B2 (en) *  20070711  20110503  International Business Machines Corporation  Adaptive execution cycle control method for enhanced instruction throughput 
US7779237B2 (en) *  20070711  20100817  International Business Machines Corporation  Adaptive execution frequency control method for enhanced instruction throughput 
JP5300428B2 (en) *  20081113  20130925  ルネサスエレクトロニクス株式会社  Arithmetic apparatus and the arithmetic processing method 
US8332453B2 (en) *  20081210  20121211  International Business Machines Corporation  Shifter with allone and allzero detection using a portion of partially shifted vector and shift amount in parallel to generated shifted result 
US8996601B2 (en) *  20120621  20150331  Advanced Micro Devices, Inc.  Method and apparatus for multiply instructions in data processors 
JP5966764B2 (en) *  20120822  20160810  富士通株式会社  Multiplication equipment and multiplication method 
US9483232B2 (en) *  20140307  20161101  Arm Limited  Data processing apparatus and method for multiplying floating point operands 
US9696992B2 (en) *  20141223  20170704  Intel Corporation  Apparatus and method for performing a check to optimize instruction flow 
Citations (60)
Publication number  Priority date  Publication date  Assignee  Title 

US35311A (en) *  18620520  Improvement in breechloading ordnance  
FR2258666A1 (en) *  19740121  19750818  Data General Corp  
US3900723A (en) *  19740528  19750819  Control Data Corp  Apparatus for controlling computer pipelines for arithmetic operations on vectors 
US4217657A (en) *  19781018  19800812  Honeywell Inc.  Floating point arithmetic control 
EP0110160A2 (en) *  19821029  19840613  Kabushiki Kaisha Toshiba  Floatingpoint arithmetic operation system 
US4488252A (en) *  19820222  19841211  Raytheon Company  Floating point addition architecture 
US4534010A (en) *  19801031  19850806  Hitachi, Ltd.  Floating point type multiplier circuit with compensation for overflow and underflow in multiplication of numbers in two's compliment representation 
EP0180048A2 (en) *  19841025  19860507  International Business Machines Corporation  An arithmetic processor having a parallel accumulate function 
US4589067A (en) *  19830527  19860513  Analogic Corporation  Full floating point vector processor with dynamically configurable multifunction pipelined ALU 
US4777613A (en) *  19860401  19881011  Motorola Inc.  Floating point numeric data processor 
US4839846A (en) *  19850318  19890613  Hitachi, Ltd.  Apparatus for performing floating point arithmetic operations and rounding the result thereof 
US4841467A (en) *  19871005  19890620  General Electric Company  Architecture to implement floating point multiply/accumulate operations 
US4866652A (en) *  19870901  19890912  Weitek Corporation  Floating point unit using combined multiply and ALU functions 
US4878190A (en) *  19880129  19891031  Texas Instruments Incorporated  Floating point/integer processor with divide and square root functions 
US4887232A (en) *  19870515  19891212  Digital Equipment Corporation  Apparatus and method for performing a shift operation in a multiplier array circuit 
US4926369A (en) *  19881007  19900515  International Business Machines Corporation  Leading 0/1 anticipator (LZA) 
US4941120A (en) *  19890417  19900710  International Business Machines Corporation  Floating point normalization and rounding prediction circuit 
EP0394169A2 (en) *  19890417  19901024  International Business Machines Corporation  Method and apparatus for processing postnormalization and rounding in parallel 
US4999802A (en) *  19890113  19910312  International Business Machines Corporation  Floating point arithmetic two cycle data flow 
US5053631A (en) *  19900402  19911001  Advanced Micro Devices, Inc.  Pipelined floating point processing unit 
US5058048A (en) *  19900402  19911015  Advanced Micro Devices, Inc.  Normalizing pipelined floating point processing unit 
US5117384A (en) *  19900124  19920526  International Business Machines Corporation  Method and apparatus for exponent adder 
US5126963A (en) *  19890522  19920630  Nec Corporation  Hardware arrangement for floatingpoint multiplication and operating method therefor 
US5128888A (en) *  19900402  19920707  Advanced Micro Devices, Inc.  Arithmetic unit having multiple accumulators 
US5136536A (en) *  19900504  19920804  Weitek Corporation  Floatingpoint ALU with parallel paths 
US5195051A (en) *  19920331  19930316  Intel Corporation  Computation of sign bit and sign extension in the partial products in a floating point multiplier unit 
US5204825A (en) *  19910830  19930420  Weitek Corporation  Method and apparatus for exact leading zero prediction for a floatingpoint adder 
USH1222H (en) *  19911230  19930803  Apparatus for determining sticky bit value in arithmetic operations  
US5241490A (en) *  19920106  19930831  Intel Corporation  Fully decoded multistage leading zero detector and normalization apparatus 
US5247471A (en) *  19911213  19930921  International Business Machines Corporation  Radix aligner for floating point addition and subtraction 
US5249149A (en) *  19890113  19930928  International Business Machines Corporation  Method and apparatus for performining floating point division 
US5257215A (en) *  19920331  19931026  Intel Corporation  Floating point and integer number conversions in a floating point adder 
US5260889A (en) *  19920331  19931109  Intel Corporation  Computation of stickybit in parallel with partial products in a floating point multiplier unit 
US5272660A (en) *  19920601  19931221  Motorola, Inc.  Method and apparatus for performing integer and floating point division using a single SRT divider in a data processor 
US5276634A (en) *  19900824  19940104  Matsushita Electric Industrial Co., Ltd.  Floating point data processing apparatus which simultaneously effects summation and rounding computations 
US5282156A (en) *  19910131  19940125  Matsushita Electric Industrial Co., Ltd.  Leading one anticipator and floating point addition/subtraction apparatus employing same 
RU2006915C1 (en) *  19911227  19940130  Институт точной механики и вычислительной техники им.С.А.Лебедева РАН  Adder 
US5301139A (en) *  19920831  19940405  Intel Corporation  Shifter circuit for multiple precision division 
US5310134A (en) *  19920316  19940510  Hughes Aircraft Company  Tethered vehicle positioning system 
US5317527A (en) *  19930210  19940531  Digital Equipment Corporation  Leading one/zero bit detector for floating point operation 
US5337265A (en) *  19911220  19940809  International Business Machines Corporation  Apparatus for executing add/sub operations between IEEE standard floatingpoint numbers 
US5341319A (en) *  19930210  19940823  Digital Equipment Corporation  Method and apparatus for controlling a rounding operation in a floating point multiplier circuit 
US5343413A (en) *  19920706  19940830  Matsushita Electric Industrial Co., Ltd.  Leading one anticipator and floating point addition/subtraction apparatus 
US5357455A (en) *  19921009  19941018  Intel Corporation  Floating point remainder generator for a math processor 
US5367186A (en) *  19920128  19941122  Thunderbird Technologies, Inc.  Bounded tub fermi threshold field effect transistor 
US5390134A (en) *  19930129  19950214  HewlettPackard Company  System and method for reducing latency in a floating point processor 
US5463574A (en) *  19921105  19951031  International Business Machines Corporation  Apparatus for argument reduction in exponential computations of IEEE standard floatingpoint numbers 
US5481686A (en) *  19940511  19960102  Vlsi Technology, Inc.  Floatingpoint processor with apparentprecision based selection of executionprecision 
US5487022A (en) *  19940308  19960123  Texas Instruments Incorporated  Normalization method for floating point numbers 
US5493520A (en) *  19940415  19960220  International Business Machines Corporation  Two state leading zero/one anticipator (LZA) 
US5504912A (en) *  19870417  19960402  Hitachi, Ltd.  Coprocessor executing pipeline control for executing protocols and instructions 
US5511016A (en) *  19941130  19960423  International Business Machines Corporation  Method for store rounding and circuit therefor 
US5517438A (en) *  19930929  19960514  International Business Machines, Corporation  Fast multiplyadd instruction sequence in a pipeline floatingpoint processor 
US5528525A (en) *  19921016  19960618  Matsushita Electric Industrial Co., Ltd.  Processor for determining shift counts based on input data 
US5583805A (en) *  19941209  19961210  International Business Machines Corporation  Floatingpoint processor having postwriteback spill stage 
US5630160A (en) *  19950308  19970513  Texas Instruments Incorporated  Floating point exponent compare using repeated two bit compare cell 
US5646875A (en) *  19950227  19970708  International Business Machines Corporation  Denormalization system and method of operation 
US5673407A (en) *  19940308  19970930  Texas Instruments Incorporated  Data processor having capability to perform both floating point operations and memory access in response to a single instruction 
US5748516A (en) *  19950926  19980505  Advanced Micro Devices, Inc.  Floating point processing unit with forced arithmetic results 
US5761103A (en) *  19950308  19980602  Texas Instruments Incorporated  Left and right justification of single precision mantissa in a double precision rounding unit 
Family Cites Families (3)
Publication number  Priority date  Publication date  Assignee  Title 

US5267186A (en) *  19900402  19931130  Advanced Micro Devices, Inc.  Normalizing pipelined floating point processing unit 
US5726927A (en) *  19950911  19980310  Digital Equipment Corporation  Multiply pipe round adder 
US5729485A (en) *  19950911  19980317  Digital Equipment Corporation  Fast determination of carry inputs from lower order product for radix8 odd/even multiplier array 
Patent Citations (61)
Publication number  Priority date  Publication date  Assignee  Title 

US35311A (en) *  18620520  Improvement in breechloading ordnance  
FR2258666A1 (en) *  19740121  19750818  Data General Corp  
US3900723A (en) *  19740528  19750819  Control Data Corp  Apparatus for controlling computer pipelines for arithmetic operations on vectors 
US4217657A (en) *  19781018  19800812  Honeywell Inc.  Floating point arithmetic control 
US4534010A (en) *  19801031  19850806  Hitachi, Ltd.  Floating point type multiplier circuit with compensation for overflow and underflow in multiplication of numbers in two's compliment representation 
US4488252A (en) *  19820222  19841211  Raytheon Company  Floating point addition architecture 
EP0110160A2 (en) *  19821029  19840613  Kabushiki Kaisha Toshiba  Floatingpoint arithmetic operation system 
US4589067A (en) *  19830527  19860513  Analogic Corporation  Full floating point vector processor with dynamically configurable multifunction pipelined ALU 
EP0180048A2 (en) *  19841025  19860507  International Business Machines Corporation  An arithmetic processor having a parallel accumulate function 
US4683547A (en) *  19841025  19870728  International Business Machines Corporation  Special accumulate instruction for multiple floating point arithmetic units which use a putaway bus to enhance performance 
US4839846A (en) *  19850318  19890613  Hitachi, Ltd.  Apparatus for performing floating point arithmetic operations and rounding the result thereof 
US4777613A (en) *  19860401  19881011  Motorola Inc.  Floating point numeric data processor 
US5504912A (en) *  19870417  19960402  Hitachi, Ltd.  Coprocessor executing pipeline control for executing protocols and instructions 
US4887232A (en) *  19870515  19891212  Digital Equipment Corporation  Apparatus and method for performing a shift operation in a multiplier array circuit 
US4866652A (en) *  19870901  19890912  Weitek Corporation  Floating point unit using combined multiply and ALU functions 
US4841467A (en) *  19871005  19890620  General Electric Company  Architecture to implement floating point multiply/accumulate operations 
US4878190A (en) *  19880129  19891031  Texas Instruments Incorporated  Floating point/integer processor with divide and square root functions 
US4926369A (en) *  19881007  19900515  International Business Machines Corporation  Leading 0/1 anticipator (LZA) 
US4999802A (en) *  19890113  19910312  International Business Machines Corporation  Floating point arithmetic two cycle data flow 
US5249149A (en) *  19890113  19930928  International Business Machines Corporation  Method and apparatus for performining floating point division 
US4941120A (en) *  19890417  19900710  International Business Machines Corporation  Floating point normalization and rounding prediction circuit 
EP0394169A2 (en) *  19890417  19901024  International Business Machines Corporation  Method and apparatus for processing postnormalization and rounding in parallel 
US5126963A (en) *  19890522  19920630  Nec Corporation  Hardware arrangement for floatingpoint multiplication and operating method therefor 
US5117384A (en) *  19900124  19920526  International Business Machines Corporation  Method and apparatus for exponent adder 
US5058048A (en) *  19900402  19911015  Advanced Micro Devices, Inc.  Normalizing pipelined floating point processing unit 
US5053631A (en) *  19900402  19911001  Advanced Micro Devices, Inc.  Pipelined floating point processing unit 
US5128888A (en) *  19900402  19920707  Advanced Micro Devices, Inc.  Arithmetic unit having multiple accumulators 
US5136536A (en) *  19900504  19920804  Weitek Corporation  Floatingpoint ALU with parallel paths 
US5276634A (en) *  19900824  19940104  Matsushita Electric Industrial Co., Ltd.  Floating point data processing apparatus which simultaneously effects summation and rounding computations 
US5282156A (en) *  19910131  19940125  Matsushita Electric Industrial Co., Ltd.  Leading one anticipator and floating point addition/subtraction apparatus employing same 
US5204825A (en) *  19910830  19930420  Weitek Corporation  Method and apparatus for exact leading zero prediction for a floatingpoint adder 
US5247471A (en) *  19911213  19930921  International Business Machines Corporation  Radix aligner for floating point addition and subtraction 
US5337265A (en) *  19911220  19940809  International Business Machines Corporation  Apparatus for executing add/sub operations between IEEE standard floatingpoint numbers 
RU2006915C1 (en) *  19911227  19940130  Институт точной механики и вычислительной техники им.С.А.Лебедева РАН  Adder 
USH1222H (en) *  19911230  19930803  Apparatus for determining sticky bit value in arithmetic operations  
US5241490A (en) *  19920106  19930831  Intel Corporation  Fully decoded multistage leading zero detector and normalization apparatus 
US5367186A (en) *  19920128  19941122  Thunderbird Technologies, Inc.  Bounded tub fermi threshold field effect transistor 
US5310134A (en) *  19920316  19940510  Hughes Aircraft Company  Tethered vehicle positioning system 
US5257215A (en) *  19920331  19931026  Intel Corporation  Floating point and integer number conversions in a floating point adder 
US5260889A (en) *  19920331  19931109  Intel Corporation  Computation of stickybit in parallel with partial products in a floating point multiplier unit 
US5195051A (en) *  19920331  19930316  Intel Corporation  Computation of sign bit and sign extension in the partial products in a floating point multiplier unit 
US5272660A (en) *  19920601  19931221  Motorola, Inc.  Method and apparatus for performing integer and floating point division using a single SRT divider in a data processor 
US5343413A (en) *  19920706  19940830  Matsushita Electric Industrial Co., Ltd.  Leading one anticipator and floating point addition/subtraction apparatus 
US5301139A (en) *  19920831  19940405  Intel Corporation  Shifter circuit for multiple precision division 
US5357455A (en) *  19921009  19941018  Intel Corporation  Floating point remainder generator for a math processor 
US5528525A (en) *  19921016  19960618  Matsushita Electric Industrial Co., Ltd.  Processor for determining shift counts based on input data 
US5463574A (en) *  19921105  19951031  International Business Machines Corporation  Apparatus for argument reduction in exponential computations of IEEE standard floatingpoint numbers 
US5390134A (en) *  19930129  19950214  HewlettPackard Company  System and method for reducing latency in a floating point processor 
US5317527A (en) *  19930210  19940531  Digital Equipment Corporation  Leading one/zero bit detector for floating point operation 
US5341319A (en) *  19930210  19940823  Digital Equipment Corporation  Method and apparatus for controlling a rounding operation in a floating point multiplier circuit 
US5517438A (en) *  19930929  19960514  International Business Machines, Corporation  Fast multiplyadd instruction sequence in a pipeline floatingpoint processor 
US5673407A (en) *  19940308  19970930  Texas Instruments Incorporated  Data processor having capability to perform both floating point operations and memory access in response to a single instruction 
US5487022A (en) *  19940308  19960123  Texas Instruments Incorporated  Normalization method for floating point numbers 
US5493520A (en) *  19940415  19960220  International Business Machines Corporation  Two state leading zero/one anticipator (LZA) 
US5481686A (en) *  19940511  19960102  Vlsi Technology, Inc.  Floatingpoint processor with apparentprecision based selection of executionprecision 
US5511016A (en) *  19941130  19960423  International Business Machines Corporation  Method for store rounding and circuit therefor 
US5583805A (en) *  19941209  19961210  International Business Machines Corporation  Floatingpoint processor having postwriteback spill stage 
US5646875A (en) *  19950227  19970708  International Business Machines Corporation  Denormalization system and method of operation 
US5630160A (en) *  19950308  19970513  Texas Instruments Incorporated  Floating point exponent compare using repeated two bit compare cell 
US5761103A (en) *  19950308  19980602  Texas Instruments Incorporated  Left and right justification of single precision mantissa in a double precision rounding unit 
US5748516A (en) *  19950926  19980505  Advanced Micro Devices, Inc.  Floating point processing unit with forced arithmetic results 
NonPatent Citations (36)
Title 

"IC Master 3. Advertisers Technical Data; LSI Logic Products and Services," Hearst Business Communications, Inc., IC Master, 1991, pp. 35292532. 
"IEEE Standard for Binary FloatingPoint Arithmetic, " Institute of Electrical and Electronics Engineers, Inc., New York, Ny, ANSI/IEEE Std. 754, Nov. 1994, pp. 118. 
Benschneider, et al., "A Pipelined 50MHz CMOS 64bit FloatingPoint Arithmetic Processor", IEEE Journal of SolidState Circuits, vol. 24, No. 5, Oct. 1989, pp. 13171323. 
Benschneider, et al., A Pipelined 50 MHz CMOS 64 bit Floating Point Arithmetic Processor , IEEE Journal of Solid State Circuits, vol. 24, No. 5, Oct. 1989, pp. 1317 1323. * 
Encyclopedia of Computer Science & Engineering, Second Edition, Van Nostrand Reinhold Co., New York, Ny, 1983, pp. 98 102, 1322 1324. * 
Encyclopedia of Computer Science & Engineering, Second Edition, Van Nostrand Reinhold Co., New York, Ny, 1983, pp. 98102, 13221324. 
Gwennap, et al., "UltraSparc Unleashes SPARC Performance, NextGeneration Design Could Put Sun Back in Race" Microprocessor Report, vol. 8, No. 13, Oct. 3, 1994, pp. 110. 
Gwennap, et al., UltraSparc Unleashes SPARC Performance, Next Generation Design Could Put Sun Back in Race Microprocessor Report, vol. 8, No. 13, Oct. 3, 1994, pp. 1 10. * 
Hicks, T.N., et al., "POWER2 FloatingPoint Unit: Architecture and Implementation", IBM J. Res. Develop., vol. 38, No. 5, Sep. 1994, pp. 525536. 
Hicks, T.N., et al., POWER2 Floating Point Unit: Architecture and Implementation , IBM J. Res. Develop., vol. 38, No. 5, Sep. 1994, pp. 525 536. * 
Hokenek et al., "LeadingZero Anticipator (LZA) in the IBM RISC System/6000 FloatingPoint Execution Unit," IBM J. Res. Develop., vol. 34, No. 1, Jan., 1990, pp. 7177. 
Hokenek et al., Leading Zero Anticipator (LZA) in the IBM RISC System/6000 Floating Point Execution Unit, IBM J. Res. Develop., vol. 34, No. 1, Jan., 1990, pp. 71 77. * 
Hokenek, et al., "SecondGeneration RISC Floating Point with MultiplyAdd Fused", IEEE Journal of SolidState Circuits, vol. 25, No. 5, Oct. 1990, pp. 12071213. 
Hokenek, et al., Second Generation RISC Floating Point with Multiply Add Fused , IEEE Journal of Solid State Circuits, vol. 25, No. 5, Oct. 1990, pp. 1207 1213. * 
IC Master 3. Advertisers Technical Data; LSI Logic Products and Services, Hearst Business Communications, Inc., IC Master, 1991, pp. 3529 2532. * 
Ide, et al., "A 320MFLOPS CMOS FloatingPoint Processing Unit for Superscalar Processors", IEEE Journal of SolidState Circuits, vol. 28, No. 3, Mar. 1993, pp. 352361. 
Ide, et al., A 320 MFLOPS CMOS Floating Point Processing Unit for Superscalar Processors , IEEE Journal of Solid State Circuits, vol. 28, No. 3, Mar. 1993, pp. 352 361. * 
IEEE Standard for Binary Floating Point Arithmetic, Institute of Electrical and Electronics Engineers, Inc., New York, Ny, ANSI/IEEE Std. 754, Nov. 1994, pp. 1 18. * 
Kahan, W.,et al., "A Proposed IEEECS Standard for Binary Floating Point Arithmetic", Proceedings of the Computer Science and Statistics: 12th Annual Symposium on the Interface, May 1011, 1979, University of Waterloo, Waterloo, Ontario, Canada, pp. 3236. 
Kahan, W.,et al., A Proposed IEEE CS Standard for Binary Floating Point Arithmetic , Proceedings of the Computer Science and Statistics: 12th Annual Symposium on the Interface, May 10 11, 1979, University of Waterloo, Waterloo, Ontario, Canada, pp. 32 36. * 
LSI Logic Databook and Design Manual, 5th Ed., HCMOS Macrocells, Macrofunctions, Oct. 1986, pp. 12 1 to 12 28. * 
LSI Logic Databook and Design Manual, 5th Ed., HCMOS Macrocells, Macrofunctions, Oct. 1986, pp. 121 to 1228. 
Montoye, et al., "Design of the IBM RISC System/6000 FloatingPoint Execution Unit, " IBM J. Res. Develop., vol. 34, No. 1, Jan., 1990, pp. 5970. 
Montoye, et al., Design of the IBM RISC System/6000 Floating Point Execution Unit, IBM J. Res. Develop., vol. 34, No. 1, Jan., 1990, pp. 59 70. * 
Omondi, A.R., "Computer Arithmetic Systems: Algorithms, Architecture and Implementation", 1994, pp. 7686. 
Omondi, A.R., Computer Arithmetic Systems: Algorithms, Architecture and Implementation , 1994, pp. 76 86. * 
Quach et al., "Leading One PredictionImplementation, Generalization, and Application, Technical Report: CSLTR91463," Computer Systems Laboratory, Stanford University, Mar. 1991, pp. 112. 
Quach et al., Leading One Prediction Implementation, Generalization, and Application, Technical Report: CSL TR 91 463, Computer Systems Laboratory, Stanford University, Mar. 1991, pp. 1 12. * 
Quach, et al., "An Improved Algorithm for HighSpeed FloatingPoint Addition", Stanford University Technical Report No. CSLTR90442, Aug. 1990, pp. 117. 
Quach, et al., An Improved Algorithm for High Speed Floating Point Addition , Stanford University Technical Report No. CSL TR 90 442, Aug. 1990, pp. 1 17. * 
The SPARC Architecture Manual, Version 8, (SPARC) International, Inc., Prentice Hall, Inc., New Jersey, 1992), pp. 1 316. * 
The SPARC Architecture Manual, Version 8, (SPARC) International, Inc., PrenticeHall, Inc., New Jersey, 1992), pp. 1316. 
Weste, Neil H.E., et al., "Principles of CMOS VLSI DesignA Systems Perspective" (AddisonWesley Publishing Co., 2nd Ed., 1993), p. 532. 
Weste, Neil H.E., et al., Principles of CMOS VLSI Design A Systems Perspective (Addison Wesley Publishing Co., 2nd Ed., 1993), p. 532. * 
Yu, R.K., et al., "167 Mhz Radix4 Floating Point Multiplier", Proceedings of the Twelfth Symposium on Computer Arithimetic (IEEE 1995), pp. 149154. 
Yu, R.K., et al., 167 Mhz Radix 4 Floating Point Multiplier , Proceedings of the Twelfth Symposium on Computer Arithimetic (IEEE 1995), pp. 149 154. * 
Cited By (61)
Publication number  Priority date  Publication date  Assignee  Title 

US6173299B1 (en) *  19970902  20010109  Intrinsity, Inc.  Method and apparatus for selecting an intermediate result for parallel normalization and rounding technique for floating point arithmetic operations 
US6185593B1 (en) *  19970902  20010206  Intrinsity, Inc.  Method and apparatus for parallel normalization and rounding technique for floating point arithmetic operations 
US20090249039A1 (en) *  19971009  20091001  Mips Technologies, Inc.  Providing Extended Precision in SIMD Vector Arithmetic Operations 
US8074058B2 (en) *  19971009  20111206  Mips Technologies, Inc.  Providing extended precision in SIMD vector arithmetic operations 
US6397239B2 (en) *  19980406  20020528  Advanced Micro Devices, Inc.  Floating point addition pipeline including extreme value, comparison and accumulate functions 
US6175847B1 (en) *  19980722  20010116  Intrinsity, Inc.  Shifting for parallel normalization and rounding technique for floating point arithmetic operations 
US6633896B1 (en) *  20000330  20031014  Intel Corporation  Method and system for multiplying large numbers 
US6629120B1 (en) *  20001109  20030930  Sun Microsystems, Inc.  Method and apparatus for performing a maskdriven interval multiplication operation 
US20020178199A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Floating point status information testing circuit 
US20020178197A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  System and method for generating an integer part of a logarithm of a floating point operand 
US20020178202A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Floating point multiplier for delimited operands 
US20020184283A1 (en) *  20010525  20021205  Sun Microsystems, Inc.  Floating point system with improved support of interval arithmetic 
US20020198918A1 (en) *  20010525  20021226  Steele Guy L.  Floating point unit for detecting and representing inexact computations without flags or traps 
US20020198917A1 (en) *  20010525  20021226  Sun Microsystems, Inc.  Floating point adder with embedded status information 
US20030005012A1 (en) *  20010525  20030102  Sun Microsystems, Inc.  System and method for forcing floating point status information to selected values 
US20030005013A1 (en) *  20010525  20030102  Sun Microsystems, Inc.  Floating point system that represents status flag information within a floating point operand 
US20030005014A1 (en) *  20010525  20030102  Sun Microsystems, Inc.  Floating point divider with embedded status information 
US20030009500A1 (en) *  20010525  20030109  Sun Microsystems, Inc.  Floating point remainder with embedded status information 
US20030014455A1 (en) *  20010525  20030116  Sun Microsystems, Inc.  Floating point multiplier with embedded status information 
US20030014454A1 (en) *  20010525  20030116  Sun Microsystems, Inc.  Floating point square root provider with embedded status information 
US20030041081A1 (en) *  20010525  20030227  Sun Microsystems, Inc.  System and method for performing floating point operations involving extended exponents 
US20030126173A1 (en) *  20010525  20030703  Sun Microsystems, Inc.  Total order comparator unit for comparing values of two floating point operands 
US20020178204A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Floating point status information accumulation circuit 
US20020178201A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  System and method for extracting the high part of a floating point operand 
US8799344B2 (en)  20010525  20140805  Oracle America, Inc.  Comparator unit for comparing values of floating point operands 
US8793294B2 (en)  20010525  20140729  Oracle America, Inc.  Circuit for selectively providing maximum or minimum of a pair of floating point operands 
US6961744B2 (en)  20010525  20051101  Sun Microsystems, Inc.  System and method for generating an integer part of a logarithm of a floating point operand 
US6970898B2 (en)  20010525  20051129  Sun Microsystems, Inc.  System and method for forcing floating point status information to selected values 
US6976050B2 (en)  20010525  20051213  Sun Microsystems, Inc.  System and method for extracting the high part of a floating point operand 
US8543631B2 (en)  20010525  20130924  Oracle America, Inc.  Total order comparator unit for comparing values of two floating point operands 
US7444367B2 (en)  20010525  20081028  Sun Microsystems, Inc.  Floating point status information accumulation circuit 
US7003540B2 (en)  20010525  20060221  Sun Microsystems, Inc.  Floating point multiplier for delimited operands 
US7016928B2 (en)  20010525  20060321  Sun Microsystems, Inc.  Floating point status information testing circuit 
US7069289B2 (en) *  20010525  20060627  Sun Microsystems, Inc.  Floating point unit for detecting and representing inexact computations without flags or traps 
US7069288B2 (en)  20010525  20060627  Sun Microsystems, Inc.  Floating point system with improved support of interval arithmetic 
US20060179104A1 (en) *  20010525  20060810  Steele Guy L Jr  Total order comparator unit for comparing values of two floating point operands 
US20020178200A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Circuit for selectively providing maximum or minimum of a pair of floating point operands 
US20060242215A1 (en) *  20010525  20061026  Sun Microsystems, Inc.  Circuit for selectively providing maximum or minimum of a pair of floating point operands 
US7133890B2 (en)  20010525  20061107  Sun Microsystems, Inc.  Total order comparator unit for comparing values of two floating point operands 
US7191202B2 (en)  20010525  20070313  Sun Microsystems, Inc.  Comparator unit for comparing values of floating point operands 
US7831652B2 (en)  20010525  20101109  Oracle America, Inc.  Floating point multiplier with embedded status information 
US7613762B2 (en)  20010525  20091103  Sun Microsystems, Inc.  Floating point remainder with embedded status information 
US7228324B2 (en)  20010525  20070605  Sun Microsystems, Inc.  Circuit for selectively providing maximum or minimum of a pair of floating point operands 
US20020178198A1 (en) *  20010525  20021128  Sun Microsystems, Inc.  Comparator unit for comparing values of floating point operands 
US7363337B2 (en)  20010525  20080422  Sun Microsystems, Inc.  Floating point divider with embedded status information 
US7366749B2 (en)  20010525  20080429  Sun Microsystems, Inc.  Floating point adder with embedded status information 
US6993549B2 (en)  20010525  20060131  Sun Microsystems, Inc.  System and method for performing gloating point operations involving extended exponents 
US7430576B2 (en)  20010525  20080930  Sun Microsystems, Inc.  Floating point square root provider with embedded status information 
US7395297B2 (en)  20010525  20080701  Sun Microsystems, Inc.  Floating point system that represents status flag information within a floating point operand 
US7236999B2 (en)  20021217  20070626  Sun Microsystems, Inc.  Methods and systems for computing the quotient of floatingpoint intervals 
US7219117B2 (en)  20021217  20070515  Sun Microsystems, Inc.  Methods and systems for computing floatingpoint intervals 
US20040117420A1 (en) *  20021217  20040617  Sun Microsystems, Inc.  Methods and systems for computing the quotient of floatingpoint intervals 
US20040117421A1 (en) *  20021217  20040617  Sun Microsystems, Inc.  Methods and systems for computing floatingpoint intervals 
US20060004990A1 (en) *  20040702  20060105  Seagate Technology Llc  Distributed processing in a multiple processing unit environment 
US7441106B2 (en)  20040702  20081021  Seagate Technology Llc  Distributed processing in a multiple processing unit environment 
US20060218380A1 (en) *  20050324  20060928  Stexar Corporation  Addshiftround instruction with dualuse source operand for DSP 
US7698353B2 (en)  20050914  20100413  Freescale Semiconductor, Inc.  Floating point normalization and denormalization 
US20070061391A1 (en) *  20050914  20070315  Dimitri Tan  Floating point normalization and denormalization 
US9092256B2 (en)  20121206  20150728  International Business Machines Corporation  Vector execution unit with prenormalization of denormal values 
US9092257B2 (en)  20121206  20150728  International Business Machines Corporation  Vector execution unit with prenormalization of denormal values 
US9817662B2 (en)  20151024  20171114  Alan A Jorgensen  Apparatus for calculating and retaining a bound on error during floating point operations and methods thereof 
Also Published As
Publication number  Publication date  Type 

US5844830A (en)  19981201  grant 
US6099158A (en)  20000808  grant 
Similar Documents
Publication  Publication Date  Title 

Li et al.  Implementation of single precision floating point square root on FPGAs  
US5448509A (en)  Efficient hardware handling of positive and negative overflow resulting from arithmetic operations  
US7509366B2 (en)  Multiplier array processing system with enhanced utilization at lower precision  
US5732007A (en)  Computer methods and apparatus for eliminating leading nonsignificant digits in floating point computations  
US5218564A (en)  Layout efficient 32bit shifter/register with 16bit interface  
US6349318B1 (en)  Arithmetic processor for finite field and module integer arithmetic operations  
US5058048A (en)  Normalizing pipelined floating point processing unit  
US5991785A (en)  Determining an extremum value and its index in an array using a dualaccumulation processor  
US5880983A (en)  Floating point split multiply/add system which has infinite precision  
US5042001A (en)  Method and apparatus for performing mathematical functions using polynomial approximation and a rectangular aspect ratio multiplier  
US5418736A (en)  Optimized binary adders and comparators for inputs having different widths  
US4484259A (en)  Fraction bus for use in a numeric data processor  
US4488252A (en)  Floating point addition architecture  
US4228520A (en)  High speed multiplier using carrysave/propagate pipeline with sparse carries  
US5153848A (en)  Floating point processor with internal freerunning clock  
US5325320A (en)  Area efficient multiplier for use in an integrated circuit  
US6687722B1 (en)  Highspeed/low power finite impulse response filter  
US3993891A (en)  High speed parallel digital adder employing conditional and lookahead approaches  
US5268855A (en)  Common format for encoding both single and double precision floating point numbers  
US6049865A (en)  Method and apparatus for implementing floating point projection instructions  
US5220525A (en)  Recoded iterative multiplier  
US6282554B1 (en)  Method and apparatus for floating point operations and format conversion operations  
US6631392B1 (en)  Method and apparatus for predicting floatingpoint exceptions  
US5631859A (en)  Floating point arithmetic unit having logic for quad precision arithmetic  
US5394351A (en)  Optimized binary adder and comparator having an implicit constant for an input 
Legal Events
Date  Code  Title  Description 

FPAY  Fee payment 
Year of fee payment: 4 

FPAY  Fee payment 
Year of fee payment: 8 

FPAY  Fee payment 
Year of fee payment: 12 