US5933757A - Etch process selective to cobalt silicide for formation of integrated circuit structures - Google Patents
Etch process selective to cobalt silicide for formation of integrated circuit structures Download PDFInfo
- Publication number
- US5933757A US5933757A US08/879,659 US87965997A US5933757A US 5933757 A US5933757 A US 5933757A US 87965997 A US87965997 A US 87965997A US 5933757 A US5933757 A US 5933757A
- Authority
- US
- United States
- Prior art keywords
- substrate
- cobalt
- titanium
- etchant mixture
- aqueous etchant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910017052 cobalt Inorganic materials 0.000 title claims abstract description 127
- 239000010941 cobalt Substances 0.000 title claims abstract description 127
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 title claims abstract description 127
- 229910021332 silicide Inorganic materials 0.000 title claims abstract description 75
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 title claims abstract description 75
- 238000000034 method Methods 0.000 title claims abstract description 32
- 230000015572 biosynthetic process Effects 0.000 title claims abstract description 20
- 239000000758 substrate Substances 0.000 claims abstract description 100
- 239000000203 mixture Substances 0.000 claims abstract description 74
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims abstract description 45
- 239000010936 titanium Substances 0.000 claims abstract description 45
- 229910052719 titanium Inorganic materials 0.000 claims abstract description 45
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims abstract description 41
- 238000005507 spraying Methods 0.000 claims abstract description 31
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 claims abstract description 30
- 239000007795 chemical reaction product Substances 0.000 claims abstract description 22
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims abstract description 20
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 claims abstract description 17
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 claims abstract description 16
- 229910017604 nitric acid Inorganic materials 0.000 claims abstract description 16
- VHUUQVKOLVNVRT-UHFFFAOYSA-N Ammonium hydroxide Chemical compound [NH4+].[OH-] VHUUQVKOLVNVRT-UHFFFAOYSA-N 0.000 claims abstract description 15
- 239000000908 ammonium hydroxide Substances 0.000 claims abstract description 15
- 239000004065 semiconductor Substances 0.000 claims abstract description 12
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims abstract description 10
- 229910003944 H3 PO4 Inorganic materials 0.000 claims abstract description 6
- 239000000463 material Substances 0.000 claims description 29
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims description 11
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- 239000008367 deionised water Substances 0.000 claims description 7
- 229910021641 deionized water Inorganic materials 0.000 claims description 7
- 230000009977 dual effect Effects 0.000 claims description 5
- 238000000137 annealing Methods 0.000 claims description 4
- 229910052751 metal Inorganic materials 0.000 description 9
- 239000002184 metal Substances 0.000 description 9
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 3
- 229920005591 polysilicon Polymers 0.000 description 3
- 229910021341 titanium silicide Inorganic materials 0.000 description 3
- 238000002149 energy-dispersive X-ray emission spectroscopy Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003749 cleanliness Effects 0.000 description 1
- 150000001869 cobalt compounds Chemical class 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- -1 e.g. Substances 0.000 description 1
- 230000001747 exhibiting effect Effects 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 238000000746 purification Methods 0.000 description 1
- 238000004064 recycling Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000007921 spray Substances 0.000 description 1
Images
Classifications
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
- C23F1/14—Aqueous compositions
- C23F1/16—Acidic compositions
- C23F1/26—Acidic compositions for etching refractory metals
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23F—NON-MECHANICAL REMOVAL OF METALLIC MATERIAL FROM SURFACE; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL; MULTI-STEP PROCESSES FOR SURFACE TREATMENT OF METALLIC MATERIAL INVOLVING AT LEAST ONE PROCESS PROVIDED FOR IN CLASS C23 AND AT LEAST ONE PROCESS COVERED BY SUBCLASS C21D OR C22F OR CLASS C25
- C23F1/00—Etching metallic material by chemical means
- C23F1/10—Etching compositions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
- H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
Definitions
- This invention relates to formation of integrated circuit structures. More particularly, this invention relates to an etch process for removal of materials remaining from the formation of cobalt silicide on an integrated circuit structure on a semiconductor substrate in preference to the removal of cobalt silicide.
- a metal silicide layer over the polysilicon gate electrode, and over the source/drain regions of the silicon substrate, to facilitate electrically and metallurgically connecting the silicon to metal interconnects.
- a metal layer capable of reacting with silicon to form a conductive metal silicide is usually blanket deposited over the polysilicon gate electrode and the source/drain regions of the silicon substrate, as well as over the silicon oxide insulation regions of the substrate, e.g., the field oxide regions. The structure is then heated sufficiently to cause the metal in contact with the silicon to react, thereby forming the desired metal silicide.
- cobalt silicide CoSi 2
- titanium silicide has been widely used in the past, as the dimensions of the integrated circuit structure have become smaller, the use of cobalt silicide (CoSi 2 ) is becoming preferred over titanium silicide because of certain problems encountered in the use of titanium silicide in the formation of narrow lines.
- cobalt does not reduce oxide as well as titanium, and thus the cleanliness of the semiconductor substrate is much more critical if cobalt is used to form the desired metal silicide.
- the use of such a dual capping structure to provide such a uniform thickness cobalt silicide layer is also desirable.
- the use of such a dual capping layer requires the removal of a number of different materials after the cobalt silicide layer is formed, including unreacted cobalt, titanium, and titanium nitride, as well as any other reaction products of cobalt other than the desired cobalt silicide layer.
- Such selective removal requires an etch system which is capable of removing all such materials while being highly selective to cobalt silicide, i.e., which will remove such materials as unreacted cobalt or other cobalt reaction products, as well as titanium and titanium nitride, without removing any substantial amount of cobalt silicide.
- an etch process capable of removing titanium and/or titanium nitride, unreacted cobalt, and cobalt reaction products other than cobalt silicide, after the formation of cobalt silicide on an integrated circuit structure on a semiconductor substrate comprises a first step of contacting the substrate with an aqueous mixture of ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) to selectively remove titanium and/or titanium nitride in preference to the removal of cobalt silicide, followed by a second step of contacting the substrate with an aqueous mixture of phosphoric acid (H 3 PO 4 ), acetic acid (CH 3 COOH), and nitric acid (HNO 3 ) to selectively remove cobalt and cobalt reaction products other than cobalt silicide in preference to the removal of cobalt silicide.
- the substrate is contacted by the respective etchant systems by spraying the respective aqueous mixtures onto
- the invention comprises a selective etch process for the removal of titanium and/or titanium nitride capping layers, as well as unreacted cobalt, and cobalt reaction products other than cobalt silicide, after the formation of cobalt silicide on an integrated circuit structure on a semiconductor substrate.
- the etch process comprises a first step of contacting the substrate with a first aqueous etchant mixture of ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) to selectively remove titanium and titanium nitride in preference to the removal of cobalt silicide, followed by a second step of contacting the substrate with a second aqueous etchant mixture of phosphoric acid (H 3 PO 4 ), acetic acid (CH 3 COOH), and nitric acid (HNO 3 ) to selectively remove cobalt and cobalt reaction products other than cobalt silicide in preference to the removal of cobalt silicide.
- the substrate is contacted by the respective etchant mixture by spraying the respective aqueous etchant mixtures onto the substrate rather than immersing the substrate into baths containing the respective aqueous mixtures.
- a layer of cobalt is formed over exposed silicon surfaces of an integrated circuit structure formed on a semiconductor substrate.
- one or more capping layers are formed over the cobalt layer to protect the cobalt layer during the initial annealing step, resulting in the formation of a cobalt silicide layer of more uniform thickness.
- Either a titanium capping layer or a titanium nitride capping layer may be utilized.
- a dual capping structure comprising a titanium layer and a tintaium nitride layer is utilized.
- the structure is then annealed at a first annealing temperature, which may range from about 425° C. to about 475° C., to form cobalt silicide.
- the titanium and/or titanium nitride capping layers are then removed, after the formation of the desired cobalt silicide on the integrated circuit structure on the semiconductor substrate, by contacting the substrate with a first aqueous etchant mixture of ammonium hydroxide (NH 4 OH) and hydrogen peroxide (H 2 O 2 ) for a period of from about 30 seconds to about 10 minutes, while maintaining the first etchant mixture at a temperature ranging from about 20° C. to about 60° C.
- the concentration of the NH 4 OH in the first etchant mixture ranges from about 60 vol. % to about 90 vol. %, while the concentration of the H 2 O 2 in the first etchant mixture ranges from about 10 vol. % to about 40 vol. %.
- the substrate is treated with the first etchant mixture by spraying the etchant mixture over the surface of the substrate.
- a spraying technique rather than the more conventional immersing of the substrate into a bath, ensures the continuous contact of the substrate with a fixed or constant concentration of the etchant mixture throughout the treatment time, since the titanium and titanium nitride materials being removed will wash off the substrate and not affect the further treatment of the substrate as would the presence of such removed materials in a bath which would tend to dilute the bath as such materials accumulated in the bath.
- the application of the etchant mixture to the substrate by spraying permits the collection (and discarding) of the initial runoff of the mixture of etchant mixture and materials removed by the first etchant mixture (which will have a high concentration of the materials removed by the first etchant mixture), followed by collection of the remaining first etchant mixture (containing dilute amounts of removed titanium and titanium nitride) for purification and subsequent recycling of the first etchant mixture.
- Apparatus which can be used in such a spraying process is available from the Semitool Company as a spray etch tool.
- the substrate is rinsed in water, e.g., deionized water, to remove the first etchant mixture as well as any remaining materials selectively etched from the substrate by the first etchant treatment.
- This rinse step may be carried out by spraying the substrate with water at room temperature for a period ranging from about 1 to about 3 minutes.
- the unreacted cobalt and cobalt reaction products are removed by treating the substrate with a second aqueous etchant mixture consisting of phosphoric acid, acetic acid, and nitric acid.
- a second aqueous etchant mixture consisting of phosphoric acid, acetic acid, and nitric acid. This treatment is carried out for a period of from about 30 seconds to about 30 minutes, while maintaining the second etchant mixture at a temperature ranging from about 20° C. to about 60° C.
- the concentration of the phosphoric acid in the second etchant mixture ranges from about 50 vol. % to about 80 vol. %
- the concentration of the acetic acid in the second etchant mixture ranges from about 1 vol.
- concentration of the nitric acid in the second etchant mixture ranges from about 1 vol. % to about 20 vol. %.
- Such an etchant mixture is commercially available from the Cyantek Corporation as an A1 etch called A1-30.
- the substrate is also treated with the second etchant mixture by spraying the second etchant mixture over the surface of the substrate.
- the substrate is again washed in water, such as deionized water, to remove the second etchant mixture as well as any other materials selectively etched from the substrate by the second etchant treatment.
- This rinse step may be carried out by spraying the substrate with water at a temperature of from about room temperature to about 80° C. for a period ranging from about 1 to about 3 minutes.
- a silicon substrate was covered with a 190 Angstrom thick cobalt layer in a vacuum apparatus.
- An 80 Angstrom thick titanium capping layer was then deposited over the cobalt layer in the same vacuum apparatus.
- the structure was then subject to a first anneal in an annealing chamber for about 60 seconds at about 450° C. to form the initial cobalt silicide.
- the titanium capping layer was then removed by spraying the substrate with the first etchant mixture (the aqueous ammonium hydroxide and hydrogen peroxide mixture) at room temperature for a period of about 4 minutes.
- the substrate was then rinsed by spraying with room temperature deionized water for about 3 minutes.
- the substrate was then sprayed with the second etchant mixture (the phosphoric acid, acetic acid, nitric acid mixture) at room temperature for a period of about 10 minutes to remove the unreacted cobalt, as well as cobalt reaction products other than the desired cobalt silicide.
- the substrate was then again rinsed by spraying with room temperature deionized water for about 3 minutes.
- the cobalt silicide was then further annealed by heating the substrate to a temperature of about 750° C. for a period of about 60 seconds to form the desired higher temperature cobalt silicide product.
- the sheet resistance of the resulting high temperature annealed cobalt silicide formed on the substrate was then measured and found to be 3 ⁇ / ⁇ , indicative of the complete removal of the titanium, unreacted cobalt, and undesired cobalt reaction products. This complete removal of these undesired materials was then further verified by EDS (energy dispersive spectroscopy). Similar results can be obtained using a titanium nitride capping layer or mutiple layers, consisting of a titanium capping layer and a titanium nitride capping layer.
- the invention provides a process for selective removal of the titanium and titanium nitride capping layers formed over a layer of cobalt to protect the cobalt layer from oxygen and other contaminants which would otherwise prevent formation of a cobalt silicide layer of uniform thickness; and for subsequent selective removal of the unreacted cobalt and undesired cobalt reaction products (i.e., the cobalt compounds formed during the anneal other than cobalt silicide).
- the etchant mixtures used in each of the two etch steps is highly selective to cobalt silicide, i.e., the titanium, titanium nitride, unreacted cobalt, and other cobalt reaction products are removed by the respective etchants, in preference to removal of the cobalt silicide.
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- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
Claims (19)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/879,659 US5933757A (en) | 1997-06-23 | 1997-06-23 | Etch process selective to cobalt silicide for formation of integrated circuit structures |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/879,659 US5933757A (en) | 1997-06-23 | 1997-06-23 | Etch process selective to cobalt silicide for formation of integrated circuit structures |
Publications (1)
Publication Number | Publication Date |
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US5933757A true US5933757A (en) | 1999-08-03 |
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US08/879,659 Expired - Lifetime US5933757A (en) | 1997-06-23 | 1997-06-23 | Etch process selective to cobalt silicide for formation of integrated circuit structures |
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Cited By (174)
Publication number | Priority date | Publication date | Assignee | Title |
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US6171959B1 (en) * | 1998-01-20 | 2001-01-09 | Motorola, Inc. | Method for making a semiconductor device |
JP2001148356A (en) * | 1999-10-07 | 2001-05-29 | Samsung Electronics Co Ltd | Manufacturing for semiconductor element with chamfered metallic silicide layer |
US6335294B1 (en) * | 1999-04-22 | 2002-01-01 | International Business Machines Corporation | Wet cleans for cobalt disilicide processing |
US6437411B1 (en) | 1999-03-29 | 2002-08-20 | Samsung Electronics Co., Ltd. | Semiconductor device having chamfered silicide layer and method for manufacturing the same |
US20030162392A1 (en) * | 2002-02-11 | 2003-08-28 | Applied Materials, Inc. | Method of annealing metal layers |
US20030189026A1 (en) * | 2002-04-03 | 2003-10-09 | Deenesh Padhi | Electroless deposition method |
US20030190426A1 (en) * | 2002-04-03 | 2003-10-09 | Deenesh Padhi | Electroless deposition method |
US20030190812A1 (en) * | 2002-04-03 | 2003-10-09 | Deenesh Padhi | Electroless deposition method |
US20040043624A1 (en) * | 2002-09-04 | 2004-03-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of high selectivity wet etching of salicides |
US20040087141A1 (en) * | 2002-10-30 | 2004-05-06 | Applied Materials, Inc. | Post rinse to improve selective deposition of electroless cobalt on copper for ULSI application |
US20040140291A1 (en) * | 2003-01-20 | 2004-07-22 | Swanson Eric D. | Copper etch |
KR100458119B1 (en) * | 2001-08-31 | 2004-11-20 | 동부전자 주식회사 | Method for manufacturing a silicide layer of semiconductor device |
US20050081785A1 (en) * | 2003-10-15 | 2005-04-21 | Applied Materials, Inc. | Apparatus for electroless deposition |
US20050260345A1 (en) * | 2003-10-06 | 2005-11-24 | Applied Materials, Inc. | Apparatus for electroless deposition of metals onto semiconductor substrates |
US20050260813A1 (en) * | 2003-11-14 | 2005-11-24 | Shea Kevin R | Reduced cell-to-cell shorting for memory arrays |
US20050263066A1 (en) * | 2004-01-26 | 2005-12-01 | Dmitry Lubomirsky | Apparatus for electroless deposition of metals onto semiconductor substrates |
US20060003570A1 (en) * | 2003-12-02 | 2006-01-05 | Arulkumar Shanmugasundram | Method and apparatus for electroless capping with vapor drying |
US7105458B1 (en) * | 2000-03-13 | 2006-09-12 | Oki Electric Industry Co., Ltd. | Method of etching semiconductor devices using a hydrogen peroxide-water mixture |
US20060276048A1 (en) * | 2005-06-07 | 2006-12-07 | Micron Technology, Inc. | Methods of etching nickel silicide and cobalt silicide and methods of forming conductive lines |
US20070111519A1 (en) * | 2003-10-15 | 2007-05-17 | Applied Materials, Inc. | Integrated electroless deposition system |
US20090004851A1 (en) * | 2007-06-29 | 2009-01-01 | Taiwan Semiconductor Manufacturing Co., Ltd. | Salicidation process using electroless plating to deposit metal and introduce dopant impurities |
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