US5912501A - Elimination of radius of curvature effects of p-n junction avalanche breakdown using slots - Google Patents
Elimination of radius of curvature effects of p-n junction avalanche breakdown using slots Download PDFInfo
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- US5912501A US5912501A US08/897,265 US89726597A US5912501A US 5912501 A US5912501 A US 5912501A US 89726597 A US89726597 A US 89726597A US 5912501 A US5912501 A US 5912501A
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- 230000000694 effects Effects 0.000 title description 8
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- 238000003379 elimination reaction Methods 0.000 title 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0642—Isolation within the component, i.e. internal isolation
- H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/1004—Base region of bipolar transistors
Definitions
- This invention relates generally to high voltage semiconductor devices. More particularly, this invention relates to high voltage bipolar semiconductor devices in which radius-of-curvature effects that limit pn-junction breakdown voltage are prevented.
- the bipolar transistor is an electronic device with two pn junctions in very close proximity. There are three device regions: an emitter region, a base region, and a collector region. The two pn junctions are known as the emitter-base (EB) junction and the collector-base (CB) junction. Modulation of the current in one pn junction by means of a change in the bias of the other nearby junction is called bipolar-transistor action. Because the mobility of minority carriers (electrons) in the base region of npn transistors is higher than that of holes in the base of pnp transistors, higher frequency operation and higher speed performances can be obtained with npn devices. For this reason, the following discussion will be in terms of npn transistors but it is to be understood that the discussion is applicable to pnp transistors as well.
- the desired device characteristics of bipolar transistors include: high current gain, high frequency ac operation, fast switching speed, high device-breakdown voltages, minimum device size (to achieve high functional density) and high reliability of device operation.
- the parasitic resistances of the transistor; R E , R B , and R C , and the parasitic junction capacitances; C EB , C CB , and C CB must be minimized.
- high-level injection effects for example, the Kirk effect should be avoided.
- the Early voltage must be high.
- the mechanism of avalanche breakdown in a pn junction limits the maximum reverse-bias voltages that can be applied to a pn junction and is also responsible for some of the maximum operating voltage values in bipolar transistors.
- the doping on the lightly doped side of the collector typically determines BV CBO .
- the pn junction is formed by diffusion into the silicon at openings in the surface SiO 2 layer. The impurities will diffuse downward through the opening and sideways under the edges of the SiO 2 layer.
- the pn junction has a plane region with nearly cylindrical edges and spherical corners.
- the rectangle, indicated at 1400, bounded by sides 1402, 1404, 1406, and 1408 represents the dimensions of the opening through which the impurities were diffused.
- the regions 1410 are regions in which the impurities have diffused sideways under the SiO 2 layer and the regions 1410 have a cylindrical shape.
- the regions 1412 are regions in which the impurities have diffused sideways at the corners of the rectangle under the SiO 2 layer and the regions 1412 have a spherical shape.
- Such junction curvatures enhance the electric field in the curved parts of the associated depletion regions. The enhanced electric field reduces the breakdown voltage below that predicted by the one-dimensional junction theory.
- the smaller radii of curvature are found in devices that have very shallow base regions and as can be seen from FIG. 15, as the radii of curvature becomes smaller the breakdown voltage becomes significantly smaller. This indicates that in the drive towards smaller and smaller devices the decrease in breakdown voltage becomes a very significant problem. For example, a comparison of the breakdown voltages for various devices with an impurity concentration N B of 10 15 shows the significant effects of increasing the curvature.
- the breakdown voltage for a device having a plane junction is approximately 320 V
- the breakdown voltage for a spherical junction with a radius of 10 microns is approximately 160 volts
- the breakdown voltage for a spherical junction with a radius of 0.1 microns is only approximately 9.5 V.
- the present invention is directed to a semiconductor device having a base region that terminates on the surface of a slot that surrounds the base region.
- the base region terminates substantially perpendicular to the surface of the slot.
- the collector-base junction of the semiconductor device has substantially no spherical or cylindrical surface.
- the base region and the surrounding slot are formed in an epitaxial region of the semiconductor device.
- the semiconductor device has a buried layer formed on a portion of the interface between the epitaxial region and a substrate region.
- the epitaxial region is surrounded by isolation structures that extend from the surface of the device to the interface between the epitaxial region and the substrate region.
- FIGS. 1-4 show selected initial steps in the manufacture of a semiconductor device.
- FIGS. 5-8 show selected continuing steps in the manufacture of the semiconductor device shown in FIGS. 1-4 to obtain a prior art semiconductor device.
- FIGS. 9-12 show selected continuing steps in the manufacture of the semiconductor device shown in FIGS. 1-4 to obtain a semiconductor device in accordance with the present invention.
- FIG. 13 shows a top view showing the structure of a semiconductor device in accordance with the present invention.
- FIG. 14 shows a perspective view of the shape of a base region diffused through a rectangular opening.
- FIG. 15 is a graphical representation of the breakdown voltage versus impurity concentration for different radii of curvature of the junctions between the base and collector regions.
- FIGS. 1-4 show selected initial steps in the manufacture of a standard-buried-collector (SBC) npn semiconductor device.
- SBC standard-buried-collector
- FIGS. 5-8 show selected continuing steps in the manufacture of the semiconductor device shown in FIGS. 1-4 in which a semiconductor device as known in the prior art is formed.
- FIGS. 9-12 show selected continuing steps in the manufacture of the semiconductor device shown in FIGS. 1-4 in which a semiconductor device in accordance with the present invention is formed.
- the vertical dimension is somewhat larger so that the junctions and film thicknesses are actually smaller than they appear in the figures in relation to the horizontal dimension of the various elements.
- FIG. 1 shows a lightly p-type doped silicon substrate 100 with an oxide layer 102 that has been formed on the surface of the substrate 100 and etched to expose a portion of the surface 104 of the substrate 100.
- the oxide layer 102 is typically formed by exposing the surface of the substrate 100 to a wet oxidation atmosphere and a high temperature cycle.
- the substrate doping is selected to be light enough to minimize the parasitic collector-to-substrate depletion-layer capacitance, but heavy enough to prevent it from being changed to n-type during subsequent processing.
- FIG. 2 shows the portion of the substrate 100 shown in FIG. 1 with a layer 200 formed in the portion of the surface 104 defined by the oxide layer 102 shown in FIG. 1 in which a window has been etched.
- the layer 200 is formed by heavy n+ type diffusion or ion implantation and will become a buried layer during further processing.
- the buried layer is also called a subcollector.
- the surface 104 of the substrate 100 is exposed to an appropriate atmosphere containing the selected dopant ions or ion implantation at approximately 30 keV and approximately 10 15 atoms/cm 2 .
- dopants with relatively small diffusion constants such as arsenic and antimony are used to form the layer 200.
- the highly doped layer 200 provides a low resistance path from the active part of the transistor, to be discussed later, to the collector contact, which will also be discussed later.
- the oxide layer 102 is removed exposing the surface 201 of the substrate 100.
- An anneal/drive-in procedure is performed in an oxidizing ambient that causes a new oxide to be formed on the wafer surface.
- a step of approximately 100-200 nm remains in the substrate 100 at the edges of the layer 200.
- the step is indicated at 202 and 204 and is formed because of the unequal thicknesses of the oxides that have grown on the respective underlying materials.
- the steps propagate through the epitaxial layer and become the alignment marks that allow subsequent mask levels to be aligned with the buried layer.
- FIG. 3 shows an epitaxial layer 300 grown on the surface of the entire wafer, including the surface 201 of the substrate 100 and the surface of the layer 200.
- the epitaxial layer 300 is a lightly doped n-type layer and under proper conditions the epitaxial layer 300 is a single-crystal layer that continues the crystal structure of the original substrate. This makes the epitaxial layer 300 suitable for the fabrication of devices.
- the dopant typically used to form the lightly doped (approximately 10 15 -10 16 atoms/cm 3 ) n-type epitaxial layer is arsenic because of its small diffusivity.
- the minimum thickness and maximum doping concentration of the epitaxial layer are determined by the avalanche breakdown and reach through limitations on the value of BV CEO .
- the steps indicated at 202, 204 are shown replicated on the surface of the epitaxial layer 300.
- the presence of the steps 202 and 204 allows subsequent mask levels to be aligned to the layer 200, which is now buried.
- the buried layer 200 becomes larger because of diffusion of the dopants used to form the buried layer 200.
- dopants with a low diffusion rate are typically used to minimize the subsequent growth of the buried layer 200.
- FIG. 4 shows two isolation structures 400 and 402 formed in the epitaxial layer 300.
- the isolation structures are formed by growing an oxide layer 406 on the surface of the epitaxial layer 300 and opening windows, indicated at 408 and 410 in the oxide layer 406 at locations where isolation structures are to be formed. A deep p+ type diffusion process, typically using boron, is then performed.
- the purpose of the isolation structures is to isolate the collectors of the transistors from one another with reverse-biased pn junctions.
- the acceptor concentration in the isolation regions must be higher than the donor concentration in the epitaxial layer, and the junction depth (the depth of the isolation structures) must be at least equal to the depth of the epitaxial layer in order for complete isolation to be achieved. As shown in FIG.
- p+ isolation structures 400 and 402 are formed. Initially, the p+ isolation structures 400 and 402 do not extend to the substrate layer 100. However, subsequent high-temperature processes will cause the p + isolation diffusion making up the isolation structures 400 and 402 to reach as far as the original substrate surface 201 as shown in FIG. 5. It is customary to "overdrive" the isolation diffusion beyond the depth of the epitaxial layer to prevent the possibility that the depletion region could extend beneath the isolation diffusion. Once the p+ isolation diffusion reaches or extends beyond the original substrate layer, there will be an n-type island completely surrounded by p+ type material. This can be clearly seen in FIG. 5. It should be appreciated by one of ordinary skill in the art, that the figures show a cross-section of the device and the structures are all three-dimensional. For example, it should be appreciated that the isolation structures indicated at 400 and 402 surround the region 500 of the device shown in FIG. 5.
- FIG. 5 shows the device shown in FIG. 4 with the oxide layer 406 removed and a new oxide layer 502 formed on the device.
- a base diffusion mask is used to open a window 504 in the oxide and a p-type diffusion process is performed to form the base region 506 of the transistor.
- the formation of the base region is one of the most critical processes in bipolar transistor fabrication.
- the base must be aligned so that the collector-base and collector-substrate depletion regions do not merge, following diffusion at the surface.
- the minimum allowable spacing between the isolation regions and the base region is determinable from knowledge of the applied voltages and the epitaxial-layer doping concentration.
- the width of the window 504 is limited by the theoretically predicted width of the sideways depletion region that is associated with the collector-base junction 508 and will be discussed in conjunction with FIG. 6.
- the collector-base junction 508 does not reach as far as the buried layer 200.
- the region 501 between the base region 506 and the buried layer 200 remains lightly doped, which gives more ideal characteristics for the transistor and also provides a higher breakdown voltage.
- FIG. 6 shows the device shown in FIG. 5 with an oxide layer 600 formed on the surface of the device.
- a window at 602 is opened in the oxide layer 600 for an emitter diffusion process and a window at 604 is opened at the same time in the oxide layer 600 for a collector diffusion process.
- the combined emitter and collector diffusion process is a shallow, high-concentration n-type diffusion and is performed in an oxidizing ambient so that oxide covers the entire wafer after the diffusion is completed.
- the emitter diffusion and collector diffusion process shown in FIG. 6 are done in separate diffusion processes.
- the collector region 608 is to extend to the buried layer 200 it may be necessary to have the emitter diffusion process separate from the emitter diffusion process so that the emitter diffusion does not diffuse too deeply into the base region 506.
- the deep diffusion of the collector region also called a plug or sinker
- the collector contact is typically formed by means of a diffusion process.
- an ion implantation process could be used. Phosphorus is chosen for this application since it is a faster-diffusing impurity than arsenic.
- an additional mask must be used to allow the dopant to be selectively introduced only into the collector region.
- the emitter diffusion process forms the emitter region 606 and the collector diffusion process forms the collector region 608.
- FIG. 7 shows the device shown in FIG. 6, after the contact mask has been used to open windows in the oxide layer 700.
- the windows 702, 704, and 706 are for the purpose of allowing electrical contacts to be made to the emitter region 606, the base region 506 and the collector region 608.
- FIG. 8 shows the device shown in FIG. 7, with an electrical contact 800 to the emitter region 606, an electrical contact 802 to the base region 506, and an electrical contact 804 to the collector region 608.
- FIG. 9 shows the device shown in FIG. 4 with a slot having a selected depth formed in the region 500 with a first portion of the slot indicated at 900 and a second portion of the slot indicated at 902.
- the depth of the slot is selected so that it will extend beyond the base region formed in a prior or a subsequent process.
- the slot can be formed either before or after the base region 904 is formed.
- the slot surrounds the base region 904 and therefore the portion 900 and the portion 902 are portions of the same slot.
- One method of forming the slot is to provide a protection layer consisting of a layer of thermal oxide, a deposited layer of silicon nitride, and a deposited layer of oxide.
- a layer of photoresist is deposited and a photoresist mask patterns the photoresist and a reactive ion etch (RIE) with chemistry etches through the protection layer, the oxide and nitride to the photoresist.
- the photoresist is removed and reactive ion etching with chemistry is used to etch the silicon slot.
- a liner material 906 is formed on the walls of the slot. The liner material depends upon the slot material and could be thermal oxide or silicon nitride.
- the slot is filled with a material such as polysilicon or tungsten.
- the slot material is planarized using a chemical mechanical planarization process. Any well-known method of making slots in a silicon device can be used to form the slots.
- FIG. 9 shows the device shown in FIG.
- a base diffusion mask is used to open a window 910 in the oxide layer 908 and a p-type diffusion process is performed to form the base region 904 of the transistor.
- the p-type diffusion process to form the base region 904 is controlled to ensure that the base region boundary 912 does not extend beyond the selected depth of the slot portions indicated at 900 and 902.
- the base region 904 does not reach as far as the buried layer 200.
- the region 501 between the base region 904 and the buried layer 200 remains lightly doped, which provides a device with more ideal characteristics for the transistor and also provides a higher breakdown voltage.
- the base diffusion process performed within the slot portions 900 and 902 provides a collector-base junction 912 that is substantially completely planar; that is, with substantially no spherical or cylindrical curvature such as in the prior art devices.
- FIG. 10 shows the device shown in FIG. 9 with an oxide layer 1000 formed on the surface of the device.
- a window at 1002 is opened in the oxide layer 1000 for an emitter diffusion process and a window at 1004 is opened at the same time in the oxide layer 1000 for a collector diffusion process.
- the combined emitter and collector diffusion process is a shallow, high-concentration n-type diffusion and is performed in an oxidizing ambient so that oxide covers the entire wafer after the diffusion is completed.
- the emitter diffusion and collector diffusion process shown in FIG. 10 are done in separate diffusion processes.
- the collector region 1008 is to extend to the buried layer 200 it may be necessary to have the emitter diffusion process separate from the emitter diffusion process so that the emitter diffusion does not diffuse too deeply into the base region 904.
- the deep diffusion of the collector region is necessary in some applications because the value of the R C (the resistance of the collector to base path) is too high if a deep diffusion is not done.
- the deep diffusion of the collector is also called a plug or sinker.
- the collector contact is typically formed by means of a diffusion process. In other types of devices, an ion implantation process could be used. Phosphorus is chosen for this application since it is a faster-diffusing impurity than arsenic. As can be appreciated, an additional mask must be used to allow the dopant to be selectively introduced only into the collector region.
- the emitter diffusion process forms the emitter region 1008 and the collector diffusion process forms the collector region 1006.
- FIG. 11 shows the device shown in FIG. 10, after the contact mask has been used to open windows in the oxide layer 1100 that was formed on the surface of the device.
- the windows 1102, 1104, and 1106 are for the purpose of allowing electrical contacts to be made to the emitter region, the base region and the collector region.
- FIG. 12 shows the device shown in FIG. 11 with an electrical contact 1200 to the emitter region 1008, an electrical contact 1202 to the base region 904, and an electrical contact 1204 to the collector region 1006.
- FIG. 13 is a top view of a portion of a semiconductor device 1300 fabricated in accordance with the present invention.
- An emitter region 1302 is shown in a base region 1304 and the base region 1304 is shown surrounded by a slot 1306.
- FIG. 14 shows the shape of a base region that has been diffused through a rectangular opening in the SiO 2 layer.
- the rectangle, indicated at 1400, bounded by sides 1402, 1404, 1406, and 1408 represents the shape of the opening through which the impurities were diffused.
- the regions 1410 are regions in which the impurities have diffused sideways under the SiO 2 layer and the regions 1410 have a cylindrical shape.
- the regions 1412 are regions in which the impurities have diffused under the corners under the SiO 2 layer and the regions 1412 have a spherical shape.
- Such junction curvatures enhance the electric field in the curved parts of the associated depletion regions that reduces the breakdown voltage below that predicted by one-dimensional junction theory.
- FIG. 15 shows the effects of the curvature of the collector-base junction on breakdown voltage.
- the smaller radii of curvature are found in devices that have very shallow base regions and as can be seen from FIG. 15, as the radii of curvature becomes smaller the breakdown voltage becomes significantly smaller. This indicates that in the drive towards smaller and smaller devices the decrease in breakdown voltage becomes a very significant problem.
- a comparison of the breakdown voltages for various devices with an impurity concentration N B of 10 15 shows the significant effects of increasing the curvature.
- the breakdown voltage for a device having a plane junction is approximately 320 V.
- the breakdown voltage for a spherical junction with a radius of 10 microns is approximately 160 volts and the breakdown voltage for a spherical junction with a radius of 0.1 microns is only approximately 9.5 V.
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Abstract
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US08/897,265 US5912501A (en) | 1997-07-18 | 1997-07-18 | Elimination of radius of curvature effects of p-n junction avalanche breakdown using slots |
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Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6011297A (en) * | 1997-07-18 | 2000-01-04 | Advanced Micro Devices,Inc. | Use of multiple slots surrounding base region of a bipolar junction transistor to increase cumulative breakdown voltage |
US20080210980A1 (en) * | 2002-08-14 | 2008-09-04 | Advanced Analogic Technologies, Inc. | Isolated CMOS transistors |
US20090280616A1 (en) * | 2004-01-15 | 2009-11-12 | Infineon Technologies Ag | Integrated transistor, particularly for voltages and method for the production thereof |
US9257504B2 (en) | 2002-09-29 | 2016-02-09 | Advanced Analogic Technologies Incorporated | Isolation structures for semiconductor devices |
CN108133959A (en) * | 2017-12-25 | 2018-06-08 | 深圳市晶特智造科技有限公司 | Groove triode and preparation method thereof |
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US9905640B2 (en) | 2002-09-29 | 2018-02-27 | Skyworks Solutions (Hong Kong) Limited | Isolation structures for semiconductor devices including trenches containing conductive material |
US9257504B2 (en) | 2002-09-29 | 2016-02-09 | Advanced Analogic Technologies Incorporated | Isolation structures for semiconductor devices |
US10074716B2 (en) | 2002-09-29 | 2018-09-11 | Skyworks Solutions (Hong Kong) Limited | Saucer-shaped isolation structures for semiconductor devices |
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US8021952B2 (en) | 2004-01-15 | 2011-09-20 | Infineon Technologies Ag | Integrated transistor, particularly for voltages and method for the production thereof |
US20100330765A1 (en) * | 2004-01-15 | 2010-12-30 | Infineon Technologies Ag | Integrated transistor, particularly for voltages and method for the production thereof |
US8129249B2 (en) | 2004-01-15 | 2012-03-06 | Infineon Technologies Ag | Integrated transistor, particularly for voltages and method for the production thereof |
US20090280616A1 (en) * | 2004-01-15 | 2009-11-12 | Infineon Technologies Ag | Integrated transistor, particularly for voltages and method for the production thereof |
CN108133959A (en) * | 2017-12-25 | 2018-06-08 | 深圳市晶特智造科技有限公司 | Groove triode and preparation method thereof |
CN108133959B (en) * | 2017-12-25 | 2020-12-15 | 浙江昌新生物纤维股份有限公司 | Groove triode and manufacturing method thereof |
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