US5902717A - Method of fabricating semiconductor device using half-tone phase shift mask - Google Patents

Method of fabricating semiconductor device using half-tone phase shift mask Download PDF

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Publication number
US5902717A
US5902717A US08/797,340 US79734097A US5902717A US 5902717 A US5902717 A US 5902717A US 79734097 A US79734097 A US 79734097A US 5902717 A US5902717 A US 5902717A
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United States
Prior art keywords
hole
conductive film
semiconductor device
film
forming
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Expired - Lifetime
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US08/797,340
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English (en)
Inventor
Tsutomu Hayakawa
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Longitude Semiconductor SARL
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NEC Corp
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Assigned to NEC ELECTRONICS CORPORATION reassignment NEC ELECTRONICS CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION
Assigned to ELPIDA MEMORY, INC. reassignment ELPIDA MEMORY, INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: NEC CORPORATION, NEC ELECTRONICS CORPORATION
Assigned to ELPIDA MEMORY INC. reassignment ELPIDA MEMORY INC. SECURITY AGREEMENT Assignors: PS4 LUXCO S.A.R.L.
Assigned to PS4 LUXCO S.A.R.L. reassignment PS4 LUXCO S.A.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ELPIDA MEMORY, INC.
Assigned to LONGITUDE SEMICONDUCTOR S.A.R.L. reassignment LONGITUDE SEMICONDUCTOR S.A.R.L. CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: PS5 LUXCO S.A.R.L.
Assigned to PS5 LUXCO S.A.R.L. reassignment PS5 LUXCO S.A.R.L. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: PS4 LUXCO S.A.R.L.
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/946—Step and repeat

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device using a half-tone phase shift mask.
  • the half-tone phase shift method is a lithography method using mask patterns that are formed by a semitransparent film having a light transmittivity of 1-16% and an optical phase difference of within 180 ⁇ 10° with respect to an optically transmitting portion.
  • a sharp image intensity is produced at an edge portion due to an optical phase inversion effect that develops at the mask pattern edge portion, thus enabling to enhance the resolution.
  • a region irradiated by one exposure is set so as to cover at least one chip region, and a repeat margin of a predetermined dimension is provided therein so that there occurs no gap between shots caused by misalignment between individual steps.
  • shots a region irradiated by one exposure
  • the edge of a shot A comes on a scribe region which defines chip regions on the wafer, but this edge extends outwardly by the extent of the repeat margin 102 (for example, 2 ⁇ m) from the center lines 101-1, 101-2 of the scribe region.
  • overlap exposure portions portions of a plurality of shots
  • problems in the case of a half-tone phase shift method which are explained below.
  • the half-tone phase shift mask is often used in the formation of a contact hole.
  • a photoresist film 3 is formed, and a hole 4 for the formation of the contact hole is provided in a chip region I by a step exposure and development using the half-tone phase shift mask.
  • the numeral III represents the center line position of the scribe region.
  • a hole 5 is often unavoidably formed also at a four-fold exposure portion (103 in FIG. 1). This is because the exposure is made four times by the light transmitted through the semitransparent film of the half-tone phase shift mask.
  • the photoresist film 9 As a mask, the Al-Si-Cu alloy film 8 is patterned and the interconnect layer 8a is formed. At that time, the residue 10 of Al-Si-Cu tends to be present at sidewalls of the hole 7.
  • An object of the present invention is to overcome the problems existing in the prior art, and to provide a method of fabricating with which it is possible to prevent the occurrence of contaminants when a contact hole is formed using a half-tone phase shift mask.
  • the patterning step may include an exposure process using a transmission type mask.
  • the conductive films remained at the four-fold exposure portion are made progressively larger in size with each being made larger than an underlying one.
  • the conductive film pattern is left at the second hole and its peripheral portion, the residue which is otherwise present at the sidewalls of the second hole and which peels off during the cleaning step is not present.
  • the conductive film is deposited on the insulating film and the conductive film is patterned such that this conductive film remains at the second hole, which results in being formed on the insulating film at the four-fold exposure portion, and at its peripheral portion.
  • the conductive film is deposited on the insulating film and the conductive film is patterned such that this conductive film remains at the second hole, which results in being formed on the insulating film at the four-fold exposure portion, and at its peripheral portion.
  • FIG. 1 is a plan view for showing an overlap exposure portion which develops when the step exposure using a half-tone phase shift mask is carried out;
  • FIGS. 2A, 2B and 2C are sectional views of a part of a semiconductor device, for use in explaining steps of a conventional method of fabricating the semiconductor device;
  • FIGS. 3A-3G are sectional views of a part of a semiconductor device fabricated by a method according to the invention, for use in explaining steps of the method according to the invention;
  • FIG. 4 is a plan view of a part of the semiconductor device fabricated by the method according to the invention, for use in explaining an embodiment according to the invention
  • FIG. 5 is a graph showing the number of contaminants on a lot to lot basis.
  • FIG. 6 is a graph showing the yield on a lot to lot basis.
  • FIG. 3A shows that a silicon oxide film (an interlayer insulating film 2) having a thickness of 500 nm is formed after the formation of a field oxide film, a gate insulating film, a gate electrode and a source/drain region (all not shown) on a surface of a P-type silicon substrate 1 and, thereafter, a photoresist film 3 is formed for the formation of a contact hole which reaches, for example, the source/drain region.
  • a hole 4 for the formation of the contact hole is formed but, at the same time, a hole 5 results in being formed at a four-fold exposure portion on a scribe region II. This aspect is the same as that already explained with respect to the prior art.
  • the interlayer insulating film 2 is etched using the photoresist film 3 as a mask and a contact hole 6 (first hole) is formed as shown in FIG. 3B, but a second hole 7 is also unavoidably formed at the four-fold exposure portion.
  • a conductive film such as Al-Si-Cu film 8
  • a photoresist film 9A for the formation of an interconnect layer is formed.
  • the photoresist film 9A is also formed in the hole 7 and on its peripheral portion.
  • the exposure mask used for this purpose is a commonly used mask (hereinafter referred to as a "transmission type mask") which has been in use since before the phase shift mask was proposed.
  • a shielding film may be provided at each corner thereof so that the four-fold exposure portion 103 (a 4 ⁇ m ⁇ 4 ⁇ m region when the repeat margin 102 is 2 ⁇ m) at, for example, a shot A is shielded so that a square region 104 of, for example, 6 ⁇ m ⁇ 6 ⁇ m is not irradiated by the exposure light.
  • a positive type photoresist and a negative type photo mask are examples of a positive type photoresist and a negative type photo mask.
  • the Al-Si-Cu alloy film 8 is anisotropically etched using the photoresist film 9A as a mask and, as shown in FIG. 3C, an interconnect layer 8a and a conductive film pattern 8b are formed. Then, in the case of a single-layer interconnect semiconductor device, in the interlayer insulating film 2 on the scribe region II, the portions that are not covered by the conductive film pattern 8b are removed. In the case of a multi-layer interconnect semiconductor device, as shown in FIG.
  • a silicon oxide film (interlayer insulating film 11) having a thickness of 400 nm is deposited, and a photoresist film 12 having a hole 13 for the formation of a contact hole on the interconnect layer 8a is formed using a half-tone phase shift mask.
  • a hole 14 is also formed above the conductive film pattern 8b.
  • the interlayer insulating film 11 is etched away using the photoresist film 12 as a mask and, as shown in FIG. 3E, holes 15 and 16 are formed.
  • a conductive film such as an Al-Cu-Si alloy film 17, is formed, and a photoresist film 18 for the formation of an upper interconnect layer is formed by using a transmission type mask.
  • the photoresist film 18 is formed such that it remains in the hole 16 and on its peripheral portion so as to cover steps of the interlayer insulating film 11 that develop at an edge portion of the conductive film pattern 8b.
  • the Al-Si-Cu alloy film 17 is anisotropically etched and, as shown in FIG. 3F, an interconnect 17a and a conductive film pattern 17b are formed.
  • the size of the conductive film pattern 17b is the same extent as that of the conductive film pattern 8b, this allows the residue of Al-Si-Cu alloy to be present on the sidewalls of the steps 19.
  • the size of the conductive film pattern 17 bis set larger, for example, to about 8 ⁇ m ⁇ 8 ⁇ m.
  • the interlayer insulating films 2 and 11 of the scribe region II are removed in the subsequent step as shown in FIG. 3G.
  • the scribe region II there remain laminates of the interlayer insulating film and the conductive film pattern but, since the area occupied thereby is small as compared to the size of the scribe region (for example, 100 ⁇ m in width), there is almost no effect on the lowering of the yield caused by the scattering of conductive matter during the scribing process.
  • the same procedure may be repeated.
  • the sizes of the conductive film patterns to be left at the four-fold exposure portion may be made sequentially larger towards an upper layer.
  • FIGS. 5 and 6 respectively show the comparison between the number of contaminants and the yield per wafer (260 chips) in a semiconductor device of the embodiment according to the invention (a double-layer interconnect semiconductor device) and those in the prior art semiconductor device.
  • the number of contaminants was counted using an automatic external appearance inspection system which is used in such testing as for pattern defects in masks. This system is capable of measuring a contaminant whose magnitude is on the order of at least 0.5 ⁇ m. It has been confirmed that the number of contaminants has been reduced from 50-70 to below 10, the yield has been enhanced by several percent, and variations among lots have been reduced.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Preparing Plates And Mask In Photomechanical Process (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Dicing (AREA)
US08/797,340 1996-02-28 1997-02-10 Method of fabricating semiconductor device using half-tone phase shift mask Expired - Lifetime US5902717A (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4104396A JP2728078B2 (ja) 1996-02-28 1996-02-28 半導体装置の製造方法
JP8-041043 1996-02-28

Publications (1)

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US5902717A true US5902717A (en) 1999-05-11

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US (1) US5902717A (ja)
JP (1) JP2728078B2 (ja)
KR (1) KR100222805B1 (ja)
TW (1) TW401600B (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645856B2 (en) * 2001-08-17 2003-11-11 Hitachi, Ltd. Method for manufacturing a semiconductor device using half-tone phase-shift mask to transfer a pattern onto a substrate
US20070013034A1 (en) * 2005-07-12 2007-01-18 Dongbu Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
US20100255409A1 (en) * 2009-04-01 2010-10-07 Man-Kyu Kang Attenuated phase-shift photomasks, method of fabricating the same and method of fabricating semiconductor using the same
US20110233625A1 (en) * 2010-03-23 2011-09-29 Elpida Memory, Inc. Semiconductor device and method for manufacturing the same
US20160109794A1 (en) * 2014-10-20 2016-04-21 Il-yong Jang Photomask and method of forming the same and methods of manufacturing electronic device and display device using the photomask

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4529099B2 (ja) * 2008-11-07 2010-08-25 ルネサスエレクトロニクス株式会社 レチクル、露光方法および半導体装置の製造方法

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05197160A (ja) * 1992-01-20 1993-08-06 Toshiba Corp パターン形成方法
US5451537A (en) * 1994-08-12 1995-09-19 Industrial Technology Research Institute Method of forming a DRAM stack capacitor with ladder storage node
US5700606A (en) * 1995-05-31 1997-12-23 Sharp Kabushiki Kaisha Photomask and a manufacturing method thereof

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05197160A (ja) * 1992-01-20 1993-08-06 Toshiba Corp パターン形成方法
US5451537A (en) * 1994-08-12 1995-09-19 Industrial Technology Research Institute Method of forming a DRAM stack capacitor with ladder storage node
US5700606A (en) * 1995-05-31 1997-12-23 Sharp Kabushiki Kaisha Photomask and a manufacturing method thereof

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6645856B2 (en) * 2001-08-17 2003-11-11 Hitachi, Ltd. Method for manufacturing a semiconductor device using half-tone phase-shift mask to transfer a pattern onto a substrate
US20070013034A1 (en) * 2005-07-12 2007-01-18 Dongbu Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
US7439161B2 (en) * 2005-07-12 2008-10-21 Dongbu Electronics Co., Ltd. Semiconductor device and method for manufacturing the same
US20090026585A1 (en) * 2005-07-12 2009-01-29 Dongbu Electronics Co. Ltd., Semiconductor Device and Method for Manufacturing the same
US20100255409A1 (en) * 2009-04-01 2010-10-07 Man-Kyu Kang Attenuated phase-shift photomasks, method of fabricating the same and method of fabricating semiconductor using the same
US20110233625A1 (en) * 2010-03-23 2011-09-29 Elpida Memory, Inc. Semiconductor device and method for manufacturing the same
US20160109794A1 (en) * 2014-10-20 2016-04-21 Il-yong Jang Photomask and method of forming the same and methods of manufacturing electronic device and display device using the photomask
US9989857B2 (en) * 2014-10-20 2018-06-05 Samsung Electronics Co., Ltd. Photomask and method of forming the same and methods of manufacturing electronic device and display device using the photomask
US10474034B2 (en) 2014-10-20 2019-11-12 Samsung Electronics Co., Ltd. Phase shift mask

Also Published As

Publication number Publication date
KR100222805B1 (ko) 1999-10-01
TW401600B (en) 2000-08-11
JPH09232315A (ja) 1997-09-05
JP2728078B2 (ja) 1998-03-18
KR970063431A (ko) 1997-09-12

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