US5883004A - Method of planarization using interlayer dielectric - Google Patents
Method of planarization using interlayer dielectric Download PDFInfo
- Publication number
- US5883004A US5883004A US08/920,172 US92017297A US5883004A US 5883004 A US5883004 A US 5883004A US 92017297 A US92017297 A US 92017297A US 5883004 A US5883004 A US 5883004A
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- US
- United States
- Prior art keywords
- layer
- buffer
- buffer layer
- dielectric
- barrier layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
Definitions
- the present invention relates to a planarization method, and particularly to a method of planarization using interlayer dielectric and a buffer layer.
- FIG. 1 shows a cross-sectional view illustrative of a conventional planarization method using a borophosilicate glass (BPSG) layer 10 as interlayer dielectric (ILD), which serves as an interlayer between metal layers and the underlying transistors.
- BPSG borophosilicate glass
- ILD interlayer dielectric
- This barrier layer 8 is used to block autodoping of Bs or Ps from the BPSG layer 10 above.
- Dashed line 12 denotes the surface after the initially deposited BPSG layer 10 is reflowed.
- a chemical-mechanical polishing (CMP) method is then utilized to achieve a global planarization over the substrate 6.
- CMP chemical-mechanical polishing
- the polishing rate using the CMP over the BPSG layer 10 varies greatly according to nonuniform concentration distribution of Bs or Ps. More specifically, the polishing rate over the region having low concentration becomes large, and vice versa. Therefore, a nonplanar surface 14 is thus produced, thereby degrading the following metallization process.
- a method for planarizing interlayer dielectric to substantially reduce thermal budget and polishing time.
- a barrier layer is firstly formed over a semiconductor substrate, and a buffer layer is then formed on the barrier layer by a spin-on-glass technique.
- the buffer layer may be cured to strengthen bonding in the buffer layer.
- a borophosilicate glass (BPSG) layer is formed on the buffer layer, wherein the polishing rate of the borophosilicate glass layer is larger than the polishing rate of the buffer layer, and the barrier layer serves as a block of autodoping coming from the borophosilicate glass layer.
- the borophosilicate glass layer is polished using the buffer layer as buffer by a chemical-mechanical polishing, thereby planarizing the borophosilicate glass layer.
- FIG. 1 shows a cross-sectional view illustrative of a conventional planarization method using a borophosilicate glass (BPSG) layer as interlayer dielectric (ILD);
- BPSG borophosilicate glass
- ILD interlayer dielectric
- FIG. 2 shows a cross-sectional view illustrative of a planarization method in accordance of one embodiment of the present invention.
- FIG. 3 shows a cross-sectional view illustrative of the planarization method in accordance of the embodiment of the present invention, wherein the interlayer dielectric has a substantially uniform surface.
- a metal-oxide-semiconductor field effect transistor having a gate 20 and source/drain 22 is conventionally formed in and on the substrate 24.
- Field oxide (FOX) 26 is conventionally formed on the FOX region 26.
- a thin dielectric layer 28 having a thickness of about 1500 angstroms is then conformably formed over the substrate 24 and the gate 20.
- the dielectric layer 28 is a silicon oxide layer preferably formed by the pyrolytic oxidation of tetraethylorthosilane (TEOS) carried by atmospheric pressure chemical vapor deposition (APCVD) or low pressure chemical vapor deposition (LPCVD) at about 650°-750° C., and proceeded as follows:
- the dielectric layer 28 is primarily used as a barrier layer to block autodoping of Bs or Ps from a borophosilicate glass (BPSG) layer 32, which will be described later.
- BPSG borophosilicate glass
- a buffer layer 30 which is preferably formed, in this embodiment, by a conventional spin-on-glass (SOG) technique.
- the thickness of this buffer layer 30 is about 3000 angstroms, but can range from about 1000 to 10000 angstroms.
- methylpolysiloxane is preferably used.
- the buffer layer 30 may be cured at about 250°-500° C. in 0.5-4 hours, so that the chemical bonding of the methylpolysiloxane is cross linked, and strengthened.
- the method used in the curing may be vacuum, N 2 , or E-beam cure.
- a dielectric layer 32 such as silicon oxide layer is formed on the buffer layer 30.
- a BPSG is preferably used as the material of this dielectric layer 32, which is formed by any suitable chemical vapor deposition (CVD) method, using co-oxidation of SiH 4 , B 2 H 6 , and PH 3 with O 2 and N 2 O, in a nitrogen carrier gas.
- Typical temperature for forming the BPSG layer 32 is about 350°-400° C. for plasma enhanced chemical vapor deposition (PECVD), and 400°-450° C. in the absence of plasma enhancement.
- PETEOS plasma enhanced tetraethylorthosilane
- PETEOS plasma enhanced tetraethylorthosilane
- the thickness of the dielectric layer 32 is about 1000-5000 angstroms, which is thinner compared to that used in the conventional method (7500 angstroms in the BPSG layer 10 of FIG. 1). It is noted that the BPSG layer 32 is thin enough to eliminate the subsequent reflow step of the BPSG layer 32, thereby reducing thermal budget in fabricating very large scale integration (VLSI) circuits. Further, elimination of the reflow step substantially reduces autodoping of Bs and Ps.
- a planarization method such as chemical-mechanical polishing (CMP) method is performed over the dielectric layer 32.
- the buffer layer 30 is generally used in the present invention as a buffer (or cushion) during polishing, because of its slower polishing rate than the dielectric layer 32, therefore substantially improving the resulting uniformity of the polished dielectric layer 32 as shown in FIG. 3.
- the polishing time is substantially reduced due to the fact that a thin dielectric layer 32 is used, and the polishing of a non-reflowed dielectric layer 32 becomes faster, thereby increasing the throughput in fabricating VLSI circuits.
Abstract
Description
Si(C.sub.2 H.sub.5 O).sub.4 +12O.sub.2 =SiO.sub.2 +8CO.sub.2 +10H.sub.2 O
Claims (16)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/920,172 US5883004A (en) | 1997-08-25 | 1997-08-25 | Method of planarization using interlayer dielectric |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/920,172 US5883004A (en) | 1997-08-25 | 1997-08-25 | Method of planarization using interlayer dielectric |
Publications (1)
Publication Number | Publication Date |
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US5883004A true US5883004A (en) | 1999-03-16 |
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US08/920,172 Expired - Lifetime US5883004A (en) | 1997-08-25 | 1997-08-25 | Method of planarization using interlayer dielectric |
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Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6025272A (en) * | 1998-09-28 | 2000-02-15 | Advanced Micro Devices, Inc. | Method of planarize and improve the effectiveness of the stop layer |
US6057251A (en) * | 1997-10-02 | 2000-05-02 | Samsung Electronics, Co., Ltd. | Method for forming interlevel dielectric layer in semiconductor device using electron beams |
US6303043B1 (en) * | 1999-07-07 | 2001-10-16 | United Microelectronics Corp. | Method of fabricating preserve layer |
US20040023501A1 (en) * | 2002-08-05 | 2004-02-05 | Lee H. W. | Method of removing HDP oxide deposition |
DE10034905B4 (en) * | 1999-09-14 | 2005-11-03 | Hewlett-Packard Development Co., L.P., Houston | Determination of photoconductive wear |
US20140024180A1 (en) * | 2012-07-20 | 2014-01-23 | Applied Materials, Inc. | Interface adhesion improvement method |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5250472A (en) * | 1992-09-03 | 1993-10-05 | Industrial Technology Research Institute | Spin-on-glass integration planarization having siloxane partial etchback and silicate processes |
US5674784A (en) * | 1996-10-02 | 1997-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming polish stop layer for CMP process |
US5674783A (en) * | 1996-04-01 | 1997-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for improving the chemical-mechanical polish (CMP) uniformity of insulator layers |
US5700349A (en) * | 1995-01-20 | 1997-12-23 | Sony Corporation | Method for forming multi-layer interconnections |
-
1997
- 1997-08-25 US US08/920,172 patent/US5883004A/en not_active Expired - Lifetime
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5250472A (en) * | 1992-09-03 | 1993-10-05 | Industrial Technology Research Institute | Spin-on-glass integration planarization having siloxane partial etchback and silicate processes |
US5700349A (en) * | 1995-01-20 | 1997-12-23 | Sony Corporation | Method for forming multi-layer interconnections |
US5674783A (en) * | 1996-04-01 | 1997-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for improving the chemical-mechanical polish (CMP) uniformity of insulator layers |
US5674784A (en) * | 1996-10-02 | 1997-10-07 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming polish stop layer for CMP process |
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6057251A (en) * | 1997-10-02 | 2000-05-02 | Samsung Electronics, Co., Ltd. | Method for forming interlevel dielectric layer in semiconductor device using electron beams |
US6025272A (en) * | 1998-09-28 | 2000-02-15 | Advanced Micro Devices, Inc. | Method of planarize and improve the effectiveness of the stop layer |
US6303043B1 (en) * | 1999-07-07 | 2001-10-16 | United Microelectronics Corp. | Method of fabricating preserve layer |
DE10034905B4 (en) * | 1999-09-14 | 2005-11-03 | Hewlett-Packard Development Co., L.P., Houston | Determination of photoconductive wear |
US20040023501A1 (en) * | 2002-08-05 | 2004-02-05 | Lee H. W. | Method of removing HDP oxide deposition |
US6897121B2 (en) * | 2002-08-05 | 2005-05-24 | Macronix International Co., Ltd. | Method of removing HDP oxide deposition |
US20140024180A1 (en) * | 2012-07-20 | 2014-01-23 | Applied Materials, Inc. | Interface adhesion improvement method |
US9449809B2 (en) * | 2012-07-20 | 2016-09-20 | Applied Materials, Inc. | Interface adhesion improvement method |
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