US5818373A - Interface between superconductor and semiconductor electronic circuits using phase-shift keying coded output data format - Google Patents
Interface between superconductor and semiconductor electronic circuits using phase-shift keying coded output data format Download PDFInfo
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- US5818373A US5818373A US08/772,017 US77201796A US5818373A US 5818373 A US5818373 A US 5818373A US 77201796 A US77201796 A US 77201796A US 5818373 A US5818373 A US 5818373A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
- H03K19/195—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices
- H03K19/1954—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using superconductive devices with injection of the control current
Definitions
- the present invention relates to the interfacing of superconductor and semiconductor electronic circuits, and more particularly to the interfacing of Rapid Single-Flux-Quantum Josephson-junction circuits to room temperature electronic circuits by way of Phase-Shift-Keying coded data.
- room temperature semiconductor electronic technologies can handle multi-gigabit frequencies only if broad parallel circuits are employed, which necessitates unacceptably high power consumption. For this reason, research has turned to superconductor electronics as a viable alternative to traditional semiconductor electronics for ultrafast applications.
- RSFQ Rapid Single-Flux-Quantum
- SFQ short Single-Flux-Quantum
- RSFQ circuits allow even complex circuits to operate in the GHz clock frequency range. Due to a fundamental energy loss of about 10 -18 J/bit, such RSFQ circuits realize the goal of achieving considerably reduced power consumption (when compared to their semiconductor counterparts) at high clock frequencies.
- RSFQ circuits Due to their ability to provide ultrafast processing at low power consumption, the use of RSFQ circuits in digital systems which include room temperature semiconductor electronic components has become increasingly desirable. This necessitates the need to convert SFQ pulses, the data representation of RSFQ logic, into standard dc signals (a "SFQ/DC” converter) and conversely to convert dc signals into SFQ pulses (a "DC/SFQ” converter). Because semiconductor circuits operate at much higher signal power levels as compared to RSFQ circuits, sending data from semiconductor devices to RSFQ circuits is a relatively simple task. Sending data from RSFQ circuits to the semiconductor environment presents a far more daunting challenge.
- a simple SFQ/DC converter will convert a Return-to-Zero ("RZ") SFQ signal into an output dc voltage of the order of 100 ⁇ V, a signal that must be amplified by several orders of magnitude before it can be passed on to semiconductor electronic devices.
- RZ Return-to-Zero
- signal amplification will be effected by an array of semiconductor preamplifiers.
- a significant problem with such signal amplification lies in the fact that the output voltage signal may become contaminated by a non-zero dc component in the aforementioned RZ data, thereby reducing the noise margin of the room temperature semiconductor circuits which receive and further process the data.
- PSK Phase-Shift-Keying
- Manchester coding An alternative approach to providing a clean output signal lies in the use of Phase-Shift-Keying ("PSK”) or Manchester coding.
- PSK coding contains a zero dc spectral component.
- PSK coded data one cycle of a square wave with a particular phase is used to represent a "1" while the cycle of the square wave of opposite phase is used to represent a "0.”
- the use of such coding in the semiconductor environment is well-known and is fully described in J. D. Gibson, "Principals of Digital and Analog Communications," pp. 251-252 (Macmillan Publishing Co., 2d ed. 1993), the disclosure of which is incorporated by reference herein.
- SAIL Series Array Interferometer Logic
- EXOR exclusive OR
- the SAIL gate includes two dc Superconducting Quantum Interference Devices ("dc SQUIDs”), each of which is essentially a superconducting loop having two Josephson junctions. Two inputs (in the form of transmission lines) are directed to one of the SQUIDs, with one input designated to be fed with a high speed carrier signal and the second with a slower rate data signal. With this arrangement, the output signal will either follow the carrier signal, or be inverted with respect to that signal by the data signal. The output signal will be noiseless as it is always in one of two states (high or low), and never in a state with an intermediate apparent phase.
- the SAIL gate provides a clean signal that may be verily decoded and passed on to semiconductor electronics, it does not provide an adequate mechanism for receiving data from RSFQ circuits. This is due to an incompatibility of information presentation. Although information in the SAIL gate is presented through the presence or absence of a current, information in an RSFQ cell is presented through the presence or absence of a short voltage pulse. Accordingly, there exists a need in the art for a reliable, high-speed technique for sending data from RSFQ circuits to a semiconductor circuit.
- An object of the present invention is to provide a reliable, high-speed technique for sending data from RSFQ circuits to a semiconductor circuit.
- a further object of the present invention is to eliminate the contamination of an RSFQ output signal by a non-zero dc component in the signal.
- An additional object of the present invention is to provide a superconductor circuit to semiconductor circuit interface which does not reduce the noise margin of the semiconductor circuits which receive and further process data provided by superconductor circuits.
- Yet another object of the present invention is to effectively utilize PSK modulation in the superconductor side of the interface.
- the present invention provides a circuit for receiving SFQ data pulses from a superconductor signal source, and first and second clock pulses that are substantially equal in frequency but opposite in phase from first and second clock signal sources, and for encoding and converting the SFQ data pulses into a phase-shift-keying coded dc output voltage.
- the circuit includes RSFQ T-RS flip-flop circuitry, including quantizing circuitry for storing a current in one of two stable states, which is responsive to the first and second clock pulses and the data pulse, for PSK coding the SFQ data pulses.
- the circuit also includes a SFQ/DC converter, which is coupled to the quantizing circuitry of the RSFQ T-RS flip-flop circuitry and is responsive to a state of the current stored in the inductance loop of the quantizing circuitry, for converting the PSK coded SFQ data pulses into a PSK coded dc voltage.
- a SFQ/DC converter which is coupled to the quantizing circuitry of the RSFQ T-RS flip-flop circuitry and is responsive to a state of the current stored in the inductance loop of the quantizing circuitry, for converting the PSK coded SFQ data pulses into a PSK coded dc voltage.
- the quantizing circuitry is a quantizing inductance loop within the T-RS RSFQ circuitry.
- the quantizing inductance loop is capable of storing a current in one of two stable states, a high state and a low state, which are distinguishable by the number of flux quanta trapped in the loop.
- the RSFQ circuit also includes a current source and two Josephson junction rings.
- the current source is coupled to the input end of the quantizing inductance loop to furnish an electrical current to the quantizing inductance loop to establish the stored current.
- the first Josephson junction ring is formed of two pairs of Josephson junctions with two input points between each pair of junctions, and is coupled to an input end of the quantizing inductance loop at a position between the two pairs of Josephson junctions.
- the first ring is coupled for receiving the data pulse at a first of its input points and the second clock pulse at a second of its input points, for setting a state of the stored current into one of the two stable states, and for toggling the set state of the stored current into a different one of the two stable states.
- the second Josephson junction ring is likewise formed of two pairs of Josephson junctions with two input points between each pair of junctions, and is coupled to the output end of the quantizing inductance loop at a position between the two pairs of Josephson junctions.
- the second ring is coupled for receiving the first clock pulse at a first of the input points and the second clock pulse at a second of the input points, for resetting a state of the stored current into one of the two stable states, and for toggling the reset state of the stored current into a different one of the two stable states.
- the quantizing inductance loop may be in the form of two storage loops of unequal inductance connected in series.
- the SFQ/DC converter which may include a HUFFLE circuit for preamplifying the coded dc voltage, is advantageously coupled to the quantizing inductance loop at a position between the two storage loops.
- the RSFQ T-RS flip-flop circuit also includes four auxiliary Josephson junctions, with each of the two input points of the first Josephson junction ring and each of the two input points of the second Josephson junction ring coupled to one auxiliary Josephson junction.
- the first ring is constructed to receive the data pulse and the second clock pulse through separate auxiliary junctions
- the second ring is constructed to receive the first clock pulse and the second clock pulse through other separate auxiliary junctions.
- one auxiliary junction from each ring may be coupled to a common line, so that the second input point of the first Josephson junction ring and the second input point of the second Josephson junction ring receive the second clock pulse through the common line.
- three input inductances may be added to the circuit, where one input inductance is coupled to the common line to receive the second clock signal, a second input inductance is coupled to a first auxiliary junction to receive the data signal, and a third input inductance is coupled to a third auxiliary junction to receive the first clock signal.
- the present invention also provides a method for encoding and converting SFQ data pulses generated by a superconducting signal source into a PSK coded dc output voltage.
- the steps of the method are (a) establishing a quantized current in one of two quantized states; (b) receiving a first clock pulse and any generated single-flux-quantum data pulses during a first portion of a clock cycle; (c) causing the quantized current to be in a first of the two quantized states if a first predetermined number of data pulses are received in step (b); (d) causing the quantized current to be in a second of the two quantized states if a second predetermined number of data pulses are received in step (b); (e) receiving a second clock pulse during a second portion of the clock cycle; (f) toggling the quantized current from the first quantized state to the second quantized state if the quantized current is in the first quantized state, or from the second quantized state to the first quantized state if the quant
- the first clock pulse is received approximately one hundred picoseconds prior to receiving one single-flux-quantum data pulse if the superconducting signal source has generated a data pulse during a corresponding clock cycle.
- step (c) may include the sub-steps of resetting, after receiving the first clock pulse, the quantized current to a low state if the quantized current was in a high state during an immediately preceding clock cycle portion, and setting, after receiving the data pulse, the quantized current to a high state if one data pulse is received during the first clock cycle portion.
- step (d) may include resetting the quantized current to a low state if no data pulses are received during the first clock cycle portion and if the quantized current was in a high state during an immediately preceding clock cycle portion.
- FIG. 1 is a circuit diagram of an exemplary SFQ/DC converter including a Phase-Shift-Keying circuit in accordance with the present invention
- FIG. 2 is a circuit diagram of an exemplary superconductor circuit to semiconductor circuit interface according to the present invention
- FIG. 3 is a block diagram of an alternative embodiment of the SFQ/DC converter illustrated in FIG. 1;
- FIG. 4 is a graph illustrative of the form of the output data in accordance with the present invention.
- the circuit 100 receives SFQ data pulses D at 130 from a superconducting signal source (not shown), such as another RSFQ logic circuit.
- the circuit 100 also receives a system clock pulse ClK 1 at 140 from a system clock (not shown), and a second clock pulse ClK 2 at 101 from a second clock signal source (also not shown).
- Second clock pulse ClK 2 is substantially equal in frequency to ClK 1 , but differs in phase by 180°.
- the clock signals ClK 1 and ClK 2 have a frequency ranging from 100 KHz to 2 GHz depending on the application.
- the circuit 100 uses the clock signals ClK 1 and ClK 2 to encode the SFQ data pulses D into a PSK coded dc output voltage, as will be described below.
- the circuit 100 includes a quantizing inductance 150 and two Josephson junction rings 110, 120 which form the core of a modified RSFQ T-RS flip-flop circuit with four inputs 112, 114, 122, and 124.
- the T-RS flip-flop subfamily of RSFQ circuits is generally described in Stanislav V. Polansky et al., "Single Flux, Quantum B Flip-Flop and Its Possible Applications," 4 IEEE Trans. Applied Superconductivity 9 (1994), the disclosure of which is incorporated by reference herein.
- the operation of the modified T-RS flip-flop circuit shown in FIG. 1 is now described.
- Each Josephson junction ring essentially consists of four Josephson junctions connected in a series loop that includes two ground terminals.
- ring 110 includes junctions J 1 , J 2 , J 4 , and J 5 connected in a series loop that includes ground
- ring 120 includes the ground and junctions J 7 , J 8 , J 10 , and J 11 connected in a series loop that includes ground.
- Ring 110 is connected to the quantizing inductance 150 at point 113 which lies in between junctions J 2 and J 4 .
- Ring 120 is also connected to the quantizing inductance 150 at point 123 which lies in between junctions J 8 and J 10 .
- the Josephson junctions J 1 , J 2 , J 4 , J 5 , J 7 , J 8 , J 10 , and J 11 should be chosen to have nominal values that are suitable for the voltages associated with signals D, ClK 1 and ClK 2 .
- the junctions For typical SFQ voltage pulses of approximately 2 mV ⁇ ps, the junctions should have nominal values substantially within the range of 0.25-0.27 mA.
- auxiliary inductances L 3 and L 4 may be included in ring 110 at points above and below the junction point 113 to provide more sequential, rather than simultaneous switching of either junctions J 2 and J 5 or J 1 and J 4 , as will be described below.
- auxiliary inductances L 8 and L 9 may be included in ring 120 above and below the junction point 123. The inclusion of auxiliary inductances L 3 , L 4 , L 8 and L 9 have the effect of widening of the parameter margins associated with the circuit.
- the quantizing inductance 150 includes loops L 6 , L 11 , which act as a single main storage loop.
- the overall inductance of loops L 6 , L 11 should be relatively large as compared with the auxiliary inductances. It is desirable to use two loops in the context of the present invention so that an SFQ/DC converter 160 may be linked to the quantizing inductance 150 at a convenient point 151 which lies between the loops L 6 , L 11 . Further, in order to increase the overall margin of the circuit, it is desirable for one of the loops to have a greater inductance than the other, e.g., by setting L 6 to a greater value than L 11 , to create an asymmetrical circuit.
- storage loop L 6 preferably has a nominal value of approximately 2.89 pH
- storage loop L 11 preferably has a nominal value of approximately 1.05 pH.
- the current source I 1 is connected to one end 113 of the quantizing inductance 150, and furnishes an electrical current to the quantizing inductance to establish a stored current within the loops L 6 and L 11 .
- Auxiliary Josephson junctions J 3 , J 6 , J 9 , and J 12 may be linked to the circuit at each of the four inputs 112, 114, 122, and 124, respectively.
- junction J 6 and an input inductance L 5 are serially connected between input point 114 of ring 110 and data input terminal 130.
- data D in the form of SFQ pulses which arrive at data terminal 130 will enter the left Josephson junction ring 110 at input point 114.
- Junction J 12 and an input inductance L 10 are likewise serially connected between input point 124 of ring 120 and system clock input terminal 140, so that system clock pulses CLK 1 in the form of SFQ pulses which arrive at the system clock terminal 140 will enter the right Josephson junction ring 120 at input point 124.
- Junctions J 3 and J 9 are connected to input points 112 and 122 of rings 110, 120, respectively, and are connected to each other to form a serial connection between input points 112 and 122 of rings 110 and 120.
- the common point 102 linking junctions J 3 and J 9 is connected to the second clock terminal 101 via input inductance L 1 , so that the second clock signal ClK 2 passes through input inductance L 1 and is split between the left input branch J 3 , 112, and the right input branch J 9 , 122 to reach input points 112 and 122 of rings 110 and 120, respectively.
- Inductances L 2 and L 7 represent the parasitic inductances of the left and right Josephson junction rings 110 and 120, respectively.
- the T-RS flip-flop circuit 110, 120, 150 has two stable states which are distinguished by the number of flux quantum which are trapped in the main storage loop 150, i.e., by the value of the dc current flowing through loops L 6 , L 11 .
- the circuit possesses substantial top-bottom and left-right symmetries, and can be set to a logic "1" state by an SFQ pulse arriving at either of the two inputs 112, 114, or reset to a logic "0" state by an SFQ pulse arriving at either of the two inputs 122, 124.
- the T-RS flip-flop circuit 110, 120, 150 constructed in accordance with the above description operates in the following manner.
- the bias current provided by source I 1 is mostly split between the two arms of the left Josephson junction ring, traveling to ground via junction pairs J 1 , J 2 and J 4 , J 5 , respectively.
- An SFQ pulse arriving at input 114 via data input terminal 130 switches sub-critically biased junction J 5 .
- the pulse generated by this switching steers additional current into junctions J 1 and J 2 . Because some of the current drawn through junction J 2 will be diverted at input 112, only a portion of this current reaches junction J 1 . Thus, it is the function of junction J 2 that is switched by the arrival of this additional current.
- junctions J 5 and J 2 steers most of the bias current into the loops L 6 , L 11 and hence into the right Josephson ring 120.
- the circuit is thus switched into state "1".
- an SFQ pulse arriving at input 112 via second clock terminal 101 switches sub-critically biased junction J 1 , which in turn steers additional current into junctions J 4 and J 5 to thereby switch junction J 4 , causing most of the bias current to be steered into the loops L 6 , L 11 , and hence into the right josephson ring 120.
- the circuit is likewise switched into state "1" under such conditions.
- auxiliary junction J 3 works in a similar manner where a SFQ pulse arrives at input 114 and the circuit is already in the "1" state. In this manner, the auxiliary junctions J 3 and J 6 act to stabilize the circuit when a signal which cannot be responded to is applied to the circuit 110, 120 and 150.
- an SFQ pulse arriving at input 122 via second clock terminal 101 switches junction J 7 , which in turn steers additional current into junctions J 10 and J 11 to thereby switch junction J 10 , causing most of the bias current to be steered into the loops L 6 , L 11 and hence into the right Josephson ring 120.
- the circuit is likewise switched into state "1" under such conditions.
- auxiliary junction J 9 works in a similar manner to buffer the T-RS flip-flop circuit when the circuit is already in the "0" state when an SFQ pulse arrives at input 124.
- the data signal D and the clock signals ClK 1 and ClK 2 cause switching of Josephson junctions as described above to place the main inductance 150 in a "0" or a "1" state.
- the SFQ/DC converter 160 When the main inductance is in a "1" state, the SFQ/DC converter 160 will generate a non-zero dc voltage V which is placed on line 180. If the main inductance is in the "0" state, the SFQ/DC converter will generate zero voltage.
- the SFQ/DC converter 160 shown in FIG. 1 is a well-known SFQ/DC converter and includes Josephson junctions J 13 and J 14 , resistors R 1 , R 2 and R 3 , inductance coils L 13 , L 14 , and L 15 , and a biasing subcircuit including current source I 2 , junction J 15 , resistor R 4 and inductance coil L 16 .
- Inductance coil L 12 links the SFQ/DC circuitry to the convenient point 151 of the RSFQ T-RS flip-flop circuit which lies between the loops L 6 and L 11 .
- the SFQ/DC converter produces an output voltage close to the range of 100-150 ⁇ V when the main storage loop 150 is in the "1" state. The output voltage is in the Return-to-Zero format.
- Tables 1 and 2 below list the values of the circuit elements shown in FIG. 1 under two presently preferred operating points.
- a superconductor circuit to room temperature semiconductor circuit interface according to the present invention is shown.
- the thin film superconductor circuit 100 is fabriacted on an appropriate substrate 200, and the output line 180 of the circuit 100 is connected to contact pads 201, 202 of a 50 ohm microstrip 210.
- the chip 200 is placed into a cryogenic probe (not shown) and kept at or below the required critical temperature for the superconductor materials used in the fabrication of the circuit 100.
- the zone indicated by 280 is kept at or below 4° Kelvin.
- a high-temperature superconductor i.e., a superconductor having a relatively high critical temperature
- a higher minimum temperature for the zone 280 would be required.
- the microstrip 210 is connected to a commercially available coplanar waveguide 220 to a second microstrip 230, which is within the room temperature (300° Kelvin) environment 290.
- a suitable waveguide 220 is the Amp Microstrip Cable Assemblies (Catalog 65069) available from AMP Inc. in Harrisburg, Pa.
- the room temperature microstrip 230 is interfaced to a standard coaxial cable 240, which delivers the Return-to-Zero output voltage to a semiconductor preamplification circuit 250.
- the preamplification circuit 250 may include a series of monolithic silicon bipolar microwave amplifiers 261, 262.
- the amplifiers which may each have 20 dB gain at 100 Mhz, are cascaded to achieve the input level requirements of an ECL buffer 270 or a comparator.
- the output line 180 of SFQ/DC converter 150 is connected to a HUFFLE driver 301, which is connected to an output line 301.
- the design and operation of a HUFFLE driver is well known in the field and will not be explained in further detail herein.
- the HUFFLE driver preamplifies the 100-150 ⁇ V Return-to-Zero signal generated by the SFQ/DC converter 150 into a Return-to-Zero signal having a voltage close to the gap voltage of the Josephson junctions that are employed in the HUFFLE driver.
- the gap voltage is close to 2.6 mV, and a HUFFLE driver fabricated from Nb junctions will provide an output voltage of approximately 1.5 mV.
- circuit 100 to encode the SFQ data pulses D into a PSK coded dc output voltage is now described.
- the system clock signal ClK 1 is received at terminal 124 of the circuit of FIG. 1 at the beginning of every clock cycle, and the second clock pulse ClK 2 is received at terminal 101 at the midpoint of every clock cycle.
- FIG. 4 shows a waveform 400 illustrative of the form of the output data in accordance with the present invention.
- the system clock signal ClK 1 will arrive at terminal 140 and reset the circuit to the "0" state, as described above.
- a data pulse D arrives at the data input 130 and sets the circuit to the "1" state, as described above.
- the delay is chosen to be larger than the setup time of the circuit, approximately 30 ps, which is negligible when compared to the MHz scale chosen for the system clock.
- the output V With the circuit in the "1" state, the output V will be a non-zero output (100-150 ⁇ V in a non-HUFFLE circuit).
- the second clock signal ClK 2 arrives at terminal 101.
- the portion of the pulse which is directed into the left Josephson junction ring 110 will have no effect on the state of the circuit, as described above, because the circuit is already in the "1" state.
- the portion of the pulse which is directed into the right Josephson junction ring 120 will switch the circuit into the "0" state, i.e., it will toggle the circuit into the opposite state.
- a logical "1" representative of a data pulse D arriving at terminal 130 is encoded to be a positive voltage during the first half of the system clock cycle, and a zero voltage during the second half of the system clock cycle.
- a logical "0" a logical "0" arrives at the terminal 130, there is no pulse which can change the state of the circuit; the circuit is already in the "0" state, and the system clock signal ClK 1 arriving at terminal 140 will have no effect on the state of the circuit.
- the second clock signal ClK 2 arrives at terminal 101 at the beginning of the second half of the clock cycle 404, and toggles the circuit to the "1" state.
- a logical "0" representative of the absence of a data pulse D arriving at terminal 130 is encoded to be a zero voltage during the first half of the system clock cycle, and a positive voltage during the second half of the system clock cycle.
- the absence of a data pulse D during the third clock cycle 405 is likewise encoded to be a zero voltage during the first half of the third system clock cycle, and a positive voltage during the second half of the third system clock cycle 406.
- a data pulse D arriving during the fourth clock cycle 407 is encoded to be a positive voltage during the first half of the fourth system clock cycle, and a zero voltage during the second half of the fourth system clock cycle 408.
- the circuit could trivially be modified by employing a so-called T 2 , rather than the above-described T-RS, version of the flip-flip circuit in order to generate a differential PSK code.
- T 2 so-called T-RS
- Such a circuit includes only two inputs, one for data pulses D and a second for the second clock signal CLK 2 , while eliminating the input for the system clock CLK 1 .
- the state of the quantizing inductance loop is toggled by each data pulse D.
- This modification simplifies the superconductor circuit side of the interface by eliminating the system clock, but requires additional circuitry on the semiconductor circuit side of the interface in order to reconstruct the data D by bay of an exclusive OR function between two successive signals.
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Abstract
Description
TABLE 1 ______________________________________ Element Nominal Value Element Nominal Value ______________________________________ I.sub.1 0.50 mA L.sub.1 1.84 pH I.sub.2 0.40 mA L.sub.2 1.05 pH J.sub.1 0.27 mA L.sub.3 0.66 pH J.sub.2 0.25 mA L.sub.4 0.66 pH J.sub.3 0.22 mA L.sub.5 2.10 pH J.sub.4 0.25 mA L.sub.6 2.89 pH J.sub.5 0.27 mA L.sub.7 1.05 pH J.sub.6 0.30 mA L.sub.8 0.66 pH J.sub.7 0.25 mA L.sub.9 0.66 pH J.sub.8 0.25 mA L.sub.10 2.23 pH J.sub.9 0.19 mA L.sub.11 1.05 pH J.sub.10 0.25 mA L.sub.12 0.53 pH J.sub.11 0.27 mA L.sub.13 0.39 pH J.sub.12 0.25 mA L.sub.14 0.39 pH J.sub.13 0.125 mA L.sub.15 0.53 pH J.sub.14 0.25 mA R.sub.1 2.38 Ω J.sub.15 0.22 mA R.sub.2 0.36 Ω R.sub.3 0.36 Ω R.sub.4 0.71 Ω ______________________________________
TABLE 2 ______________________________________ Element Nominal Value Element Nominal Value ______________________________________ I.sub.1 0.43 mA L.sub.1 1.50 pH I.sub.2 0.14 mA L.sub.2 0.42 pH J.sub.1 0.22 mA L.sub.3 0.79 pH J.sub.2 0.21 mA L.sub.4 0.63 pH J.sub.3 0.21 mA L.sub.5 2.52 pH J.sub.4 0.22 mA L.sub.6 2.70 pH J.sub.5 0.25 mA L.sub.7 1.05 pH J.sub.6 0.24 mA L.sub.8 0.53 pH J.sub.7 0.25 mA L.sub.9 0.53 pH J.sub.8 0.25 mA L.sub.10 2.79 pH J.sub.9 0.21 mA L.sub.11 1.47 pH J.sub.10 0.24 mA L.sub.12 0.079 pH J.sub.11 0.26 mA L.sub.13 0.39 pH J.sub.12 0.24 mA L.sub.14 0.39 pH J.sub.13 0.12 mA L.sub.15 0.79 pH J.sub.14 0.15 mA R.sub.1 2.38 Ω J.sub.15 SHORT R.sub.2 0.36 Ω R.sub.3 0.36 Ω R.sub.4 0.71 Ω ______________________________________
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US6756925B1 (en) | 2003-04-18 | 2004-06-29 | Northrop Grumman Corporation | PSK RSFQ output interface |
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US9741918B2 (en) | 2013-10-07 | 2017-08-22 | Hypres, Inc. | Method for increasing the integration level of superconducting electronics circuits, and a resulting circuit |
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