US5745541A - Data shift control circuit - Google Patents
Data shift control circuit Download PDFInfo
- Publication number
- US5745541A US5745541A US08/797,006 US79700697A US5745541A US 5745541 A US5745541 A US 5745541A US 79700697 A US79700697 A US 79700697A US 5745541 A US5745541 A US 5745541A
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- US
- United States
- Prior art keywords
- register
- shift
- action
- circuit
- allowing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
Definitions
- the present invention relates to a data shift control circuit, and more particularly to a data shift control circuit for a shift register.
- Shift register are commonly used in digital circuits.
- the digital data stored in the shift register can be processed with the logic operations such as Shift Right (SR), Shift Left (SL), Rotate Right (RR), Rotate Left (RL), Shift Right with Carry (SRC), Shift Left with Carry (SLC), Rotate Right with Carry (RRC), and Rotate Left with Carry (RLC).
- SR Shift Right
- SL Shift Left
- RR Rotate Right
- RL Rotate Left
- SRC Shift Right with Carry
- SLC Shift Left with Carry
- RRC Rotate Right with Carry
- RLC Rotate Right with Carry
- RLC Rotate Left with Carry
- the logic operation commands (S0, S1, S2) are first decoded, and the outputs from the corresponding control lines (SR, SL, RR, RL, SRC, SLC, RRC, and RLC) are decided.
- the registers in the shift register are then triggered to execute the corresponding operations. Finally, the desired result such as Shift or Rotate is obtained.
- One objective of the present invention is to provide a more economical data shift control circuit for a shift register.
- Another objective of the present invention is to provide a more simplified data shift control circuit for a shift register.
- Still an objective of the present invention is to provide a more effective data shift control circuit for a shift register.
- the present invention provides data shift control circuit for a shift register in response to a logic operation command code.
- the shift register includes a first register and a second register and the logic operation command code includes a first portion and a second portion.
- the circuit includes a first decoder for decoding the first portion to transmit a move signal, a second decoder for decoding the second portion to transmit a control signal; a control signal channel, electrically connected to the first register and the second register, for allowing the first register and the second register to receive the control signal and for allowing the shift register to execute a first action and a move signal channel, electrically connected to all registers of the shift register for allowing the all registers to receive the move signal and for allowing the shift register to execute a second action.
- the first register can be a Most Significant Bit register
- the second register can be a Least Significant Bit register.
- the first action can include a Shift action, and the first action can include a Rotate action.
- the second action can include a Shift Left action
- the second action can include a Shift Right action.
- all of the registers can include at least 2 registers.
- FIGS. 1(a) to 1(h) illustrate block diagrams showing the actions of Shift Right, Shift Left, Rotate Right, Rotate Left, Shift Right with Carry, Shift Left with Carry, Rotate Right with Carry, and Rotate Left with Carry;
- FIG. 2 illustrates a block diagram showing one preferred embodiment of the present invention
- FIG. 3 illustrates a control circuit including a Most Significant Bit register and a Least Significant Bit register according to one preferred embodiment of the present invention
- FIG. 4 illustrates a data shift circuit for a shift register according to one preferred embodiment of the present invention.
- the shift register includes a Most Significant Bit register (22) and a Least Significant Bit register (21) and the logic operation command code (S0, S1, S2) includes a first portion (S2) and a second portion (S0, S1).
- the present invention includes a first decoder (11) for decoding the first portion (S2) to transmit a move signal; a second decoder (12) for decoding the second portion (S0, S1) to transmit a control signal; a control signal channel (SF, SFC, RTC, RT), electrically connected to the Most Significant Bit register (22) and the Least Significant Bit register (21), for allowing the Most Significant Bit register (22) and the Least Significant Bit register (21) to receive the control signal and for allowing the shift register to execute a first action such as a Shift action or a Rotate action; and a move signal channel (ML, MR), electrically connected to all registers (21, 22, 31, 32, 33,34, 35, 36) of the shift register for allowing the all registers (21, 22, 31, 32, 33 34, 35, 36) to receive the move signal and for allowing the shift register to execute a second action such as a Shift Left action or a Shift Right action.
- a control signal channel SF, SFC, R
- the eight logic operation commands Shift Right, Shift Left, Rotate Right, Rotate Left, Shift Right with Carry, Shift Left with Carry, Rotate Right with Carry, and Rotate Left with Carry can be simplified to Move Left (ML) and Move Right (MR).
- the portion of the logic operation command code (S2) is first decoded by the first decoder 11 to decide whether a move signal is to be transmitted. Then, the signal is transmitted to the data shift circuit 14 and the control circuit 13.
- Shift (SF), Shift with Carry (SFC), Rotate with Carry (RTC), and Rotate (RT) it is decided by the portion of the logic operation command code (S0 and S1) in the second decoder 12.
- a control signal is generated and transmitted to the control circuit 13.
- the move signal channels (ML and MR) in the first decoder 11 is connected to every bit of the 8-bit shift register (that is, the data shift circuit 14 and the control circuit 13) so that the actions ML and MR defined by the logic operation commands can be implemented.
- the hardware actions such as Shift, Shift with Carry, Rotate with Carry, Rotate are only related to the Most Significant Bit (MSB) register and the Least Significant Bit (LSB) register in the shift register, so the control signal channels such as Shift, Shift with Carry, Rotate with Carry, and Rotate are only connected to the control circuits 13 including the Most Significant Bit register and the Least Significant Bit register.
- the actions such as Shift, Shift with Carry, Rotate with Carry, Rotate is then well controlled.
- a simplified circuit is obtained and the application is not limited to the bit number of the shift register.
- the bit number of the decoder can be adjusted and the complexity of the circuit can be reduced.
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- Selective Calling Equipment (AREA)
- Communication Control (AREA)
- Shift Register Type Memory (AREA)
Abstract
Description
Claims (8)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE29701339U DE29701339U1 (en) | 1997-01-28 | 1997-01-28 | Data shift control circuit |
US08/797,006 US5745541A (en) | 1997-01-28 | 1997-02-07 | Data shift control circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE29701339U DE29701339U1 (en) | 1997-01-28 | 1997-01-28 | Data shift control circuit |
US08/797,006 US5745541A (en) | 1997-01-28 | 1997-02-07 | Data shift control circuit |
Publications (1)
Publication Number | Publication Date |
---|---|
US5745541A true US5745541A (en) | 1998-04-28 |
Family
ID=26059875
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US08/797,006 Expired - Lifetime US5745541A (en) | 1997-01-28 | 1997-02-07 | Data shift control circuit |
Country Status (2)
Country | Link |
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US (1) | US5745541A (en) |
DE (1) | DE29701339U1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6279044B1 (en) * | 1998-09-10 | 2001-08-21 | Advanced Micro Devices, Inc. | Network interface for changing byte alignment transferring on a host bus according to master and slave mode memory and I/O mapping requests |
US6405092B1 (en) * | 1997-09-29 | 2002-06-11 | William Vincent Oxford | Method and apparatus for amplifying and attenuating digital audio |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5125011A (en) * | 1990-02-13 | 1992-06-23 | Chips & Technologies, Inc. | Apparatus for masking data bits |
US5502408A (en) * | 1993-12-17 | 1996-03-26 | Deutsche Thomson-Brandt Gmbh | Circuit for decoding 2T encoded binary signals |
US5661418A (en) * | 1996-03-13 | 1997-08-26 | Cypress Semiconductor Corp. | Signal generation decoder circuit and method |
US5682340A (en) * | 1995-07-03 | 1997-10-28 | Motorola, Inc. | Low power consumption circuit and method of operation for implementing shifts and bit reversals |
US5689673A (en) * | 1995-02-14 | 1997-11-18 | Hal Computer Systems, Inc. | Apparatus and method for controlling instruction flow by using a matrix of transmission gates in super-scaler microprocessor and selectively delaying microprocessor instruction execution based on resource availability |
-
1997
- 1997-01-28 DE DE29701339U patent/DE29701339U1/en not_active Expired - Lifetime
- 1997-02-07 US US08/797,006 patent/US5745541A/en not_active Expired - Lifetime
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5125011A (en) * | 1990-02-13 | 1992-06-23 | Chips & Technologies, Inc. | Apparatus for masking data bits |
US5502408A (en) * | 1993-12-17 | 1996-03-26 | Deutsche Thomson-Brandt Gmbh | Circuit for decoding 2T encoded binary signals |
US5689673A (en) * | 1995-02-14 | 1997-11-18 | Hal Computer Systems, Inc. | Apparatus and method for controlling instruction flow by using a matrix of transmission gates in super-scaler microprocessor and selectively delaying microprocessor instruction execution based on resource availability |
US5682340A (en) * | 1995-07-03 | 1997-10-28 | Motorola, Inc. | Low power consumption circuit and method of operation for implementing shifts and bit reversals |
US5661418A (en) * | 1996-03-13 | 1997-08-26 | Cypress Semiconductor Corp. | Signal generation decoder circuit and method |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6405092B1 (en) * | 1997-09-29 | 2002-06-11 | William Vincent Oxford | Method and apparatus for amplifying and attenuating digital audio |
US6279044B1 (en) * | 1998-09-10 | 2001-08-21 | Advanced Micro Devices, Inc. | Network interface for changing byte alignment transferring on a host bus according to master and slave mode memory and I/O mapping requests |
Also Published As
Publication number | Publication date |
---|---|
DE29701339U1 (en) | 1997-06-12 |
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Owner name: HOLTEK MICROELECTRONICS, INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:LIN, YI;CHEN, JASON;FAN, HENRY;REEL/FRAME:008468/0005 Effective date: 19970114 |
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Owner name: UTEK SEMICONDUCTOR CORP., TAIWAN Free format text: CHANGE OF NAME;ASSIGNOR:HOLTEK MICROELECTRONICS, INC.;REEL/FRAME:009490/0001 Effective date: 19980630 |
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Owner name: HOLTEK SEMICONDUCTOR INC., TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:UTEK SEMICONDUCTOR CORPORATION;REEL/FRAME:010351/0092 Effective date: 19990712 |
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