US5719884A  Error correction method and apparatus based on twodimensional code array with reduced redundancy  Google Patents
Error correction method and apparatus based on twodimensional code array with reduced redundancy Download PDFInfo
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 US5719884A US5719884A US08508019 US50801995A US5719884A US 5719884 A US5719884 A US 5719884A US 08508019 US08508019 US 08508019 US 50801995 A US50801995 A US 50801995A US 5719884 A US5719884 A US 5719884A
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 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/13—Linear codes
 H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, BoseChaudhuriHocquenghem [BCH] codes
 H03M13/151—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, BoseChaudhuriHocquenghem [BCH] codes using error location or error correction polynomials
 H03M13/1515—ReedSolomon codes

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
 H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
 H03M13/13—Linear codes
 H03M13/15—Cyclic codes, i.e. cyclic shifts of codewords produce other codewords, e.g. codes defined by a generator polynomial, BoseChaudhuriHocquenghem [BCH] codes

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
 H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
 H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
 H03M13/2909—Product codes

 H—ELECTRICITY
 H03—BASIC ELECTRONIC CIRCUITRY
 H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
 H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
 H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
 H03M13/2906—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes using block codes
 H03M13/2927—Decoding strategies
 H03M13/293—Decoding strategies with erasure setting
Abstract
Description
The present invention relates generally to encoding data for transmittal or storage with redundant information so that errors can be detected and corrected upon receipt or retrieval of the data, and more particularly relates to twodimensional code arrays used for error correction in communications and storage channels.
Error correction codes are commonly used in both communications and storage channels to combat data corruption caused by channel noise, media defects, or other interference. A typical communications and/or storage system utilizing error correction is shown in FIG. 1. Some examples of theapplications in which error correction codes are used include: data transmission, broadcasting, and satellite communications in the communications field; and digital sound and video recording, magnetic tapes, semiconductor memories, and compact disks in the information storage field.
In the case of error correction codes known as "block codes," protection against errors is achieved by dividing the data into fixed size blocks (referred to as "raw data blocks") having an integer number, k, of "symbols" each. (Symbols are elements of an alphabet or set of values. In the case of digital information, symbols typically are multibit values of a fixed bit length. For example, commonly used alphabets for digital information such as the 256 symbol ASCII alphabet, generally comprise symbols which are 8bit bytes.) An encoder appends an integer number, r, of redundancy symbols (referred to as "check symbols" or "checks") to each raw data block to form an nsymbol "code block," where n=k+r. This code block is then sent through the communications or storage channel. (For example, the code block is stored on a recording medium such as a magnetic tape or compact disk, or transmitted on a communications medium such as on a telephone wire, a computer network, or a wireless channel, where the code block may become corrupted.) On the receiving side, a decoder uses the redundant information to retrieve the original raw data from a possibly corrupted version of the code block, provided the corruption does not exceed a certain predesigned level.
"Product codes" are a popular choice of error correction code in magnetic recording and like applications where both random and burst errors are likely, due to their ability to offer good protection against both these types of errors. (Random errors are those that occur independently at separate symbol positions of data sent through a communications or storage channel. Burst errors affect a sequential set of symbols in data sent through a communications or storage channel. For example, an electrical disturbance in a communications channel or a media defect in a storage channel can create errors in several adjacent symbols sent through these channels.) In a typical product code encoder such as that shown in FIG. 4, a twodimensional array is built using two ReedSolomon codes operating on 8bit symbols. A first code C_{1} of length n_{1} symbols and redundancy r_{1} symbols is applied to the rows of the array. A second code C_{2} of length n_{2} symbols and redundancy r_{2} symbols is applied to its columns. This yields array dimensions of n_{1} ×n_{2} symbols. In such case, the total redundancy of the array is n_{1} r_{2} +n_{1} r_{1} r_{1} r_{2} symbols per block of n_{1} n_{2} symbols. Using a decoding strategy based on detecting errors with C_{1} and correcting erasures with C_{2} such as illustrated in FIG. 5, this scheme can correct all error bursts affecting r_{2} rows or less, except possibly for a small set of burst error patterns whose probability can be made arbitrarily small by an appropriate choice of the parameter r_{1}. (Many variations on this basic strategy are possible, offering a tradeoff between random and bursterror correction. Various conventional implementations of product code encoders and decoders are described in P. Farrell, A Survey of Array Error Control Codes, 3 ETT 441454 (1992).)
ReedSolomon codes are well known block codes for which efficient encoders and decoders have been developed based on algebraic computations over finite fields. A typical encoder and a decoder for ReedSolomon codes are shown in FIGS. 2 and 3, respectively. ReedSolomon codes exist for any code block length of n symbols less than q+1, where the alphabet of the data includes q symbols. In typical applications, a symbol consists of m binary bits, where m is a positive integer, and q=2^{m} (e.g. m=8, q=256). ReedSolomon codes are particularly useful error correction codes in that these codes attain a theoretical minimum redundancy cost in error detection and correction operations, as shown in the following table 1.
TABLE 1______________________________________Redundancy Cost of Error Correction OperationsError CorrectionOperation Minimum Cost______________________________________error detection 1 check symbol/errorerasure correction 1 check symbol/erasurefull error correction 2 check symbols/error______________________________________
In an error detection operation, the decoder determines whether there are corrupted symbols within a block without determining their location. ReedSolomon codes can detect any pattern of up to r errors (where r is the redundancy of the code). In product code applications, ReedSolomon codes can further detect burst errors with a probability of 1ε, where ε is a number that decreases exponentially with r (assuming each bit in the region affected by the burst error is corrupted with probability 0.5), such as 1q^{1}. In an erasure correction operation, the decoder recovers the values of all corrupted symbols given their locations within the code block. In a full error correction operation, the decoder recovers both the locations of all corrupted symbols within a code block, and their values. ReedSolomon codes can correct any pattern of up to r/2 full errors, or up to r erasures, or any combination in which 2x(errors)+(erasures)≦r, where "errors" is the number of errors and "erasures" is the number of erasures.
There is a further distinction between deterministic (or worstcase) and probabilistic decoding schemes. In a deterministic decoding scheme, the decoder is guaranteed to correct all patterns of up to a predesigned number of errors (e.g. all errors of up to N corrupted rows in a two dimensional array, for some integer N). In a probabilistic scheme, the decoder corrects such patterns with a probability that can be made arbitrarily close to 1, under certain assumptions on the distribution of error patterns. These assumptions are well approximated in practice by the use of scramblers prior to transmission through the channel. By relaxing the error correction requirements from "always" to "with high probability," one can significantly reduce the amount of redundancy in the coding scheme. M. Kasahara, S. Hirasawa, Y. Sugiyama, and T. Namekawa, New Classes of Binary Codes Constructed on the Basis of Concatenated Codes and Product Codes, IEEE Transactions on Information Theory, 462467 (1976) hereafter Kasahara!, describe a scheme that reduces the redundancy of binary product codes, while preserving the minimum Hamming distance (and, hence, the worstcase correction capabilities) of the code. Due to their objective of preserving worstcase correction capabilities, Kasahara achieves limited code redundancy reduction.
In typical prior product codes, the code C_{1} which is applied to the rows of the array is used to detect whether each respective row has become corrupted. The code C_{2} that is applied to the array's columns is used to perform an erasure correction operation that corrects erasure of those rows identified as corrupted by application of code C_{1}. In other words, the detection operation of code C_{1} is utilized to inform the erasure correction operation of code C_{2} as to which rows are corrupted, so that the erasure correction operation can correct locations corresponding to those rows identified as corrupt in each column of the array. When designing such product codes, the redundancy r_{1} of the code C_{1} is generally chosen so that the probability of C_{1} not detecting a corrupted row, which is approximately equal to a^{r}.sbsp.1, is acceptably small. The redundancy r_{2} of the code C_{2} generally is chosen such that the probability of having more than r_{2} corrupted rows is acceptably small.
One drawback to these prior product codes, however, is that although the code C_{1} is able to detect whether up to all n_{2} rows of the product array are corrupted (the code C_{1} is applied to each row of the array and therefore can detect whether each row is corrupted), the code C_{2} is only able to correct up to r_{2} locations (corresponding to such identified, corrupted rows) per column. Since the code C_{2} can correct only up to r_{2} corrupted rows, the information derived from the code C_{1} about combination of any more than r_{2} corrupted rows is useless to the erasure correction operation with the code C_{2}. The ability of the code C_{1} to detect these extra rows (which in any case cannot all be corrected) comes at a price of added redundancy. As a result, a significant portion of the redundancy in these typical prior product code arrays serves no useful purpose.
The present invention provides an apparatus and method which eliminates the excess redundancy related to the unused error detection capability of the code C_{1} in these typical prior product code arrays based on probabilistic decoding. The apparatus and method of the present invention are based on a twodimensional code array which utilizes a third, intermediate code (herein referred to as C_{1}.5) in addition to the codes applied to the rows and columns of the array (herein referred to as C_{1} and C_{2}, respectively). The resulting redundancy in the twodimensional code array according to a preferred embodiment of the present invention is equal to n_{1} r_{2} +r_{1} r_{2}, which is smaller by r_{1} (n_{2} 2r_{2}) than the redundancy in a typical prior product code array. The present invention therefore achieves reduced redundancy (which in communications and storage channels means greater raw data throughput) with the same error correction capability as previous communications and storage devices and methods based on typical prior product codes.
According to a further feature of the preferred embodiment of the invention, the row and column codes C_{1} and C_{2}, as well as the intermediate code C_{1}.5, are each ReedSolomon codes. The apparatus of the preferred embodiment therefore can be constructed using conventional ReedSolomon encoders and decoders arranged in a new and unique manner to encode and decode the twodimensional code arrays of the invention which achieve reduced redundancy.
Because the present invention is based on probabilistic decoding, a more substantial improvement in code redundancy is achieved as compared to deterministic schemes such as disclosed in Kasahara. Kasahara's different objective of preserving worstcase correction capabilities also dictates different decoding strategies and apparatus.
Additional features and advantages of the invention will be made apparent from the following detailed description of a preferred embodiment which proceeds with reference to the accompanying drawings.
FIG. 1 is a generalized block diagram of a communications and/or storage system utilizing encoding and decoding for error correction.
FIG. 2 is a block diagram of a typical ReedSolomon encoder in the prior art that can be utilized for error correction encoding in the system of FIG. 1.
FIG. 3 is a block diagram of a typical ReedSolomon decoder in the prior art that can be utilized for error correction decoding in the system of FIG. 1.
FIG. 4 is a block diagram of a typical encoder in the prior art that can be utilized for error correction encoding in the system of FIG. 1 based on a twodimensional product code array.
FIG. 5 is a block diagram of a typical decoder in the prior art that can be utilized for error correction decoding in the system of FIG. 1 based on a twodimensional product code array.
FIG. 6 is a block diagram of an encoder that can be utilized in the system of FIG. 1 according to a preferred embodiment of the invention for error correction encoding based on a twodimensional code array with reduced redundancy.
FIG. 7 is a block diagram illustrating the twodimensional code array with reduced redundancy encoded accorded to the invention by the encoder of FIG. 6.
FIG. 8 is a block diagram of a decoder that can be utilized in the system of FIG. 1 according to the preferred embodiment of the invention for correcting burst errors based on a twodimensional code array with reduced redundancy.
FIG. 9 is a block diagram of a decoder that can be utilized in the system of FIG. 1 according to the preferred embodiment of the invention for correcting burst and random errors based on a twodimensional code array with reduced redundancy.
FIG. 1 shows a communications and/or information storage system 20 comprising an encoder 22 and a decoder 24 for error correction. Digital data is input at one end of system 20 by a data originator device 28 ("data source"), and output at an opposite end to a data consumer device 30 ("data sink"). The data is transferred between data originator 28 and data consumer 30 by a communications and/or storage channel 34 which potentially corrupts the data with random and/or burst errors. In the case of communications applications, channel 34 can comprise equipment for transmitting digital data between two sites, such as transmitters, receivers, tuners, transmission medium (wire, cable, or antennas), modulators, demodulators, and the like. In the case of information storage applications, channel 34 can comprise equipment for storing digital data, such as recording devices using magnetic recording media, optical recording media, semiconductor memory, and the like, including magnetic tape drives, compact disk drives, and computer memory chips. In some cases, particularly in storage applications, a same device can be utilized as both data originator 28 and data consumer 30. Additionally, channel 34 may include both communications and information storage equipment, such as in the case of a computer network where individual work stations store digital information on a shared file server accessed over a local area network.
During transfer on channel 34, the digital data may become corrupted due to noise, interference, media defects, or other causes. So that data received at data consumer 30 is not corrupted, encoder 22 encodes the data using error correction coding before the data enters channel 34. When the data exits channel 34, decoder 24 employs error correction operations based on the error correction code or codes employed by encoder 22 to restore the corrupted data.
In accordance with the invention, encoder 22 and decoder 24 of system 20 preferably are based on a twodimensional code array with reduced redundancy, such as that illustrated in FIG. 7 and described below. In a preferred embodiment of the invention, a reduced redundancy product code encoder 36 and decoder 38, 39 which are illustrated in FIGS. 6, 8, and 9 and described more fully below are employed as encoder 22 and decoder 24, respectively.
FIG. 2 shows a conventional implementation of a ReedSolomon encoder as an rstage feedback shift register encoder 40. This rstage feedbackshift register encoder 40 operates with block codes where the redundancy of the code is r=nk. Encoder 40 comprises an input 42 which accepts one input symbol at a time, and a plurality of shift register stages 44, labelled S_{0}, S_{1}, S_{2}, . . . , S_{r1}, each of which stores a symbol. Encoder 40 further comprises a plurality of generator polynomial coefficient multipliers 46, labelled g_{0}, g_{1}, g_{2}, . . . , g_{r1}, and adders 48 which correspond onetoone with stages 40. The quantities of the generator polynomial coefficients used in multipliers 50 are derived from the coefficients of the generator polynomial for the ReedSolomon code as shown in the following equation (1). ##EQU1## (g_{r} is assumed equal to 1.) The way in which the generator polynomial is determined is well known in the art (See, e.g. S. Wicker and V. Bhargava, ReedSolomon Codes and Their Applications, IEEE Press, New York, chapters 1, 5 and 10 (1994)). A feedback path 50 carries a feedback symbol which is a sum of a symbol from input 42 and a symbol in stage S_{r1}. The feedback symbol is multiplied by the respective generator coefficients of multipliers 46, then summed at adders 48 with the preceding stage's symbol to form an input symbol to each stage 44. The stages 44 of register 40 are synchronously clocked, causing the input symbols to be shifted into their respective stages each clock cycle.
In an encoding operation, a block of k data symbols is shifted one per clock cycle into encoder 40 at input 46. The resulting contents of stages 44 after the k data symbols are shifted into encoder 40 comprise an integer number r of check symbols. The r check symbols are combined with the k data symbols to form an nsymbol ReedSolomon code block.
FIG. 3 shows a prior art ReedSolomon decoder 60 which performs error correction on a possibly corrupted ReedSolomon code block 61. Decoder 60 comprises a syndrome generator 62, a key equation solver 64, and an error search and correction circuitry 66. Syndrome generator 62 forms an rsymbol syndrome 68 used in error detection and correction operations from an nsymbol ReedSolomon code block. A ReedSolomon encoder such as rstage feedbackshift register encoder 40 (FIG. 2) also can be utilized as syndrome generator 62. When utilized as syndrome generator 62, the nsymbol ReedSolomon code block (comprising k data symbols and r check symbols which have been sent through noisy channel 34 (FIG. 1)) is shifted into encoder 40 at input 46 (FIG. 2). After shifting in all nsymbols of the code block, the rsymbols contained in stages 44 (FIG. 2) form a "syndrome." A nonzero syndrome detects that the nsymbol code block is corrupt. An allzero syndrome indicates that the code block is not corrupted with a probability of 1ε, where ε is a number that decreases exponentially with r_{1}. In general, ε is proportional to q^{r}.sbsp.1. The probability therefore is generally proportional to 1q^{r}.sbsp.1.
The syndrome also can be further processed to perform erasure and full error correction. The illustrated decoder 60 performs full error correction. Key equation solver 64 processes syndrome 68 in a wellknown manner to form an error locator polynomial 70 and an error evaluator polynomial 71. Error locator and evaluator polynomials 7071 are input to error search and correction circuitry 66 along with corrupted input code block 61. Again using conventional techniques, error search and correction circuitry 66 utilizes error locator and evaluator polynomials 7071 to recover any corrupted symbols (shown with shading in FIG. 3), and outputs the corrected code block 74. The original k data symbols can then be extracted from the output code block 74 by omitting the r check symbols from code block 74.
Rstage feedbackshift register encoder 40 illustrated in FIG. 2 is one of many known implementations of ReedSolomon encoders. Other implementations of ReedSolomon encoders and decoders are described in S. Wicker and V. Bhargava, ReedSolomon Codes and Their Applications, IEEE Press, New York, chapters 1, 5 and 10 (1994), which is incorporated herein by reference; and in G. Seroussi, A Systolic ReedSolomon Encoder, 37 IEEE Transactions on Information Theory 12171220 (1991), which is incorporated herein by reference. These various conventional ReedSolomon encoders and decoders can be used as components of encoders and decoders based on twodimensional code arrays such as the conventional product code encoder and decoder illustrated in FIGS. 4 and 5, and the reduced redundancy product code encoder 36, and decoders 3839 (FIGS. 6, 8 and 9) according to the preferred embodiment of the invention.
FIGS. 4 and 5 show a typical prior art product code encoder 80 (FIG. 4) and decoder 82 (FIG. 5). Product code encoder 80 and decoder 82 are based on a twodimensional code array referred to as a product code. The product code generally utilizes two ReedSolomon codes, a first code C_{1} which is applied to its rows, and a second code C_{2} which is applied to its columns.
With reference to FIG. 4, product code encoder 80 forms the product code array by applying the C_{1} code to rows of a raw data block of k_{1} by k_{2} symbols, then applying the C_{2} code to columns of the codes resulting from application of the first code C_{1}. Raw data 87 to be encoded is stored in k_{2} rows having k_{1} symbols each of an input array buffer 86. Row processing circuitry 88 comprising a row encoder 90 and a row sequencer 92 apply the C_{1} code to the rows of raw data in input array buffer 86. Row encoder 90 is a ReedSolomon encoder, such as ReedSolomon encoder 40 (FIG. 2), which encodes with a redundancy r_{1}. Row sequencer 92 inputs the raw data rowbyrow from input array buffer 86 to row encoder 90. Row encoder 90 processes each row of k_{1} raw data symbols 87 to form r_{1} check symbols 93 for the row as described above. The k_{1} raw data symbols 87 and r_{1} check symbols 93 of each row form a C_{1} code of length n, symbols which is stored by row processing circuitry 80 in an intermediate array buffer 94.
Column processing circuitry 98 comprising a column encoder 100 and column sequencer 102 apply the C_{2} code to the columns of the C_{1} codes (consisting of raw data 87 and C_{1} check symbols 93) in intermediate array buffer 94. Column encoder 100 is ReedSolomon encoder, such as ReedSolomon encoder 40 (FIG. 2), which encodes with a redundancy r_{2}. Column sequencer 102 inputs the C_{1} codes columnbycolumn to column encoder 100. Column encoder 100 processes each column consisting of k_{2} symbols to form r_{2} check symbols 103, which are stored along with the columns in an output array buffer 104. The contents of output array buffer 104 after all columns are encoded is the product code array.
In some implementations of product code encoder 80, a single array buffer is employed as each of input array buffer 86 intermediate array buffer 94 and output array buffer 104. In such case, row and column processing circuitry 88, 98 operate on the data in place, rather than transferring the data between buffers as it is encoded. Further, in alternative implementations of product code encoder 80, the order of the row and column processing circuitry 88, 98 can be reversed while still producing the same product code array.
Referring now to FIG. 5, product code decoder 82 performs error correction on a product code array formed by product code encoder 80, based on a strategy utilizing code C_{1} to detect corrupted rows of the product code array and code C_{2} to correct erasure of the corrupted rows. The product code array, which potentially has corrupted rows 109, is initially stored in an input array buffer 110 upon receipt from channel 34 (FIG. 1). Row processing circuitry 112 is employed by product code decoder 82 to detect any corrupted rows 109 of the product code array in input array buffer 110. Row processing circuitry 112 comprises a row decoder 114 and row sequencer 116. Row decoder 114 is a ReedSolomon decoder similar to that shown in FIG. 3, which is adapted for error detection based on the C_{1} code. Row sequencer 116 inputs the product code array row by row from input array buffer 110 to row decoder 114. For each row, row decoder 114 forms an r_{1} symbol syndrome, and identifies the row as corrupt if the syndrome is nonzero. Row decoder 114 then forms a list ("corrupted rows list") 117 identifying which rows were detected as being corrupted. After processing by row processing circuitry 112, the product code array is stored unchanged in an intermediate array buffer 118.
Product code decoder 82 further comprises a column processing circuitry 120 which it employs to correct erasure of the corrupted rows detected by row processing circuitry 112. Column processing circuitry 120 comprises a column decoder 122 and a column sequencer 124. Column decoder 122 is a ReedSolomon decoder similar to that shown in FIG. 3, which is adapted for erasure correction operations based on the C_{2} code. Column sequencer 124 inputs the product code array column by column from intermediate array buffer 118 to column decoder 122. The corrupted rows list 117 also is input from row decoder 114 to column decoder 122. With the corrupted rows list 117, column decoder 122 declares each of the corrupted rows 109 identified in list 117 to be erased. For each column of the product code array, column decoder 122 then corrects erasures in the column by forming a syndrome of length r_{2} symbols for the column, and processing the syndrome to correct each symbol in the column from the erased rows. Column decoder 122 stores the corrected columns into an output array buffer 126. As a result of the processing by row and column processing circuitry 112, 120, output array buffer 126 contains the product code array with each of corrupted rows 109 corrected. Product array decoder 82 also can be implemented with a single array buffer employed as each of input array buffer 110, intermediate array buffer 118, and output array buffer 126, with the product code array being processed in place.
As discussed in the background of the invention above, the n_{1} ×n_{2} product code array formed by prior art product array encoder 80 has redundancy n_{1} r_{2} +n_{2} r_{1} r_{1} r_{2} symbols. With this redundancy, prior art product array decoder 82 can detect whether any of the product code array's n_{2} rows are corrupted. (Row decoder 90 forms a separate syndrome for each row, which identifies the row as being corrupted if the syndrome is nonzero.) Product array decoder 82, however, can only correct up to r_{2} corrupted rows which have been identified as being corrupted. (Erasure correction by column decoder 100 is limited to correcting r_{2} symbols per column of the product code array.) The cost in redundancy to identify more than r_{2} rows as being corrupted therefore is wasted.
FIGS. 6, 8, and 9 show reduced redundancy product code encoder 36 (FIG. 6) and decoders 38, 39 (FIGS. 8 and 9) according to a preferred embodiment of the invention. Encoder 36 and decoders 38, 39 are based on a twodimensional product code array 130 shown in FIG. 7 which utilizes an additional intermediate code C_{1}.5 to achieve a reduced redundancy (i.e. (n_{1} r_{2} +r_{1} r_{2}) in the preferred embodiment) as compared to typical prior art product array code codecs (i.e. encoder/decoders) while providing equivalent capability for burst and random error correction.
Code C_{1}.5 has block length n_{2} and redundancy 2r_{2}. Additionally, in the preferred embodiment, code C_{1}.5 is designed to be a subcode of C_{2}, i.e. code blocks of C_{1}.5 contain the r_{2} redundant check symbols computed as for C_{2}, plus an additional set of r_{2} check symbols. Consequently, code blocks encoded with code C_{2} already satisfy half of the redundancy constraints necessary to be valid code blocks under C_{1}.5. This overlap between C_{1}.5 and C_{2} contributes to the redundancy reduction, and can also simplify the design of the encoding and decoding circuitry, since parts of the circuitry used for C_{2} also can be used for C_{1}.5. In the encoders/decoders of FIGS. 6, 8, and 9, we assume that the above relation exists between C_{1}.5 and C_{2}.
Referring now to FIGS. 6 and 7, reduced redundancy product code encoder 36 (FIG. 6) encodes raw data blocks 132, 134 (FIG. 7) to form reduced redundancy product code array 130 (FIG. 7). Encoder 36 comprises column processing circuitry 140 to apply a ReedSolomon code C_{2} with redundancy r_{2} symbols on columns of product code array 130, row processing circuitry 142 to apply a ReedSolomon code C_{1} with redundancy r_{1} symbols to rows of product code array 130, column processing circuitry 144 to apply an intermediate ReedSolomon code C_{1}.5 with redundancy r_{1}.5 symbols to row checks formed by row processing circuitry 142, and an XOR adder 146. Encoder 36 additionally comprises an input array buffer 150, and intermediate array buffer 151, an output array buffer 152, and checks array buffers 154155 in which product code array 130 and check symbols are stored. Input, intermediate, and output array buffers 150152 can be physically implemented as a single buffer memory in which product code array 130 is encoded in place.
Encoding of product code array 130 by encoder 36 begins by input array buffer 150 initially storing raw data symbols which are to be encoded. In the preferred embodiment, raw data is stored into input array buffer 50 as raw data blocks 132, 134. Raw data block 132 fills a k_{1} by k_{2} symbol portion of product code array 130, while raw data block 134 fills an r_{1} by (n_{2} 2r_{2}) symbol portion for a total of (k_{1} k_{2} +r_{1} (n_{2} 2r_{2})) raw data symbols. Raw data symbols can be stored into raw data blocks 132, 134 in various ways, including, for example, sequentially as n_{1} 2r_{2} rows of n_{1} symbols each plus r_{2} rows of k_{1} symbols each.
Next, column processing circuitry 140 encodes columns of raw data block 132 with the C_{2} column code to form an array of C_{2} column code checks 160 (FIG. 7) with dimensions k_{1} by r_{2} symbols. For encoding with the C_{2} code, column processing circuitry 140 comprises a column encoder 162 and a column sequencer 164. Column encoder 162 is a ReedSolomon encoder which can be suitably implemented as a feedbackshift register encoder with r_{2} stages such as illustrated in FIG. 2, or, alternatively, as a systolic array or other architecture described in S. Wicker and G. Seroussi. Column sequencer 164 inputs raw data block 132 column by column into column encoder 162. Column encoder 162 processes each of the k_{1} columns of data block 132 (each having length k_{2} symbols) to form the C_{2} column code checks 160. Column processing circuitry 140 outputs the C_{2} column code checks 160 to fill a k_{1} by r_{1} symbol portion of intermediate array buffer 151. A remaining r_{1} by 2r_{2} symbol portion 168 of intermediate array buffer 151 is cleared (i.e. filled with zeroes). (As an alternative to clearing portion 168, row processing circuitry 142 can process only the first k_{1} symbols of the last 2r_{2} rows of product code array 130 when encoding with the C_{1} code as described immediately below.)
Row processing circuitry 142 encodes rows of raw data blocks 132, 134 and C_{2} column code checks 160 in intermediate array buffer 151 to form an array of C_{1} row code checks (comprising portions 170171) with dimensions r_{1} by n_{2} symbols. For encoding with the C_{1} code, row processing circuitry 142 comprises a row encoder 172 and a row sequencer 174. Row encoder 172 is a ReedSolomon encoder which can be suitably implemented as a feedbackshift register encoder with r_{1} stages such as illustrated in FIG. 2, or, alternatively, as a systolic array or other architecture described in Appendices A and B. Row sequencer 174 inputs symbols from intermediate array buffer 151 row by row into row encoder 172. Row encoder 172 processes each of the n_{2} rows (which each comprise n_{1} symbols) to form C_{1} row code checks which are stored in C_{1} checks array buffer 154.
C_{1} checks array buffer 154 inputs a portion 170 (having dimensions r_{1} by n_{2} 2r_{2} symbols) of C_{1} row code checks array which correspond to the first n_{2} 2r_{2} rows of product code array 130 (i.e. each of the full rows of n_{1} raw data symbols) into column processing circuitry 144. A remaining portion 171 (having dimension r_{1} by 2r_{2} symbols) of C_{1} code checks array corresponding to the last 2r_{2} rows of product code array 130 are saved in the last 2r_{2} rows of buffer 154.
Column processing circuitry 144 encodes columns of portion 170 of C_{1} row code checks array in buffer 154 to form an array 155 of C_{1}.5 column code checks with dimensions r_{1} by 2r_{2} symbols. For encoding with the C_{1}.5 code, column processing circuitry 144 comprises a column encoder 192 and a column sequencer 194. Column encoder 192 is a ReedSolomon encoder which can be suitably implemented as a feedbackshift register encoder with r_{1}.5 stages such as illustrated in FIG. 2, or, alternatively, as a systolic array or other architecture described in S. Wicker and Seroussi. Column sequencer 194 inputs symbols from C_{1} checks array portion 170 in buffer 154 column by column into column encoder 192. Column encoder 192 processes each of the r_{1} columns (which each comprise n_{2} 2r_{2} symbols) to form the C_{1}.5 column code checks array. Column processing circuitry 144 output the C_{1}.5 column code checks array into C_{1}.5 checks array buffer 155.
XOR adder 146 sums by bitwise exclusiveor operation the C_{1}.5 column code checks array in buffer 155 with portion 171 of C_{1} row code checks array in buffer 154 symbol by symbol to form an array 198 of row code checks with dimensions of r_{1} by 2r_{2} symbols. The row code checks array 198 is stored into output array buffer 152 with raw data block 132, 134 and C_{2} column code checks 160. The resulting contents of output array buffer 152 forms reduced redundancy product code array 130 (FIG. 7).
The redundancy portion of product code array 130 constitutes only the C_{2} column code checks 160 and row code checks 198, which consist of a total of n_{1} r_{2} +r_{1} r_{2} symbols. This is r_{1} (n_{2} 2r_{2}) symbols fewer than the redundancy of the product code array formed by prior art product array encoder 80 (which has a redundancy of n_{1} r_{2} +n_{2} r_{1} r_{1} r_{2} symbols). Reduced redundancy product code encoder 36 thus realizes a significant savings in redundancy over prior art product code encoder 80 (FIG. 5) for product codes of equal dimensions. With typical product code dimensions of n_{1} =128, r_{1} =12, n_{2} =98, and r_{2} =8, for example, the savings in redundancy realized by reduced redundancy product code encoder 36 is shown in the following Table 2.
TABLE 2______________________________________Comparison of Prior Art and ReducedRedundancy Product Code Encoders. Reduced Redundancy Prior Art Product Product Code Code Encoder 80 Encoder 36______________________________________Product Code 12544 12544LengthProduct Code 2104 1120RedundancyRedundancy/ 16.8% 8.9%LengthRedundancy/ 20.2% 9.8%Raw Data______________________________________
Referring now to FIG. 8, reduced redundancy product code decoder 38 decodes product code array 130 (FIG. 7) formed by reduced redundancy product code encoder 36 (FIG. 6) to correct burst errors introduced in transferring product code array 130 through channel 34 (FIG. 1). Decoder 38 utilizes the C_{1} row code and C_{1}.5 intermediate code to locate up to r_{2} rows ("corrupted rows") 205 of product code array 130 that were corrupted during transfer through channel 34. Decoder 38 then utilizes the C_{2} column code for erasure correction of the corrupted rows 205. Reduced redundancy product code decoder 38 therefore provides error correction capability equivalent to prior art product array decoder 82 (FIG. 5) with the reduced redundancy of product code array 130.
To process product code array 130 utilizing the C_{1}, C_{1}.5, and C_{2} codes, decoder 38 comprises a row processing circuitry 210, an intermediate processing circuitry 212, and a column processing circuitry 214. Decoder 38 further comprises an input array buffer 220, an output array buffer 221, and a syndrome array buffer 222. A single physical buffer can be employed as both input and output array buffers 220221, by processing the product code array in place. After being transferred through channel 34, product code array 130 is initially stored into input array buffer 220.
Row processing circuitry 210 processes rows of the product code array in input array buffer 220 with the C_{1} code to form a syndrome array. To form the syndrome array, row processing circuitry 210 comprises a row decoder 230 and row sequencer 232. Row decoder 230 is a ReedSolomon encoder used as a syndrome generator (as described above with reference to FIG. 3) which can be suitably implemented as a feedbackshift register encoder with r_{1} stages such as illustrated in FIG. 2, or, alternatively, as a systolic array or other architecture described in S. Wicker and Seroussi. Row sequencer 232 inputs symbols from input array buffer 220 row by row into row decoder 230. Row decoder 230 processes each of the n_{2} rows (which comprise n_{1} symbols each) of the product array to yield a corresponding syndrome having r_{1} symbols. Row processing circuitry 210 outputs the syndromes into rows of syndrome array buffer 222 corresponding to rows of input array buffer 220 to form the syndrome array.
Intermediate processing circuitry 212 processes columns of the syndrome array according to the C_{1}.5 code to locate corrupted rows 205 of the product array. Intermediate processing circuitry 212 comprises a syndrome array decoder 240 and a column sequencer 242. Syndrome array decoder 240 is a ReedSolomon decoder which can be implemented similarly to decoder 60 of FIG. 3 with a syndrome generator and key equation solver. Column sequencer 242 inputs symbols from syndrome array buffer 222 into syndrome array decoder 240 one column at a time. Syndrome array decoder 240 then forms an r_{1}.5 symbol syndrome for each column of the syndrome array, and processes the C_{1}.5 symbol syndrome to determine error locations. The rows of the syndrome array in which errors are located correspond to corrupted rows 205 of the product array in input array buffer 220.
In the case of burst errors, each column of the syndrome array is likely to have errors in the same rows of the syndrome array. Consequently, most of corrupted rows 205 will be located in processing just one column of the syndrome array. Further, there is a high likelihood that all corrupted rows 205 will be located after processing just a few columns. Accordingly, in some embodiments of the invention, intermediate processing circuitry 212 can process only some of the r_{1} columns of the syndrome array (two or three columns for example) so as to speed up the decoding process at the sacrifice of a very small chance of failing to detect some of corrupted rows 205. Alternatively, corrupted rows 205 can be located using only the first few columns, and the rest of the columns can be used to verify their locations. When a discrepancy is found, an additional column is fully processed. As a result of processing the syndrome array columns, syndrome array decoder 240 produces a corrupted rows list 249 which is output to column processing circuitry 214.
Column processing circuitry 214 performs erasure correction of corrupted rows 205 in the product array based on corrupted rows list 249. Column processing circuitry 214 comprises a column decoder 250 and a column sequencer 252. Column decoder 250 is a ReedSolomon decoder which can be implemented similarly to decoder 60 shown in FIG. 3 with a syndrome generator, key equation solver, and error search and correction circuitry. Column sequencer 252 inputs the product code array column by column from input array buffer 220 to column decoder 250. Corrupted rows list 249 also is input to column decoder 250. With corrupted rows list 249, column decoder 250 declares each of the corrupted rows 205 identified in list 249 to be erased. For each column of the product code array, column decoder 250 then corrects erasures in the column by forming a syndrome of length r_{2} symbols for the column, and processing the syndrome to correct each symbol from the erased rows in the column. Column decoder 250 stores the corrected columns into an output array buffer 221. As a result of processing by row, intermediate, and column processing circuitry 210, 212, and 214, output array buffer 221 contains the product code array with each of corrupted rows 205 corrected (with very high probability).
Referring now to FIG. 9, decoder 38 is modified in reduced redundancy product code decoder 39 to decode product code array 130 (FIG. 7) to correct both burst and random errors introduced in transferring product code array 130 through channel 34 (FIG. 1). As in decoder 38, decoder 39 utilizes the C_{1} row code and C_{1}.5 intermediate code to locate up to r_{2} corrupted rows 205 of product code array 130, then utilizes the C_{2} column code for erasure correction of the corrupted rows 205. Decoder 39 additionally utilizes the C_{1}.5 intermediate code and C_{1} row code to correct random errors 258 in product code array 130. The reduced redundancy of product code array 130 therefore can be used to provide both random and burst error protection.
In addition to row, intermediate, and column processing circuitry 210, 212, 214 and buffers 220222, reduced redundancy product code decoder 39 comprises an intermediate array buffer 260 and a corrected syndrome array buffer 260. In some embodiments of the invention, syndrome array buffer 222 and corrected syndrome array buffer 262 can be implemented as a single physical buffer, and input array buffer 220, output array buffer 221, and intermediate array buffer 260 can all be implemented as a second single physical buffer.
In decoder 39, row processing circuitry 210 encodes rows of product code array 130 in input array buffer 220 with the C_{1} row code to form a syndrome array. Row processing circuitry 210 outputs the syndrome array to syndrome array buffer 222. Intermediate processing circuitry 212 processes columns of the syndrome array in syndrome array buffer 222 with the C_{1}.5 intermediate code to yield corrupted row list 249, and to correct errors in the syndrome array. Intermediate processing circuitry 212 outputs corrupted rows list 249 to column processing circuitry 214, and the corrected syndrome array to corrected syndrome array buffer 262.
Row processing circuitry 210 utilizes the corrected syndrome array to correct random errors 258 in rows of the product code array in input array buffer 220. Row decoder 230 of row processing circuitry is implemented similarly to decoder 60 of FIG. 3, with a key equation solver and error search and correction circuitry. With these components of row decoder 230, row processing circuitry 210 locates and corrects random errors 258, and outputs the resulting product code array to intermediate array buffer 260.
Column processing circuitry 214 then processes columns of the product code array in intermediate array buffer 260 with the C_{2} column code for erasure correction of corrupted rows 205 identified in corrupted rows list 249. The product code array with both random and burst errors 205, 258 corrected is output to output array buffer 221.
Having described and illustrated the principles of our invention with reference to a preferred embodiment, it will be recognized that the preferred embodiment can be modified in arrangement and detail without departing from such principles. In view of the many possible embodiments to which the principles of our invention may be applied, it should be recognized that the detailed embodiments are illustrative only and should not be taken as limiting the scope of our invention. Rather, we claim as our invention all such embodiments as may come within the scope and spirit of the following claims and equivalents thereto.
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JP3737204B2 (en)  20060118  grant 
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