US5650965A - Method of narrowing flash memory device threshold voltage distribution - Google Patents

Method of narrowing flash memory device threshold voltage distribution Download PDF

Info

Publication number
US5650965A
US5650965A US08584601 US58460196A US5650965A US 5650965 A US5650965 A US 5650965A US 08584601 US08584601 US 08584601 US 58460196 A US58460196 A US 58460196A US 5650965 A US5650965 A US 5650965A
Authority
US
Grant status
Grant
Patent type
Prior art keywords
cell
word
cells
erased
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US08584601
Inventor
Roger R. Lee
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Round Rock Research LLC
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • G11C16/3409Circuits or methods to recover overerased nonvolatile memory cells detected during erase verification, usually by means of a "soft" programming step
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3404Convergence or correction of memory cell threshold voltages; Repair or recovery of overerased or overprogrammed cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/344Arrangements for verifying correct erasure or for detecting overerased cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/344Arrangements for verifying correct erasure or for detecting overerased cells
    • G11C16/3445Circuits or methods to verify correct erasure of nonvolatile memory cells

Abstract

A method of erasing memory cells in a sector of a flash programmable memory device, the sector having a plurality of word lines and a plurality of memory cells along each of the word lines, each of the cells in the sector having a source region common to all cells in the sector, the method comprising a first step of erasing the memory cells in the sector simultaneously, then reading a first cell along a first word line to determine if the first cell is under-erased. Responsive to the first cell being erased, a second cell along the first word line is read to determine if the second cell is under-erased. Responsive to the second cell being under-erased, a negative first voltage is applied to the first word line, a positive second voltage is applied to the common source of the cells in the sector, and a positive third voltage is applied to the plurality of word lines except the first word line.

Description

This is a continuation-in-part of application Ser. No. 08/348,649 filed Dec. 1, 1994, which was a continuation-in-part of application Ser. No. 08/152,809, filed Nov. 15, 1993, issued Jun. 13, 1995 as U.S. Pat. No. 5,424,993.

FIELD OF THE INVENTION

The invention relates to semiconductor memory devices, and more specifically to a method for erasing a sector of a flash memory device.

BACKGROUND OF THE INVENTION

In recent years flash memory has emerged as an important category of memory device, as flash devices combine high density with electrical erasability. Flash memories comprise a plurality of one-transistor flash electrically-erasable programmable read-only memory (EEPROM) cells formed on and within a semiconductor substrate. Each cell comprises a P-type conductivity substrate, an N-type conductivity source region formed within the substrate, and an N-type conductivity drain region also formed within the substrate. A floating gate is separated from the substrate by a dielectric layer. A second dielectric layer separates a control gate from the floating gate. A P-type channel region within the substrate is interposed between the source and drain. The control gate of the cell is formed from a word line, and a plurality of cells are along each word line such that one word line controls a plurality of cells. A digit line interconnects the drain regions of a plurality of cells.

Various voltages are associated with a flash cell, as shown in FIG. 1. To program a flash cell the drain region and the control gate are raised to predetermined potentials above the potential applied to the source region. For example 12 volts is applied to the control gate, 0.0 volts is applied to the source, and 6.0 volts is applied to the drain. These voltages produce "hot electrons" which are accelerated from the substrate across the dielectric layer to the floating gate. This hot electron injection results in an increase of the threshold voltage (the voltage which must be applied between the source, drain, and control gate for the cell to conduct) by approximately two to four volts.

To erase a flash cell a high positive potential, for example 12 volts, is applied to the source region, the control gate is grounded, and the drain is allowed to float. These voltages are applied for a timed period, and the longer the period the more the cell becomes erased. A strong electric field develops between the floating gate and the source region, and negative charge is extracted from the floating gate to the source region, for example by Fowler-Nordheim tunneling. If an unprogrammed flash EEPROM cell in an array of such cells is repeatedly erased under these conditions, the floating gate will eventually acquire a more positive potential. Consequently, even with the control gate being grounded the cell will always be turned on. This causes column leakage current thereby preventing the proper reading of any other cell in the column of the array containing this cell as well as making programming of the other cells on the same column increasingly more difficult. This condition, referred to as "over-erase," is disadvantageous since the data programming characteristics of the memory cell is deteriorated so as to cause endurance failures.

To determine if a cell is programmed, the magnitude of the read current is measured, for example by grounding the source, applying about 5.0 volts to the control gate, and applying between 1.0 and 2.0 volts to the drain. Under these conditions, an unprogrammed cell will conduct at a current level of about 50 to 100 microamps. The programmed cell will have considerably less current flowing.

To change the content of a flash memory device all cells are programmed and then erased and then selected cells are programmed. By first programming all of the cells and then erasing all cells, over-erasure of any unprogrammed cells is reduced. An over-erase condition must be avoided to prevent a cell from functioning as a depletion transistor in the read mode of operation. During a read mode of an over-erased memory cell an entire column of a sector can be disabled.

An advantage of a flash memory device is that an entire sector of cells can be erased simultaneously as the sources for each cell within the sector are tied together. Some cells, however, erase more quickly than others resulting from manufacturing variations from cell to cell such as the dielectric thickness between the substrate and the floating gate. The flash erase cycle must therefore be optimized for the "average" cell of the entire sector. Some cells will be slightly over-erased while some remain slightly under-erased, and thus a variation in the threshold voltage of the cells in the sector results. A method of erasing cells within a sector which provides for a more uniform threshold voltage distribution would be desirable.

SUMMARY OF THE INVENTION

A method of erasing memory cells in a sector of a memory device, the sector having a plurality of word lines and a plurality of memory cells along each of the word lines, comprises a first step of erasing the memory cells in the sector simultaneously. Next, subsequent to the step of erasing, a first cell along a first word line is read to determine if the first cell is under-erased. If the first cell is erased, a second cell along the first word line is read to determine if it is under-erased. Responsive to the second cell being under-erased, only the plurality of cells along the first word line are further erased.

Objects and advantages will become apparent to those skilled in the art from the following detailed description read in conjunction with the appended claims and the drawings attached hereto.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a table showing the voltages associated with a flash memory device, and FIG. 2 is a flow chart describing one embodiment of the inventive method.

DETAILED DESCRIPTION OF THE INVENTION

A memory device such as a flash memory device typically comprises a sector having a plurality of word lines and a plurality of memory cells along each word line. One embodiment of the inventive method for erasing memory cells in a sector of a memory device, as described in FIG. 2, comprises programming the memory cells in the sector, then erasing the memory cells in the sector simultaneously. Subsequently, a first word line is selected, and a first cell along the first word line is selected and read to determine if the first cell is under-erased.

It should be noted that for purposes of this disclosure, an under-erased cell is a cell which functions as a programmed cell when it is expected to function as an unprogrammed cell or as an erased cell. For example, using the cell arrangement described in the background section, if a cell is properly erased it should conduct (i.e. "turn on," "trip," or conduct across its channel between its source and drain) when the read voltages are applied. If a cell which is erased does not conduct when the read voltages are applied, it is considered to be under-erased.

With this embodiment of the invention, if the first cell is read and is determined to be under-erased, the first cell and the other cells along the first word line in the sector are further erased. While the cells along the first word line are further erased the remaining cells in the sector along the other word lines are maintained (not further erased). The first cell is again read to determine if the erasure has been successful. If the first cell remains under-erased, it is further erased. This "erase-then-read" process continues until the cell is determined to be erased. Once the first cell is determined to be adequately erased, the second cell along the word line is similarly read and erased if required. Each cell along the first word line is similarly tested in turn. When all the cells along the first word line have been repaired and/or found to be adequately erased the cells along the second word line are read and repaired if necessary, then each cell, in turn, along the third and then the remaining word lines.

If the first cell is not under-erased no further erasure (i.e. repair) of the first cell is necessary, and the second cell along the first word line is read and repaired if necessary. After all cells along the first word line have been tested and repaired if necessary, the cells along the second and then the remaining word lines are tested and repaired if necessary.

It can be seen that as the test progresses along the word line each cell has a higher probability of being properly erased, as the cells along the word line have been further erased if any previous cells along its word line have been further erased. Erasing all cells along one word line is required because the sources are tied together.

The method of erasing can comprise various voltages on the word lines and the source lines, while the digit lines are allowed to float. A negative voltage can be applied to the first word line and, simultaneously, a voltage greater than or equal to 0.0 volts (a nonnegative voltage) is applied to the plurality of word lines except the first word line to maintain (not further erase) cells along those word lines. For example, about -10 volts can be applied to the first word line (the one having a cell therealong to be erased) while about +5 volts is applied to the plurality of word lines in the sector except the first word line. Simultaneously applying +5 volts to the source region of the cells in the sector would allow the cells along the first word line to be erased while the cells along the other word lines are maintained. These voltages can be applied for a timed interval, for example from about 0.1 millisecond to about 1.0 second, which may vary depending on the voltages applied to the word lines and the source regions.

By further erasing only those cells along the word line where an under-erased cell is detected, the cells along the remaining word lines are not over-erased while the under-erased cell is being further erased. It can be seen that the probability of over-erasing a cell in the sector is decreased over repair schemes which further erase every cell in the sector if one under-erased cell is to be repaired.

In an alternate embodiment, a cell which is determined to be under-erased is repaired but is not re-read to determine if it has been repaired. This embodiment would be possible when it is known that specific voltages applied to the word line and to the source of a cell for a time during a further erasure of the cell is adequate to ensure it functions as an erased cell.

The inventive memory device could conceivably be attached along with other devices to a printed circuit board, for example to a computer motherboard or as a part of a memory module used in a personal computer, a minicomputer, or a mainframe. The inventive device could further be useful in other electronic devices related to telecommunications, the automobile industry, semiconductor test and manufacturing equipment, consumer electronics, or virtually any piece of consumer or industrial electronic equipment. Further, the inventive method can be implemented on-chip, or as an external circuit.

While this invention has been described with reference to illustrative embodiments, this description is not meant to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as additional embodiments of the invention, will be apparent to persons skilled in the art upon reference to this description. For example, various voltages can be applied to the word lines and the sources while maintaining the spirit of the invention. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as fall within the true scope of the invention.

Claims (22)

What is claimed is:
1. A method of erasing memory cells in a sector of a memory device, said sector having a plurality of word lines and a plurality of memory cells along each of said word lines, said method comprising the following steps:
a) reading a first cell along a first word line to determine if said first cell is under-erased;
b) responsive to said first cell being erased, reading a second cell along said first word line to determine if said second cell is under-erased;
c) responsive to said second cell being under-erased, further erasing only said plurality of cells along said first word line.
2. The method of claim 1 further comprising the step of rereading said second cell to determine if said second cell remains under-erased subsequent to said step of further erasing.
3. The method of claim 2 further comprising reading a third cell to determine if said third cell is under-erased subsequent to said step of rereading said second cell.
4. The method of claim 1 further comprising the step of applying a negative voltage to said first word line and, simultaneously, applying a voltage greater than or equal to 0.0 volts to said plurality of word lines except said first word line during said step of further erasing.
5. The method of claim 1 further comprising the step of applying about -10V to said first word line, applying about +5V to a source of said first cell, and applying about +5V to said plurality of word lines except said first word line during said step of further erasing.
6. The method of claim 5 wherein said voltages are applied for between about 0.1 millisecond to about 1.0 second.
7. The method of claim 1 further comprising erasing said memory cells in said sector simultaneously prior to said step of reading said first cell.
8. The method of claim 7 further comprising the step of programming said memory cells in said sector prior to said step of erasing said memory cells.
9. A method of erasing memory cells in a sector of a memory device, said memory cells each having a source, a drain, and a control gate, said sector having a plurality of word lines and a plurality of memory cells along each of said word lines, said method comprising the following steps:
a) applying a read voltage to a source, a drain, and a control gate of a first cell along a first word line to determine if said first cell conducts;
b) responsive to said first cell conducting, reading a second cell along said first word line to determine if said second cell conducts;
c) responsive to said second cell not conducting, further erasing only said plurality of cells along said first word line.
10. The method of claim 9 further comprising the step of rereading said second cell to determine if said second cell conducts subsequent to said step of further erasing.
11. The method of claim 10 further comprising reading a third cell to determine if said third cell conducts subsequent to said step of rereading said second cell.
12. The method of claim 9 further comprising the step of applying a negative voltage to said first word line and, simultaneously, applying a voltage greater than or equal to 0.0 volts to said plurality of word lines except said first word line during said step of further erasing.
13. The method of claim 9 further comprising the step of applying about -10V to said first word line, applying about +5V to a source of said first cell, and applying about +5V to said plurality of word lines except said first word line during said step of further erasing.
14. The method of claim 13 wherein said voltages are applied for between about 0.1 millisecond to about 1.0 second.
15. The method of claim 9 further comprising erasing said memory cells in said sector simultaneously prior to said step of reading said first cell.
16. The method of claim 15 further comprising the step of programming said memory cells in said sector prior to said step of erasing said memory cells.
17. A method of erasing memory cells in a sector of a flash programmable memory device, said sector having a plurality of word lines and a plurality of memory cells along each of said word lines, each of said cells in said sector having a source region common to all cells in said sector, said method comprising the following steps:
a) erasing said memory cells in said sector simultaneously;
b) subsequent to said step of erasing, reading a first cell along a first word line to determine if said first cell is under-erased;
c) responsive to said first cell being erased, reading a second cell along said first word line to determine if said second cell is under-erased;
d) responsive to said second cell being under-erased, applying a negative first voltage to said first word line, applying a positive second voltage to said common source of said cells in said sector, and applying a positive third voltage to said plurality of word lines except said first word line.
18. The method of claim 17 wherein said second voltage is about 5.0 volts.
19. The method of claim 18 wherein said third voltage is about 5.0 volts.
20. The method of claim 19 wherein said first voltage is about -10.0 volts.
21. The method of claim 20 further comprising the step of rereading said second cell to determine if said second cell remains under-erased subsequent to said step of further erasing.
22. The method of claim 21 further comprising reading a third cell to determine if said third cell is under-erased subsequent to said step of rereading said second cell.
US08584601 1993-11-15 1996-01-11 Method of narrowing flash memory device threshold voltage distribution Expired - Lifetime US5650965A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
US08152809 US5424993A (en) 1993-11-15 1993-11-15 Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device
US08348649 US5633823A (en) 1994-12-01 1994-12-01 Method of narrowing flash memory device threshold voltage distribution
US08584601 US5650965A (en) 1993-11-15 1996-01-11 Method of narrowing flash memory device threshold voltage distribution

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08584601 US5650965A (en) 1993-11-15 1996-01-11 Method of narrowing flash memory device threshold voltage distribution

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US08348649 Continuation-In-Part US5633823A (en) 1994-12-01 1994-12-01 Method of narrowing flash memory device threshold voltage distribution

Publications (1)

Publication Number Publication Date
US5650965A true US5650965A (en) 1997-07-22

Family

ID=26849886

Family Applications (1)

Application Number Title Priority Date Filing Date
US08584601 Expired - Lifetime US5650965A (en) 1993-11-15 1996-01-11 Method of narrowing flash memory device threshold voltage distribution

Country Status (1)

Country Link
US (1) US5650965A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963479A (en) * 1996-12-28 1999-10-05 Hyundai Electronics Industries, Co., Ltd. Method of erasing a flash memory cell and device for erasing the same
US6414351B2 (en) 1998-09-03 2002-07-02 Micron Technology, Inc. Mini FLASH process and circuit

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4279024A (en) * 1978-06-30 1981-07-14 Siemens Aktiengesellschaft Word-by-word electrically reprogrammable nonvolatile memory
US4805151A (en) * 1986-05-13 1989-02-14 Mitsubishi Denki Kabushiki Kaisha Nonvolatile semiconductor memory device
US5163021A (en) * 1989-04-13 1992-11-10 Sundisk Corporation Multi-state EEprom read and write circuits and techniques
US5233562A (en) * 1991-12-30 1993-08-03 Intel Corporation Methods of repairing field-effect memory cells in an electrically erasable and electrically programmable memory device
US5237535A (en) * 1991-10-09 1993-08-17 Intel Corporation Method of repairing overerased cells in a flash memory
US5268870A (en) * 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US5272669A (en) * 1991-02-20 1993-12-21 Sundisk Corporation Method and structure for programming floating gate memory cells
US5335198A (en) * 1993-05-06 1994-08-02 Advanced Micro Devices, Inc. Flash EEPROM array with high endurance
US5424993A (en) * 1993-11-15 1995-06-13 Micron Technology, Inc. Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4279024A (en) * 1978-06-30 1981-07-14 Siemens Aktiengesellschaft Word-by-word electrically reprogrammable nonvolatile memory
US4805151A (en) * 1986-05-13 1989-02-14 Mitsubishi Denki Kabushiki Kaisha Nonvolatile semiconductor memory device
US5268870A (en) * 1988-06-08 1993-12-07 Eliyahou Harari Flash EEPROM system and intelligent programming and erasing methods therefor
US5163021A (en) * 1989-04-13 1992-11-10 Sundisk Corporation Multi-state EEprom read and write circuits and techniques
US5272669A (en) * 1991-02-20 1993-12-21 Sundisk Corporation Method and structure for programming floating gate memory cells
US5237535A (en) * 1991-10-09 1993-08-17 Intel Corporation Method of repairing overerased cells in a flash memory
US5233562A (en) * 1991-12-30 1993-08-03 Intel Corporation Methods of repairing field-effect memory cells in an electrically erasable and electrically programmable memory device
US5335198A (en) * 1993-05-06 1994-08-02 Advanced Micro Devices, Inc. Flash EEPROM array with high endurance
US5424993A (en) * 1993-11-15 1995-06-13 Micron Technology, Inc. Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5963479A (en) * 1996-12-28 1999-10-05 Hyundai Electronics Industries, Co., Ltd. Method of erasing a flash memory cell and device for erasing the same
US6414351B2 (en) 1998-09-03 2002-07-02 Micron Technology, Inc. Mini FLASH process and circuit
US6551878B2 (en) 1998-09-03 2003-04-22 Micron Technology, Inc. Mini flash process and circuit

Similar Documents

Publication Publication Date Title
US5343434A (en) Nonvolatile semiconductor memory device and manufacturing method and testing method thereof
US6169693B1 (en) Self-convergence of post-erase threshold voltages in a flash memory cell using transient response
US5712819A (en) Flash EEPROM system with storage of sector characteristic information within the sector
US5550772A (en) Memory array utilizing multi-state memory cells
US5546341A (en) Nonvolatile semiconductor memory
US7310271B2 (en) Program-verify method of non-volatile memory device
US5142495A (en) Variable load for margin mode
US5467306A (en) Method of using source bias to increase threshold voltages and/or to correct for over-erasure of flash eproms
US6331951B1 (en) Method and system for embedded chip erase verification
US5438544A (en) Non-volatile semiconductor memory device with function of bringing memory cell transistors to overerased state, and method of writing data in the device
US6831858B2 (en) Non-volatile semiconductor memory device and data write control method for the same
US5386422A (en) Electrically erasable and programmable non-volatile memory system with write-verify controller using two reference levels
US5233562A (en) Methods of repairing field-effect memory cells in an electrically erasable and electrically programmable memory device
US5267209A (en) EEPROM programming method
US5313427A (en) EEPROM array with narrow margin of voltage thresholds after erase
US6452840B1 (en) Feedback method to optimize electric field during channel erase of flash memory devices
US5973962A (en) Method of programming non-volatile memory devices having a NAND type cell array
US5122985A (en) Circuit and method for erasing eeprom memory arrays to prevent over-erased cells
US6281716B1 (en) Potential detect circuit for detecting whether output potential of potential generation circuit has arrived at target potential or not
US4783766A (en) Block electrically erasable EEPROM
US5424993A (en) Programming method for the selective healing of over-erased cells on a flash erasable programmable read-only memory device
US6009014A (en) Erase verify scheme for NAND flash
US6160739A (en) Non-volatile memories with improved endurance and extended lifetime
US6055190A (en) Device and method for suppressing bit line column leakage during erase verification of a memory cell
US6975538B2 (en) Memory block erasing in a flash memory device

Legal Events

Date Code Title Description
AS Assignment

Owner name: MICRON TECHNOLOGY, INC., IDAHO

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:LEE, ROGER R.;REEL/FRAME:007870/0665

Effective date: 19960111

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: ROUND ROCK RESEARCH, LLC,NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223

Owner name: ROUND ROCK RESEARCH, LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MICRON TECHNOLOGY, INC.;REEL/FRAME:023786/0416

Effective date: 20091223