US5634115A  System and method for behavioral description translation  Google Patents
System and method for behavioral description translation Download PDFInfo
 Publication number
 US5634115A US5634115A US08/355,058 US35505894A US5634115A US 5634115 A US5634115 A US 5634115A US 35505894 A US35505894 A US 35505894A US 5634115 A US5634115 A US 5634115A
 Authority
 US
 United States
 Prior art keywords
 branch
 type
 voltage
 current
 defined
 Prior art date
 Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
 Expired  Lifetime
Links
Images
Classifications

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRIC DIGITAL DATA PROCESSING
 G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
 G06F17/50—Computeraided design
 G06F17/5009—Computeraided design using simulation
 G06F17/5036—Computeraided design using simulation for analog modelling, e.g. for circuits, spice programme, direct methods, relaxation methods
Abstract
Description
This application is a continuationinpart of a U.S. patent application entitled ELECTRONIC MODEL GENERATION PROCESS, Ser. No. 08/137,842, filed Oct. 15, 1993 now abandoned.
The present invention relates to the field of automated computeraided design (ECAD) systems for automating and simulating the design of electrical and electronic circuits and, in particular, to those systems and methods which translate higherlevel behavioral descriptions into lowerlevel specifications to describe a circuit and its components to a simulator system.
In the art of system design, in order to automate the process of designing and prototyping complex systems, various software and related hardware simulator tools have been developed. A simulator is a program that takes as input a description of a circuit network along with behavioral descriptions for each component contained therein to predict the response of the overall circuit to a given input stimulus. These simulators typically merge systems, components, and input descriptions together. In order to describe the circuit network to the simulator circuit component modeling languages are employed.
To use these modeling languages the circuit designers must understand the internal practices and limitations of the simulator itself because these practices tend to shape the modeling language employed to a relatively large degree. For example, some simulators force users to learn modified nodal analysis (MNA) formulation methodology because certain simulators use this methodology internally to formulate circuit relationships. Although efficient from the simulator's perspective, it can be difficult for most users to fully understand. Thus, extensive training was often needed before these more advanced modeling languages could be fully utilized.
Some modeling languages employ MNA both internally and at the user level. As the name implies, modified nodal analysis is an extension of the nodal analysis method which allows components to be described using constitutive (or branch) relationships that map voltages into currents and interconnection (or terminal) relationships. The terminal relationships are derived by an application of Kirchoff's laws to a single branch and are independent of both the behavior of the branch and the topology of the network. Presently, languages implement this MNA in a manner in which some of the component's interconnection relationships are given explicitly and others are given implicitly. For example, if a component is described with a branch relationship that gives electrical current as a function of voltage, the terminal relationships can be merged into the branch relationships. However, for the 3 other possibilities, e.g., voltage from current, voltage from voltage, or current from current, the user is required to explicitly specify additional relationships to fully describe the component's behavior. Any other combination requires the use of additional concepts that circuit designers may find unnatural and counterintuitive.
Another problem with these type modeling languages is that they only allow one to formulate a branch relationship to specify current as a function of one or more voltages. In particular, one could not directly specify a branch voltage or measure a branch current. These two limitations also force the user to use rather complicated procedures to describe component behaviors whose outputs are given in terms of voltage and whose inputs are given in terms of currents.
For example, consider one description of a voltagecontrolled current source (VCCS), implemented as shown in prior art FIG. 1A wherein only the branch relationships are given. Since the voltage controlled current source is relatively simple, the output current can be written as a function of the input voltage.
In another example, consider the description of a current controlled voltage source (CCVS) implemented as shown in prior art FIG. 1B wherein the statements
I.sub.in : v(ps)=v(ns)
I.sub.out : v(p)v(n)=gain*I.sub.in
are the branch relationships. For current controlled voltage sources, an extra relationship is needed to describe the component's characteristics of the output port and an additional relationship may be needed to describe the characteristics at the input ports. In other words, voltage is used as a controlling variable directly. If current is used an additional relationship is needed to fully describe input and output characteristics. Similarly, current can be used as the output directly. If voltage is used then an additional relationship is needed. Thus, there is an asymmetry in the MNA formulation methodology that circuit designers can find confusing.
Therefore, what is needed in this art is a behavioral description translation method which can translate higherlevel behavioral descriptions into a lowerlevel specification for the simulator and which would generate those other relationships needed by a simulator that were not already present in the original higherlevel description.
The present invention is directed to a behavioral description translation method which translates higherlevel behavioral descriptions to a lowerlevel specification to describe a circuit to a circuit simulator program tool.
Briefly summarized, a novel behavioral description translation method is disclosed which translates higherlevel behavioral descriptions to a lowerlevel specification to describe a circuit to a circuit simulator program tool. The preferred embodiment comprises the step of first identifying access functions from the behavioral descriptions of the underlying circuit and its components. Output access functions are used to specify signals and are found on the lefthand side of contribution statements. Input access functions are used to monitor signals and are found in expressions. The signals produced by the sources would be controlled by the signals measured by the probes in a manner specified by these branch relationships. The preferred embodiment has the next step of constructing structural representations of the behavioral descriptions of the circuits components as identified by the access functions. Four branch primitives are preferred herein to facilitate this construction. The preferred method further comprises the step of collapsing those Stype branches, i.e., voltage sources and current probes, that are connected in series between the same pair of nodes into one branch where the voltage on the new branch is the sum of the voltages of the old branches. Then, collapsing those Ptype branches, i.e., the current sources and voltage probes, that are connected in parallel between the same pair of nodes into one branch where the current through the new branch is the sum of the currents of the old branches. The next step of the present method comprises for every node in the network generating a single relationship that expresses KCL. The relationships thus formed are combined to eliminate unnecessary branch relationships. In such a manner, a behavior description translation method is disclosed which translate higherlevel behavioral descriptions into a lowerlevel specification to describe the circuit to a simulator program. In such a manner, the simulator can be provided with the relationships necessary to simulate the circuit and its components. Furthermore, the present invention advantageously enables users to treat voltage and current in a similar manner when formulating the higherlevel behavioral descriptions.
In order to more fully understand the present invention, reference is made to the appended drawings. Understanding that these drawings are not to be considered limitations in the scope of the invention, the presently preferred embodiments and the presently understood best mode of the invention are described with additional detail through use of the accompanying drawings in which:
FIG. 1A is a prior art behavioral descriptions of a voltage controlled current source;
FIG. 1B is a prior art behavioral descriptions of a current controlled voltage source;
FIG. 2 is an illustration of directions and signals associated with the illustrated branch and its terminals;
FIG. 3 is a generalized flow diagram of an improved electronic design automation (EDA) process including behavioral description generation according to one embodiment of the present invention;
FIG. 4 is a more detailed flow diagram of the more generalized flow diagram of FIG. 3;
FIG. 5 is a simplified block diagram illustrating flow source 76 and value probe 74 coupled to nodes 70 and 72;
FIG. 6 is a user defined behavioral description of a voltage controlled current source (VCCS) and a current controlled voltage source (CCVS) as defined by the associated contribution statements as written in SpectreHDL syntax;
FIG. 7 is a diagram illustrating the preferred set of four primitive branches as implemented herein for defining structural representations of behavioral descriptions from the identified access functions in accordance with the preferred embodiment of the present translation method;
FIG. 8A is an illustration of a simple conductance form of the resistor structurally represented as a parallel combination of a voltage probe and a current source;
FIG. 8B is an illustration of a resistor structurally represented as a series combination of a current probe and a voltage source;
FIG. 9 is a diagram illustrating two alternate structural representations of a branch that is dynamically bound;
FIG. 10 is a simple circuit illustration wherein R1 is implemented as a conductor and R2 is implemented as a resistor;
FIG. 11 is a coded representation of circuit component behavior given in SpectreHDL language syntax;
FIG. 12 is a structural representation of the circuit behaviorally described in FIG. 11; and
FIG. 13 is a simplified block diagram illustrating an electronic design automation (EDA) system for implementing the behavioral translation method of the present invention.
The present invention is directed to a behavioral description translation method which translates higherlevel behavioral descriptions to a lowerlevel specification to describe a circuit to a circuit simulator program tool.
The present invention was implemented using the SpectreHDL behavioral modeling language on a Cadence Spectre circuit simulator, both commercially available. This modeling language supplies the syntax used by the circuit designer to describe component behavior.
Some properties of nodes, branches, and terminals are: any number of terminals, and therefore any number of components, can be connected to the same node; a component may contain more than one branch; and inside a component more than one branch may connect to the same terminal. There are two qualities, in particular, flow and potential which are associated with each node and with each branch. Flow is the amount or rate of migration of matter, charge, etc. and, in electrical circuits, is either current or the movement of charge. The potential at a point is a measure of pressure or force in the applicable discipline that is a necessary requirement to produce flow. For example, in electrical circuits potential is electromotive force which is also referred to as voltage. For purposes of the description herein potential is referred to as the value of the node or branch.
A reference direction is also associated with each branch. The flow through a branch is considered positive if it flows with the reference direction and negative if it flows against the reference direction. Similarly, the potential across the branch is considered positive if flow moving in the reference direction is moving from a higher potential to a lower potential. With a positive potential across the branch, the terminal with the highest potential is considered the positive terminal for the branch, the other is considered the negative terminal. These associated reference directions are illustrated in FIG. 2. For clarity, voltage and current are used herein interchangeably with potential and flow.
At this point it is appropriate to introduce some fundamental concepts associated with potentials and flows referred to as Kirchoff's laws in the electrical/electronic arts. It should be understood that one considered skilled in this art would readily understand the following basic principles and properties pertinent to an understanding of the present invention.
Briefly, Kirchoff's current law describes how the currents combine at the node and Kirchoff's voltage law describes how the voltage is distributed at the nodes. These two laws are the conservation requirements. They describe how the voltage and currents on different branches interact. The conservation relationships are independent of the behavior of the branches but are dependent on the topology of the network and they enforce important requirements such as the conservation of charge or the conservation of mass. In addition, by an application of Tellegen's theorem, they can also be shown to enforce conservation of energy.
As previously discussed, both branch relationships and terminal relationships are needed to fully describe circuit systems and their components to a simulator. The branch relationships are independent of the topology of the network and describe the behavior of the individual branches of the circuit by relating the voltage and current of the branches therein. The terminal relationships are independent of both the behavior of the branch and the topology of the network and are derived by an application of Kirchoff's laws to a single branch. The terminal relationships for current, for instance, describe how current moves between the branch and the nodes. These relationships are: I_{P} =I_{B} and I_{N} =I_{B} where I_{B} is the branch current, I_{P} is the current flowing out of terminal P, and I_{N} is the current flowing out of terminal N. The terminal relationship for voltage, for instance, describes how the voltage at the nodes of the branch relates to the voltage on the branch itself. These relationships are: V_{B} =V_{P} V_{N} where V_{B} is the branch voltage, V_{P} is the voltage at terminal P, and V_{N} is the voltage at terminal N.
With respect to a more generalized embodiment of the present invention, attention is respectfully directed to FIG. 3 which is a generalized flow diagram of an improved electronic design automation (EDA) process including behavioral description generation according to one embodiment of the present invention herein described. Initially, user specification 11 of a prototype design is provided, conventionally as an electronic file describing system or circuit structure (netlist) 24 and/or behavior (model) 10. Then, simulation equation formulation 40 is performed automatically largely through software programs and files using conventional computing equipment to modify model 10 according to the present invention described herein.
In particular, upon receiving model 10, a structural representation of model 10 is extracted such that the structural representation is constructed from a set of basic branch types (e.g., value probe, flow probe, value source, or flow source). Based on the structural representation, a set of branch equations 52 (e.g., val=f(flow) 54, val=f(value) 56, flow=f(value) 58, flow=f(flow) 60) are generated in a form compatible with an underlying simulator 26. Additionally, it is determined whether to provide in model 10 an interconnection equation 42 (e.g., flow probing 44, value probing 46, flow sources 48, or value sources 50) for coupling to a pair of nodes in model 10. After equation formulation 40, conventional simulation 26 is performed on the formulated equations to determine 64 whether the prototype design is acceptable 30 or whether modification 62 is appropriate.
Reference is now being made to FIG. 4 which is a more detailed flow diagram of the more generalized flow diagram of FIG. 3. This flow diagram illustrates additional detail in the process of equation formulation 40, which occurs upon receiving behavioral model 10, provided preferably according to an analog hardware description language (AHDL). Initially, model 10, which defines conventional branch elements, is identified or interpreted as predefined structural representations. In this way, a structural representation of model 10 is generated or constructed from a set of basic component or branch types, including a value probe, a flow probe, a value source, and a flow source. From such structural representation, a set of branch equations 52 (5460) is generated or constructed, preferably in a form compatible with an underlying simulator. Moreover, as part of interpreting model 10 for structural representation, it is determined whether to provide automatically in model 10 an interconnect equation 42 for coupling to a pair of nodes included therein.
After model 10 interpretation 12 is performed in equation formulation 40, the generated structural representation is analyzed for every basic component or branch type 14, i.e., until analysis is done 27, at which point netlist 24 and the modified model 10 are simulated 26 and verified 30.
During basic component analysis 14, it is determined 16 for each identified basic component whether such basic component represents a value source (e.g., a voltage source) or a flow probe (e.g., a current probe). If it is determined that the identified basic component represents a value source or a flow probe, then an interconnection equation 42 is generated 18, preferably corresponding particularly to the basic component or branch type (e.g., flow probing 44, value probing 46, flow sources 48, value sources 50). Then, after interconnection equation 42 is generated, it is determined 20 whether another flow probe or value source is coupled to another pair of nodes in the structural representation. If it is determined that the other flow probe or value source is not coupled to a pair of nodes in the structural representation, then model 10 is modified 36 to couple the interconnection equation to that pair of nodes. Alternately, if it is determined that the other flow probe or value source is coupled thereto, then model 10 is modified 22 to couple serially the interconnection equation to the other flow probe or value source. Also, if it is determined that the identified basic component does not represent a value source or flow probe, then it is determined 32 whether an other flow source 76 or value probe 74 is couple to the pair of nodes 70, 72 of the structural representation, as shown schematically in FIG. 5. If it is determined that the other flow source 76 or value probe 74 is not coupled to pair of nodes 70,72, then model 10 is modified 28 to couple the interconnection equation to nodes 70, 72. Otherwise, model 10 is modified 34 to couple in parallel the interconnection equation to the other flow source 76 or value probe 74.
Now that the more generalized embodiment of the present invention has been discussed, the preferred embodiment of the present invention will now be described. Initially, a circuit designer writes a higherlevel behavioral description of the underlying circuit and its components using a modeling language. For example, two terminal components are described using SpectreHDL language as follows wherein the symbol "<" is an assignment operator for the behavioral descriptions in the contribution statements. The following TABLE A outlines four access functions.
______________________________________INPUT OUTPUT______________________________________voltage . . . <f(V(p,n)) V(p,n)< . . .current . . . <f(I(p,n)) I(p,n)< . . .______________________________________
TABLE A______________________________________Resistors can be expressed with one of the followingcontribution statements:V(p,n) < R*I(p,n)I(p,n) < V(p,n)/RCapacitors can be expresses in either of the followingtwo contributionsstatements:I(p,n) < C*dot(V(p,n))V(p,n) < integ(I(p,n))/CInductors can be expressed as either of the followingcontribution statements:V(p,n) < L*dot(I(p,n))I(p,n) < integ(V(p,n))/L______________________________________
A series RLC circuit can be formulated by summing the voltages across the three components and is written as the following contribution statement:
V(p,n)<R*I(p,n)+L*dot(I(p,n))+integ(I(p,n))/C
A parallel RLC circuit can be formulated by summing the currents through the three components and can be written as the following contribution statement:
I(p,n)<V(p,n)/R+C*dot(V(p,n))+integ(V(p,n))/L
As an example, attention is respectfully directed to FIG. 6 which is a coded representation of a voltage controlled current source (VCCS) and a current controlled voltage source (CCVS) as written in the above outlined syntax. Notice the application of the syntax to describe the simple example.
The preferred embodiment of the present invention further involves identifying the access functions from the written behavioral descriptions. Output access functions are used to specify signals and are found on the lefthand side of the contribution statement operator. Input access functions are used to monitor signals and are found in expressions on the right hand side of the contribution statement operator. One can think of output access functions as being controlled sources and input access functions as being probes. The signals produced by the sources would be controlled by the signals measured by the probes in a manner specified by the contribution statement.
For example, consider the contribution statement: I(a,b)<G*V(a,b). The access function V(a,b) is a function that acts as a voltage probe because it is found on the right hand side of the contribution statement operator. The access function I(a,b) is a function that acts as a current source because it is found on the left hand side of the contribution statement operator.
Once the access functions have been identified in the supplied syntax of the behavioral descriptions the next step of the preferred embodiment of the present translation method involves constructing the structural representations of the behavioral descriptions of the circuits components given the identified access functions. A structural representation is constructed using one or more of the illustrated primitive branches, i.e., voltage probes, current probes, voltage sources, and current sources, illustrated in FIG. 7. When constructing the structural representation from the identified primitive branches, there is some freedom as to how these primitives can be combined. Consider the following:
SType (serial) branches: Voltage sources and current probes from the same component and attached to the same two nodes are combined in series. Current probes and voltage sources are considered to be Stype because when they are connected to the same nodes within the same component they combine in series.
PType (parallel) branches: Current sources and voltage probes from the same component and attached to the same two nodes are combined in parallel. Herein, voltage probes and current sources are considered Ptype because when they are connected to the same two nodes within the same component they are combined in parallel.
Mixture of both type branches: When both types are specified between the same two nodes they combine in parallel.
It should be understood that connecting multiple sources between two nodes is equivalent to connecting one source whose output is the sum of their respective contributions. For example the behavioral description defined by the contribution statements: I(p,n)<x; and I(p,n)<y; are equivalent to: I(p,n)<x+y and the statements V(p,n)<y; and V(p,n)<x; are therefore equivalent to: V(p,n)<x+y.
Consider the behavioral description of a simple conductance form of the resistor defined by the contribution statement: I(p,n)<G*V(p,n). The access functions are V(p,n) and I(p,n) and have the functions as defined above. Once identified, the conductor can then be structurally represented as a parallel combination of a voltage probe and a current source as shown in FIG. 8A. A current source alone has zero conductance but when the current through the source depends on the voltage across the source, the output conductance is nonzero. Further, consider the behavioral description of a resistor defined by the contribution statement: V(p,n)<R*I(p,n). The access functions are V(p,n) and I(p,n). Once identified, the resistor can be structurally represented as a series combination of a current probe and a voltage source as shown in FIG. 8B. A voltage source alone has a zero resistance but when the voltage across the source depends on the current through the source, as in this case, the output resistance is nonzero.
Reference is now being made to FIG. 9, which is a diagram illustrating two alternate structural representations of a branch 77 and 79 that is considered to be dynamically bound, i.e., it is the special case when a branch is sometimes Stype and sometimes Ptype. Circuit designers typically encounter these type branches when modeling ideal switches and ideal diodes which are active or inactive independently. Thus, one, both, or neither can be active at an instant in time. When the Ptype (the current source) is inactive it is connected but disabled, i.e., the current is zero. When the Stype (the voltage source) is not active it is disconnected from the circuit completely. The Stype and Ptype are separate branches that are implemented independently. The Ptype is implemented as a conventional Ptype branch. The Stype driver is implemented as a Stype branch that has been modified to include the switch. An Stype branch that has been modified to include the switch is a conditional Stype branch having a branch relationship taking the form:
SIGMA(V.sub.B g(. . . ))+(1SIGMA)I.sub.B =0,
where SIGMA=1 if the Stype driver is active, and 0 otherwise, and g (. . . ) is a function
Upon the identification of the access functions and the construction of the structural representations, the next step of the preferred embodiment of the present invention involves collapsing those Stype branches (voltage sources and current probes) that are connected in series between the same pair of nodes into one branch where the voltage on the new branch is the sum of the voltages of the old branches. This involves: for every old branch j that is being collapsed into the new branch k, the branch relationship for the branch voltage can be written such that: for all j in ALPHA_{K} the set of branches that were collapsed to form branch k is: V_{Bj} =f_{j} (. . . ) and, where f_{j} (. . . ) is a function representing every old branch j. For every branch that remains after collapsing the Stype branches, the branch relationships are written as:
SIGMA(V.sub.Pk V.sub.Nk)+(1SIGMA)I.sub.B =SUM[V.sub.Bj ]
for all j in ALPHA_{K}, where SIGMA=1 if any of the Stype drivers is active. It should be understood that the SUM[ ] is used herein to represent the mathematical summation operation for a defined range. The relationships thus formed are combined to eliminate the V_{Bj} for all j in ALPHA_{K}.
In the instance wherein the branch is not a conditional Stype, then SIGMA is always 1 and can be simplified to:
V.sub.Pk V.sub.Nk =SUM[V.sub.Bj ]
for all j in ALPHA_{K}.
The preferred embodiment further comprises collapsing those Ptype branches (current sources and voltage probes) that are connected in parallel between the same pair of nodes into one branch where the current through the new branch is the sum of the currents of the old branches. More specifically, this involves: for every old branch j that is being collapsed into the new branch k, the branch relationship for the branch current can be written such that: for all j in BETA_{K}, where BETA_{K} is the set of branches that were collapsed to form branch k, is I_{Bj} =f_{j} (. . . ) and, for every branch that remains after collapsing the Ptype branches, the branch relationships are written as:
I.sub.Bk =SUM[I.sub.Bj ]
for all j in BETA_{K}. The relationships thus formed are combined to eliminate the I_{Bj} for all j in BETA_{K}.
The preferred embodiment further comprises generating the set of relationships that describes the entire system for the simulator. This set of relationships is the combination of three sets of relationships: the nodal analysis relationships of KCL; the branch relationships for Ptype branches; and the branch relationships for Stype branches. Thus, in addition to the branch relationships, the nodal analysis relationships must also be defined. This involves: for every node, one relationship is written that expresses KCL, such that:
0=SUM[I.sub.Bj ]SUM[I.sub.Bk ],
for all j in GAMMA_{N} and for all k in LAMBDA_{N}, where GAMMA_{N} is the set of branches with positive terminals that connect to node N and LAMBDA_{N} is the set of branches with negative terminals that connect to node N.
As an example, reference is now being made to the schematic diagram of FIG. 10 where resistor R_{1} is implemented as a resistor, as shown in FIG. 8A, and resistor R_{2} is implemented as a conductor, as shown in FIG. 8B. The first set of relationships is the nodal analysis relationships which include one relationship for each node that simply states that the sum of the currents exiting the node must be zero. In this example, there is only one node. Ground is ignored because the written relationship would be redundant, thus: I_{B1} +I_{B2} =0. Only Ptype branches are contained in the conductor R1, thus: I_{B1} =V_{B1} /R_{1} +0. The first term on the right side of the above relationship is the contribution from the current source. The second term is due to the voltage probe. Recall that: V_{B1} =V_{P1} V_{N1} and that V_{P1}, the voltage on the positive terminal, is equal to V_{1} the voltage on node 1. Thus, the voltage V_{N1} is the voltage on the negative terminal (which is 0) because the negative terminal is grounded. As a result, the above relationship becomes: R_{1} I_{B1} =V_{1}. The only Stype branches are contained in the resistor R_{2}. Thus, we have V_{B2} =R_{2} I_{B2} +0. The first term on the right side of this relationship is the contribution from the voltage source. The second term is due to the current probe. Therefore, V_{B2} can be eliminated to: V_{1} =R_{2} I_{B2} +0. These relationships then can be combined into the following set of relationships:
I.sub.B1 +I.sub.B2 =0 (1)
V.sub.1 R.sub.1 I.sub.B1 =0 (2)
R.sub.2 I.sub.B1 V.sub.1 =0 (3)
The last step of the preferred method comprises the step of eliminating unnecessary branch relationships. A branch relationship can be eliminated if the branch current can be solved for explicitly. In other words, if the branch relationship can be rewritten as I_{Bj} =f(. . . ), where f(. . . ) does not contain a reference to I_{Bj} ; and the branch current is not needed either as an output or as a controlling variable for some other component in the system then it can be eliminated.
To illustrate, attention is specifically directed to the previously generated above set of relationships (1), (2) and (3). For branch relationships, if the branch relationship can be rewritten as I_{Bj} =f( . . . ), where the function f(. . . ) does not contain a reference to I_{Bj} and if the branch current is not needed either as an output or as a controlling variable for some other component in the system then that relationship can be eliminated in advance. For example: consider I_{B1} =V_{1} /R_{1}. Eliminating the branch relationship and the branch current for the conductor results in the following:
(V.sub.1 /R.sub.1)+I.sub.B2 =0 (4)
(R.sub.2 I.sub.B2)V.sub.1 =0 (5)
which are the relationships for the circuit of FIG. 10.
As a further example of an application of the preferred embodiment of the present invention, attention is respectfully directed to FIG. 11 which illustrates a user coded behavioral description of a circuit with series resistance and inductance using SpectreHDL language syntax. In accordance with the preferred embodiment as previously discussed herein, the access functions are first identified in the syntax provided by the circuit designer as a higherlevel behavioral description of the underlying circuit. This specific higherlevel behavioral description contains a total of 8 access functions. In line (1) of FIG. 11, the access functions are V(A,IntA) and I(A,IntA) for the parasitic resistor. Note the particular side of the contribution statement operator that each access functions is on. In line (2), the access functions are V(A,IntA) and I(A,IntA). In line (3), the identified access function is V(IntA,C). In line (4), I(IntA,C). In line (5), I(IntA,C). And, in line (6), V(IntA,C). Reference is now being made to FIG. 12 which is a structural representation of the circuit higherlevel behaviorally described in the syntax of FIG. 11. Both the parasitic resistor and inductor therein each contain a current probe and a voltage source connected between node A and IntA wherein the access function V(A,IntA) on the left side is represented by the voltage source and the access function I(A,IntA) on the right side is represented by the current probe. Since current probes and voltage sources are Stype components they are placed in series between A and IntA. Both the junction diode and capacitor therein each contain a voltage probe and a current source connected between node IntA and C wherein the access function I(IntA,C) on the left side is represented by the current source, and the access function V(IntA,C) on the right side is represented by the voltage probe. Since voltage probes and current sources are Ptype components they are placed in parallel between IntA and C.
An application of the next step of the preferred embodiment involves collapsing those Stype branches (voltage sources and current probes) that are connected in series between the same pair of nodes into one branch where the voltage on the new branch is the sum of the voltages of the old branches. In this instance, this involves those which are tied between A and IntA into the following voltage source:
V.sub.A V.sub.IntA =(rs*I.sub.RL +ls(dI.sub.RL /dt))/area
An application of the next step of the preferred embodiment involves collapsing those Ptype branches (current sources and voltage probes) that are connected in parallel between the same pair of nodes into one branch where the current through the new branch is the sum of the currents of the old branches. In this instance, this involves those which are tied between IntA and C with the following current source:
I.sub.J =area is[e.sup.(V.sbsb.J/n.sup.V.sbsb.T.sup.) 1+area(d/dt)(tau I.sub.d +2cjo*root(phi(phi+V.sub.J)))]
The next step of the present method comprises the step of: for every node in the network writing a single relationship that expresses KCL. As such, generating the KCL relationships for the individual components of FIG. 12 produces the following:
A: 0=I.sub.RL + . . . (6)
IntA: 0=I.sub.J I.sub.RL (7)
C: 0= . . . I.sub.J (8)
The last step of the present method involves eliminating he unnecessary branch relationships thus formed. Thus, the relationship given by (6) is folded into (7) and (8) thereby eliminating (6) to generate the set of relationships for the circuit of FIG. 12 which will be used by the simulator to describe the circuit and its function. In such a manner, a behavior description translation method is disclosed which translate higherlevel behavioral descriptions into a lowerlevel specification to describe the circuit to a circuit simulator program tool.
Reference is now being made to FIG. 13, which is a block diagram of an electronic design automation (EDA) system 80 for implementing the present invention. System 80 includes conventional processor 82 and storage 84, which runs conventional EDA tools 86 for prototype system definition (e.g., netlisting/modeling) and verification (e.g., simulation). As detailed above, the present invention generally resides in providing in conjunction with EDA tools 86 a behavioralmodel software translator or modifier 88, for converting a higherlevel behavioral model 90, which is independent of the underlying simulator's equation formulation method, to a lowlevel behavioral model 92, which is dependent on the underlying simulator's equation formulation method, essentially by adding certain interconnection equations 84 into the model. In an alternative embodiment, lowlevel behavioral model 92 may be converted to higherlevel behavioral model, essentially by identifying and removing such added interconnection equations.
It should be understood that because the simulator tool is generally a computer program it is envisioned herein that the techniques of the present invention find their implementation in a software algorithm interfaced with the simulator program providing thereto the end relationships generated by the present method.
In summary, a novel behavioral description translation method is disclosed which translates higherlevel behavioral descriptions to a lowerlevel specification to describe a circuit to a circuit simulator program tool. The preferred embodiment comprises the step of first identifying access functions from the behavioral descriptions of the underlying circuit and its components. Output access functions are used to specify signals and are found on the lefthand side of contribution statements. Input access functions are used to monitor signals and are found in expressions. The signals produced by the sources would be controlled by the signals measured by the probes in a manner specified by these branch relationships. The preferred embodiment has the next step of constructing structural representations of the behavioral descriptions of the circuits components as identified by the access functions. Four branch primitives are preferred herein to facilitate this construction. The preferred method further comprises the step of collapsing those Stype branches, i.e., voltage sources and current probes, that are connected in series between the same pair of nodes into one branch where the voltage on the new branch is the sum of the voltages of the old branches. Then, collapsing those Ptype branches, i.e., the current sources and voltage probes, that are connected in parallel between the same pair of nodes into one branch where the current through the new branch is the sum of the currents of the old branches. The next step of the present method comprises for every node in the network generating a single relationship that expresses KCL. The relationships thus formed are combined to eliminate unnecessary branch relationships. In such a manner, a behavior description translation method is disclosed which translate higherlevel behavioral descriptions into a lowerlevel specification to describe the circuit to a simulator program.
It will be appreciated by those skilled in this art that the present invention can be embodied in other specific forms without departing form the spirit or essential characteristics thereof. The presently disclosed embodiments are therefore considered in all respects to be illustrative and not restrictive. The scope of the invention is therefore indicated by the appended claims rather than the foregoing description and all changes that come within the meaning and range of equivalents thereof are intended to be considered as being embraced within their scope.
Claims (28)
Priority Applications (2)
Application Number  Priority Date  Filing Date  Title 

US13784293A true  19931015  19931015  
US08/355,058 US5634115A (en)  19931015  19941213  System and method for behavioral description translation 
Applications Claiming Priority (1)
Application Number  Priority Date  Filing Date  Title 

US08/355,058 US5634115A (en)  19931015  19941213  System and method for behavioral description translation 
Related Parent Applications (1)
Application Number  Title  Priority Date  Filing Date  

US13784293A ContinuationInPart  19931015  19931015 
Publications (1)
Publication Number  Publication Date 

US5634115A true US5634115A (en)  19970527 
Family
ID=22479276
Family Applications (1)
Application Number  Title  Priority Date  Filing Date 

US08/355,058 Expired  Lifetime US5634115A (en)  19931015  19941213  System and method for behavioral description translation 
Country Status (2)
Country  Link 

US (1)  US5634115A (en) 
EP (1)  EP0660268A3 (en) 
Cited By (15)
Publication number  Priority date  Publication date  Assignee  Title 

US5812431A (en) *  19940613  19980922  Cadence Design Systems, Inc.  Method and apparatus for a simplified system simulation description 
US5896300A (en) *  19960830  19990420  Avant Corporation  Methods, apparatus and computer program products for performing postlayout verification of microelectronic circuits by filtering timing error bounds for layout critical nets 
US5949993A (en) *  19971031  19990907  Production Languages Corporation  Method for the generation of ISA simulators and assemblers from a machine description 
US6009252A (en) *  19980305  19991228  Avant! Corporation  Methods, apparatus and computer program products for determining equivalencies between integrated circuit schematics and layouts using color symmetrizing matrices 
US6101323A (en) *  19980715  20000808  Antrim Design Systems, Inc.  Method and apparatus for improvement of sparse matrix evaluation performance 
WO2000057317A1 (en) *  19990319  20000928  Moscape, Inc.  System and method for performing assertionbased analysis of circuit designs 
US6152612A (en) *  19970609  20001128  Synopsys, Inc.  System and method for system level and circuit level modeling and design simulation using C++ 
US6305006B1 (en)  19980518  20011016  Mentor Graphics Corporation  Generating candidate architectures for an architectural exploration based electronic design creation process 
US6314552B1 (en)  19980518  20011106  Lev A. Markov  Electronic design creation through architectural exploration 
US20030172055A1 (en) *  20020308  20030911  Mentor Graphics Corporation  Array transformation in a behavioral synthesis tool. 
US20040111692A1 (en) *  20001221  20040610  Mentor Graphics Corp.  Interactive interface resource allocation in a behavioral synthesis tool 
US6917909B1 (en)  19980518  20050712  Lev A. Markov  Facilitating guidance provision for an architectural exploration based design creation process 
US20070162269A1 (en) *  20051210  20070712  Electronics And Telecommunications Research Institute  Method for digital system modeling by using higher software simulator 
US20070186205A1 (en) *  20060209  20070809  Henry Yu  Managing and controlling the use of hardware resources on integrated circuits 
US7672827B1 (en)  20000828  20100302  Cadence Design Systems, Inc.  Method and system for simulation of analog/digital interfaces with analog tristate ioputs 
Citations (3)
Publication number  Priority date  Publication date  Assignee  Title 

US5047971A (en) *  19870623  19910910  Intergraph Corporation  Circuit simulation 
EP0490478A2 (en) *  19901214  19920617  Tektronix Inc.  Automatic compilation of model equations into a gradient based analog simulator 
US5469366A (en) *  19930920  19951121  Lsi Logic Corporation  Method and apparatus for determining the performance of nets of an integrated circuit design on a semiconductor design automation system 

1994
 19940415 EP EP94105868A patent/EP0660268A3/en not_active Withdrawn
 19941213 US US08/355,058 patent/US5634115A/en not_active Expired  Lifetime
Patent Citations (4)
Publication number  Priority date  Publication date  Assignee  Title 

US5047971A (en) *  19870623  19910910  Intergraph Corporation  Circuit simulation 
EP0490478A2 (en) *  19901214  19920617  Tektronix Inc.  Automatic compilation of model equations into a gradient based analog simulator 
US5363320A (en) *  19901214  19941108  Tektronix, Inc.  Automatic compilation of model equations into a gradient based analog simulator 
US5469366A (en) *  19930920  19951121  Lsi Logic Corporation  Method and apparatus for determining the performance of nets of an integrated circuit design on a semiconductor design automation system 
NonPatent Citations (10)
Title 

"A Unified MixedMode Digital Analog Simulation Env.", Odryna, P., IEEE 1988, pp. 893896. 
"Development of an Analog Hardware Description Lang.", Kurker, C., IEEE Custom Integ. Circuits Conf. 1990, pp. 5.4.15.4.6. 
A Unified Mixed Mode Digital Analog Simulation Env. , Odryna, P., IEEE 1988, pp. 893 896. * 
Development of an Analog Hardware Description Lang. , Kurker, C., IEEE Custom Integ. Circuits Conf. 1990, pp. 5.4.1 5.4.6. * 
J. Sams, "Model the Equation, Not the Circuit", Electronic Engineering, vol. 65 No. 802, Oct. 1993, pp. 4348. 
J. Sams, Model the Equation, Not the Circuit , Electronic Engineering, vol. 65 No. 802, Oct. 1993, pp. 43 48. * 
M. Iordache et al., "Generalized Diakoptic Analysis for LargeScale Electric Circuits", Revue Roumaine Des Sciences Techniques, Serie Electrotechnique et Enertique, vol. 38, No. 3, Jul. 1993Sep. 1993 pp. 365384. 
M. Iordache et al., Generalized Diakoptic Analysis for Large Scale Electric Circuits , Revue Roumaine Des Sciences Techniques, Serie Electrotechnique et Enertique, vol. 38, No. 3, Jul. 1993 Sep. 1993 pp. 365 384. * 
M.L. Blostein, "On the Application of Certain Network Concepts to Artibrary Systems", IEEE Proceedings of the International Symposium on Circuit Theory, 1972 Hollywood, U.S. pp. 213217. 
M.L. Blostein, On the Application of Certain Network Concepts to Artibrary Systems , IEEE Proceedings of the International Symposium on Circuit Theory, 1972 Hollywood, U.S. pp. 213 217. * 
Cited By (27)
Publication number  Priority date  Publication date  Assignee  Title 

US5812431A (en) *  19940613  19980922  Cadence Design Systems, Inc.  Method and apparatus for a simplified system simulation description 
US5896300A (en) *  19960830  19990420  Avant Corporation  Methods, apparatus and computer program products for performing postlayout verification of microelectronic circuits by filtering timing error bounds for layout critical nets 
US6286126B1 (en)  19960830  20010904  Avant! Corporation  Methods, apparatus and computer program products for performing postlayout verification of microelectronic circuits using best and worst case delay models for nets therein 
US6152612A (en) *  19970609  20001128  Synopsys, Inc.  System and method for system level and circuit level modeling and design simulation using C++ 
US5949993A (en) *  19971031  19990907  Production Languages Corporation  Method for the generation of ISA simulators and assemblers from a machine description 
US6009252A (en) *  19980305  19991228  Avant! Corporation  Methods, apparatus and computer program products for determining equivalencies between integrated circuit schematics and layouts using color symmetrizing matrices 
US6305006B1 (en)  19980518  20011016  Mentor Graphics Corporation  Generating candidate architectures for an architectural exploration based electronic design creation process 
US6314552B1 (en)  19980518  20011106  Lev A. Markov  Electronic design creation through architectural exploration 
US6917909B1 (en)  19980518  20050712  Lev A. Markov  Facilitating guidance provision for an architectural exploration based design creation process 
US6101323A (en) *  19980715  20000808  Antrim Design Systems, Inc.  Method and apparatus for improvement of sparse matrix evaluation performance 
US6374390B1 (en)  19980715  20020416  Antrim Design Systems, Inc.  Method and apparatus for improvement of sparse matrix evaluation performance 
WO2000057317A1 (en) *  19990319  20000928  Moscape, Inc.  System and method for performing assertionbased analysis of circuit designs 
US6591402B1 (en)  19990319  20030708  Moscape, Inc.  System and method for performing assertionbased analysis of circuit designs 
US7672827B1 (en)  20000828  20100302  Cadence Design Systems, Inc.  Method and system for simulation of analog/digital interfaces with analog tristate ioputs 
US7302670B2 (en)  20001221  20071127  Bryan Darrell Bowyer  Interactive interface resource allocation in a behavioral synthesis tool 
US7831938B2 (en)  20001221  20101109  Mentor Graphics Corporation  Interactive interface resource allocation in a behavioral synthesis tool 
US20080077906A1 (en) *  20001221  20080327  Bowyer Bryan D  Interactive interface resource allocation in a behavioral synthesis tool 
US20040111692A1 (en) *  20001221  20040610  Mentor Graphics Corp.  Interactive interface resource allocation in a behavioral synthesis tool 
US7310787B2 (en)  20020308  20071218  Shiv Prakash  Array transformation in a behavioral synthesis tool 
US20030172055A1 (en) *  20020308  20030911  Mentor Graphics Corporation  Array transformation in a behavioral synthesis tool. 
US20070162269A1 (en) *  20051210  20070712  Electronics And Telecommunications Research Institute  Method for digital system modeling by using higher software simulator 
US7783467B2 (en) *  20051210  20100824  Electronics And Telecommunications Research Institute  Method for digital system modeling by using higher software simulator 
US20070186205A1 (en) *  20060209  20070809  Henry Yu  Managing and controlling the use of hardware resources on integrated circuits 
US7735050B2 (en)  20060209  20100608  Henry Yu  Managing and controlling the use of hardware resources on integrated circuits 
US20100318954A1 (en) *  20060209  20101216  Henry Yu  Managing and controlling the use of hardware resources on integrated circuits 
US8726204B2 (en)  20060209  20140513  Mentor Graphics Corporation  Managing and controlling the use of hardware resources on integrated circuits 
US9747398B2 (en)  20060209  20170829  Mentor Graphics Corporation  Managing and controlling the use of hardware resources on integrated circuits 
Also Published As
Publication number  Publication date 

EP0660268A2 (en)  19950628 
EP0660268A3 (en)  19960131 
Similar Documents
Publication  Publication Date  Title 

Kuo  Network analysis by digital computer  
Daems et al.  Simulationbased generation of posynomial performance models for the sizing of analog integrated circuits  
Cheng et al.  Automatic generation of functional vectors using the extended finite state machine model  
US5790835A (en)  Practical distributed transmission line analysis  
US5446676A (en)  Transistorlevel timing and power simulator and power analyzer  
Newton  Techniques for the simulation of largescale integrated circuits  
US5475605A (en)  Timing analysis for logic optimization using target library delay values  
Lin et al.  Analogue circuits fault dictionary—New approaches and implementation  
US6192504B1 (en)  Methods and systems for functionally describing a digital hardware design and for converting a functional specification of same into a netlist  
US5880971A (en)  Methodology for deriving executable lowlevel structural descriptions and valid physical implementations of circuits and systems from semantic specifications and descriptions thereof  
Croix et al.  Blade and razor: cell and interconnect delay analysis using currentbased models  
Quarles et al.  SPICE3 Version 3f3 User’s Manual  
US7278120B2 (en)  Methods and apparatuses for transient analyses of circuits  
US5481484A (en)  Mixed mode simulation method and simulator  
US7324363B2 (en)  SPICE optimized for arrays  
US6925621B2 (en)  System and method for applying timing models in a statictiming analysis of a hierarchical integrated circuit design  
Ratzlaff et al.  RICE: Rapid interconnect circuit evaluator  
US6134513A (en)  Method and apparatus for simulating large, hierarchical microelectronic resistor circuits  
US6871331B1 (en)  Combined waveform and data entry apparatus and method for facilitating fast behavioral verification of digital hardware designs  
Qian et al.  Modeling the" Effective capacitance" for the RC interconnect of CMOS gates  
US5933356A (en)  Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models  
Feldmann  Reducedorder modeling of large linear subcircuits via a block Lanczos algorithm  
Koza et al.  Automated design of both the topology and sizing of analog electrical circuits using genetic programming  
US6662149B1 (en)  Method and apparatus for efficient computation of moments in interconnect circuits  
US5815402A (en)  System and method for changing the connected behavior of a circuit design schematic 
Legal Events
Date  Code  Title  Description 

AS  Assignment 
Owner name: CADENCE DESIGN SYSTEMS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:FITZPATRICK, DANIEL;KUNDERT, KENNETH S.;REEL/FRAME:007344/0786 Effective date: 19950210 

FPAY  Fee payment 
Year of fee payment: 4 

FPAY  Fee payment 
Year of fee payment: 8 

FPAY  Fee payment 
Year of fee payment: 12 