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Semiconductor device with buried inverse T-type field region

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US5391907A
US5391907A US08193910 US19391094A US5391907A US 5391907 A US5391907 A US 5391907A US 08193910 US08193910 US 08193910 US 19391094 A US19391094 A US 19391094A US 5391907 A US5391907 A US 5391907A
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Prior art keywords
field
oxide
film
nitride
region
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Expired - Lifetime
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US08193910
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Seong J. Jang
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LG Semicon Co Ltd
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LG Semicon Co Ltd
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26Bombardment with radiation
    • H01L21/263Bombardment with radiation with high-energy radiation
    • H01L21/265Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
    • H01L21/26533Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically inactive species in silicon to make buried insulating layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76267Vertical isolation by silicon implanted buried insulating layers, e.g. oxide layers, i.e. SIMOX techniques
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76281Lateral isolation by selective oxidation of silicon

Abstract

The present invention relates to a semiconductor and a method for fabrication thereof and particularly to a semiconductor having a field oxide having a shape such that the lower part is wider that the upper part.
Therefore, according to the present invention, the ion implantation process for forming a channel stop region becomes unnecessary, because of the effect of accurate insulation between the devices and the pn junction area can be decreased, so that the junction capacitance becomes decreased. Furthermore, because LOCOS edge does not coincide with the junction edge, the leakage current due to the damage of the edge is not generated. Because a field oxide is of the buried inverse T-type, the effective width of the device is increased more than that of a mask. Because the bird's beak is not generated, the problem due to the narrow width can be settled.

Description

This application is a continuation of U.S. Application Ser. No. 07/974,978, filed Nov. 12, 1992, now abandoned, which is a division of U.S. application Ser. No. 07/856,020, filed Mar. 23, 1992, and now issued as U.S. Pat. No. 5,182,226.

BACKGROUND OF THE INVENTION

The present invention relates to a semiconductor device and a method for fabrication thereof having a field oxide of the buried inverse T-type suited to sub-micron MOS devices.

FIG. 1 shows a cross-sectional view of a semiconductor device where a field oxide is formed using a conventional LOCOS process (Local Oxidation of Silicon).

In the prior art, when MOS devices are fabricated, the field oxide is formed using the conventional LOCOS to isolate devices.

Thus, as shown in FIG. 1, a field oxide layer 2 is grown on a field region of a Si substrate 1 using a nitride layer (not shown herein) and a gate 3 is formed at a predetermined region, and then predetermined impurities are implanted on both sides of gate 3 to form the source and drain regions 4.

Furthermore, because, when the field oxide 2 is grown, it penetrates only a little within Si substrate 1, predetermined impurities are implanted in a field region to form a channel stop for insulation transistors.

However, the conventional fabrication process for forming the field oxide has disadvantages in that the effective area of the device is decreased, because of the generation of the bird beak and the capacitance is increased due to the pn junction. Furthermore, leakage current is generated by the damage of the edge portion, so that it is not able to completely insulate the device.

SUMMARY OF THE INVENTION

It is an object of the present invention to provide a semiconductor device having a field oxide of the buried inverse T-type.

It is another object of the present invention to provide a method for fabrication of the semiconductor device for forming a field oxide of the buried inverse T-type using oxygen or nitrogen ion implantation.

To achieve this object of the present invention, there is provided a semiconductor device isolated by a field oxide in the shape of a buried inverse T, in which the lower part is wider than the upper part.

And, there is provided a method for fabrication of the semiconductor device, which comprises the steps of:

successively depositing a pad nitride film, a first nitride film and a first oxide film on a Si substrate;

exposing the Si substrate of field region and forming the side wall of a second nitride film;

implanting ion impurities into the exposed substrate to a predetermined depth;

removing the first oxide film and second nitride film and successively depositing a second oxide film and a second nitride film on the whole surface;

etching the third nitride film to expose the fixed portion of the Si substrate;

implanting the impurities with lower energy than the first ion implantation;

forming a field oxide by heat treatment of the impurities implanted within the substrate;

removing the remaining third nitride film, second nitride film, first nitride film and pad nitride film; and

forming a transistor in an active region isolated by the field oxide.

BRIEF DESCRIPTION OF THE INVENTION

The features and advantages of the present invention will be more clearly appreciated from the following description of the preferred embodiments of the invention taken in conjunction with the accompanying drawings in which:

FIG. 1 is a cross-sectional view of a semiconductor device in which a field oxide is formed using the conventional LOCOS.

FIGS. 2A through 2E are cross-sectional views illustrating the device after various operations in a fabrication process forming a field oxide of the buried inverse T-type according to a preferred embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

A semiconductor device and a method for fabrication thereof according to the present invention will be described in more detail with reference to the various views in accompanying FIG. 2.

FIGS. 2A through 2E are cross-sectional views of the device after completion of various steps in a fabrication process for manufacturing a semiconductor device having the buried inverse T-type according to a preferred embodiment of the present invention.

A pad nitride film 12, a first nitride film 13 and a first oxide film 14 are successively deposited on a Si substrate 11. The Si substrate 11 of the field region is exposed by using an active mask (not shown herein).

Then, the second nitride film is thinly deposited and then etched by an RIE process to form the side wall 15.

The fixed impurities, such as the oxygen ions or the nitrogen ions, are then implanted into the exposed Si substrate 11 to a predetermined depth.

Herein, the first ion implantation condition is that the impurities should be implanted into the surface of the Si substrate 11 to a depth of about 0.5 μm with an energy of from about 150 to 250 KeV.

Furthermore, amount of the dose is on the order of from 1017 /cm2 to 2019 /cm2.

Henceforth, as shown in FIG. 2B, the first oxide film 14 and the side wall 15 are removed and the second oxide film 16 and the third nitride film 17 are successively deposited on the whole surface.

Then, as shown in FIG. 2C, the third nitride film 17 is etched by RIE to form the side wall 17a, and the oxygen ions or the nitrogen ions are implanted with lower energy against the Si substrate 11.

Herein, the second ion implantation condition is that the impurities should be implanted from the surface of the Si substrate 11 to a depth of about 0.5 μm with energy of from about 50 to 100 KeV.

Furthermore, the amount of the dose is on the order of from 1017 /cm2 to 1019 /cm2.

Henceforth, as shown in FIG. 2D, a heat treatment process of about 800° to 950° is performed at the oxygen ion implanted region to form a field oxide 18.

Then the side wall, the second oxide film 16, the first nitride film 13 and the pad nitride film 12 are removed. Accordingly, the field oxide 18 of the buried inverse T-type is formed.

Henceforth, as shown in FIG. 2E, the gate 19 and the source and drain region 20 are formed in the active region of the isolated field oxide 18 of the buried inverse T-type according to the present invention.

According to the present invention use, the ion implantation process for forming a channel stop region becomes unnecessary, because of the effect of accurate insulation between the devices and the pn junction area can be decreased, so that the junction capacitance becomes decreased.

Furthermore, because the LOCOS edge does not coincide with the junction edge, the leakage current due to the damage of the edge is not generated. Because the field oxide is of the buried inverse T-type, the effective width of the device is increased more than that of a mask. Because the bird's beak is not generated, the problem due to the narrow width can be settled. It will be understood by those skilled in the art that the foregoing description is in terms of a preferred embodiment of the present invention, wherein various changes and modifications may be made without departing from the spirit and scope of the invention, as set forth in the appended claims.

Claims (2)

What is claimed is:
1. A semiconductor device having a nitride field region of the buried inverse T-type comprising:
a semiconductor substrate;
at least one gate electrode having opposite edges formed on the semiconductor substrate;
source and drain regions formed below the opposite edges, respectively, of each gate electrode;
nitride field regions formed adjacent the source and drain regions, wherein a lower part of each field region contacts a lower part of the adjacent one of the source and drain regions, and an upper part of each field region contacts a side of the adjacent one of the source and drain regions, such that the lower part of each field region is wider than the upper part of the field region.
2. A semiconductor device having a nitride field region of the buried inverse T-type comprising:
a semiconductor substrate;
at least one gate electrode having opposite edges formed on the semiconductor substrate;
drain and source regions formed below the opposite edges, respectively, of each gate electrode;
nitride lower field regions formed adjacent the source and drain regions, wherein each lower field region extends below and contacts a lower part of the adjacent one of the source and drain region; and
nitride upper field regions formed adjacent the source and drain regions and above the lower field regions, wherein each upper field region contacts a side part of the adjacent one of the source and drain region.
US08193910 1991-04-15 1994-02-03 Semiconductor device with buried inverse T-type field region Expired - Lifetime US5391907A (en)

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KR910006019A KR950000103B1 (en) 1991-04-15 1991-04-15 Manufacturing method of semiconductor device
KR6019/1991 1991-04-15
US07856020 US5182226A (en) 1991-04-15 1992-03-23 Method for fabrication of a field oxide of the buried inverse t-type using oxygen or nitrogen ion implantation
US97497892 true 1992-11-12 1992-11-12
US08193910 US5391907A (en) 1991-04-15 1994-02-03 Semiconductor device with buried inverse T-type field region

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US08193910 Expired - Lifetime US5391907A (en) 1991-04-15 1994-02-03 Semiconductor device with buried inverse T-type field region

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US5962914A (en) * 1998-01-14 1999-10-05 Advanced Micro Devices, Inc. Reduced bird's beak field oxidation process using nitrogen implanted into active region
US6033943A (en) * 1996-08-23 2000-03-07 Advanced Micro Devices, Inc. Dual gate oxide thickness integrated circuit and process for making same
US6040607A (en) * 1998-02-23 2000-03-21 Advanced Micro Devices, Inc. Self aligned method for differential oxidation rate at shallow trench isolation edge
US20010055838A1 (en) * 2000-04-28 2001-12-27 Matrix Semiconductor Inc. Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication
US20020028541A1 (en) * 2000-08-14 2002-03-07 Lee Thomas H. Dense arrays and charge storage devices, and methods for making same
US20020142546A1 (en) * 2001-03-28 2002-10-03 Matrix Semiconductor, Inc. Two mask floating gate EEPROM and method of making
US20030030074A1 (en) * 2001-08-13 2003-02-13 Walker Andrew J TFT mask ROM and method for making same
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US6580124B1 (en) 2000-08-14 2003-06-17 Matrix Semiconductor Inc. Multigate semiconductor device with vertical channel current and method of fabrication
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US5182226A (en) 1993-01-26 grant
JPH0697678B2 (en) 1994-11-30 grant
KR950000103B1 (en) 1995-01-09 grant
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JPH0590401A (en) 1993-04-09 application
DE4212503A1 (en) 1992-10-22 application
DE4212503C2 (en) 1994-09-22 grant

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