Decimal multiplying assembly and multiply module
Download PDFInfo
 Publication number
 US5379245A US5379245A US08001079 US107993A US5379245A US 5379245 A US5379245 A US 5379245A US 08001079 US08001079 US 08001079 US 107993 A US107993 A US 107993A US 5379245 A US5379245 A US 5379245A
 Authority
 US
 Grant status
 Grant
 Patent type
 Prior art keywords
 module
 decimal
 digit
 order
 multiplication
 Prior art date
 Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
 Expired  Fee Related
Links
Images
Classifications

 G—PHYSICS
 G06—COMPUTING; CALCULATING; COUNTING
 G06F—ELECTRICAL DIGITAL DATA PROCESSING
 G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
 G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
 G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using noncontactmaking devices, e.g. tube, solid state device; using unspecified devices
 G06F7/491—Computations with decimal numbers radix 12 or 20.
 G06F7/4915—Multiplying; Dividing
Abstract
Description
The present invention relates to a decimal multiplying assembly and a multiply module for use in a multiplying assembly. More particularly, it relates to a decimal multiplying assembly and a multiply module for a highspeed multiplication of decimal multidigit operands.
An example of a conventional decimal multiplying device is shown in FIG. 1, in which each of a decimal Ndigit multiplicand and a decimal Mdigit multiplier is converted to a binarycoded decimal operands by a decimaltobinary converter 11 or 12 before multiplication thereof. Multiplication is carried out by a software program for calculating a product of binarycoded decimal operands in a binary mutiplying member 13, the output of which is then converted again to a final decimal product by a binarytodecimal converter 14.
With another conventional decimal multiplying device, a decimal multiplication table for decimal operands of limited digits in length is stored in a memory of the multiplying device. The table is retrieved as many times as necessary according to the numbers of digits of the multiplier and the multiplicand to be calculated. The resultant data of each retrieval is collected and combined together for obtaining the decimal product by a software program.
Each of the conventional multiplying devices as described above has a disadvantage in which the software program for calculating a product is complicated, hence requiring a large amount of time when the size of the multiplier and the multiplicand are large in length.
An object of the present invention is to provide a multiply module and a multiply module group for use in a decimal multiplying assembly in which highspeed calculation of a product can be obtained.
Another object of the present invention is to provide a multiplying assembly in which a large amount of processing time is not required due to the modular structure of a multiplying assembly having highspeed multiply modules.
According to the present invention, there is provided a first type of multiply module for a multiplicand and a multiplier each of a binarycoded decimal number of a single decimal digit, for use in a decimal multidigit multiplying assembly. The multiply module comprises: an input group receiving the multiplicand and multiplier: a hardwired circuit responsive to the multiplicand and multiplier for generating a binarycoded decimal data representing a product of the multiplicand by the. multiplier; a first output member for outputting a decimal highorder digit of the decimal data; and a second output member for outputting a decimal loworder digit of the decimal data.
The "hardwired circuit" as used in this text is meant by a wired circuit which is not operated by a software program.
A second type of multiply module according to an embodiment of the present invention can additionally receive a carry from another module. A third type of multiply module according to an embodiment of the present invention can receive two carries. These carries are added to the product of the operands of a single decimal digit. The first and second types of modules can be combined to a first module group operating multiplication of a decimal multidigit number by a decimal singledigit number. The second and third types of modules can be combined to a second module group for multiplication of a decimal multidigit number by a decimal singledigit number. The first and second types of module groups are combined to form a multiplying assembly. The multiplying assembly functions multiplication of decimal multidigit operands in a highspeed.
The multiply module can be implemented by a memory such as a readonly memory or a set of logic gates such as a programmable logic array.
Other and further objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings in which:
FIG. 1 is a block diagram showing an example of a conventional multiplying device;
FIG. 2 is a block diagram showing a decimal multiplying assembly according to an embodiment of the present invention;
FIG. 3 is a block diagram showing an embodiment of a multiply module according to the present invention, adapted for the first basic module in the multiplying assembly of FIG. 2;
FIGS. 4A to 4H are block diagrams showing another embodiment of a multiply module according to the present invention, adapted for the first basic module in the multiplying assembly of FIG. 2;
FIG. 5 is a block diagram showing still another embodiment of a multiply module according to the present invention, adapted for the second basic module in the mutiplying assembly of FIG. 2;
FIG. 6 is a block diagram showing still another embodiment of a multiply module according to the present invention, adapted for the third basic module in the multiplying assembly of FIG. 2;
FIG. 7 is a block diagram showing an embodiment of a multiply module group according to the present invention, adapted for the first, module group in the multiplying assembly of FIG. 2; and
FIG. 8 is a block diagram showing another embodiment of a multiply module group according to the present invention, adapted for the second module group in the multiplying assembly of FIG. 2.
FIG. 2 shows a decimal multiplying assembly according to an embodiment of the present invention. The multiplying assembly is designed for multiplication of a decimal multiplicand of 1 to N digits in length by a decimal multiplier of 1 to M digits in length. The decimal multiplying assembly comprises N×M multiply modules each operating multiplication of operands of a single decimal digit, and most of them additionally operate summation of the product and an input carry or carries from another module or other modules. Each column corresponding to each decimal digit B_{o}. . . ,B_{M1} of the multiplier constitutes a module group 21, 22, . . . ,2M, which comprises N multiply modules and performs multiplication of a decimal multiplicand of N digits by a decimal multiplier of a single digit.
Each of the module groups 21, . . . ,2M is supplied with the multiplicand in such a way that each digit A_{o}, . . . ,A_{N1} of the multiplicand is respectively supplied to a corresponding module disposed in each of the module groups 21, . . . ,2M. The modules are so cascaded to each other in each column that a carry component or a highorder digit of the product or data obtained by a module is transferred through the carryout C_{o} of the module to a carryin C_{i} of the adjacent module for the adjacent higher order digit of the multiplicand.
Each of the module groups 21, . . . ,2M is supplied with a corresponding order digit of the digits B_{o} to B_{M1} of the multiplier. Each of the module groups is shown as being shifted upward one point in the location from the adjacent module group for adjacent lower order digit of the multiplier shown at the left. Hence, module groups 21, . . . ,2M are cascaded to each other in such a way that a product component or loworder digit of the product or data is transferred from a productout m_{o} of a module in a column to a carryin c_{i} or a productin m_{i} of the other module for the adjacent higher order digit of the multiplicand disposed in the adjacent column for the adjacent higher order digit of the multiplier.
The decimal multiplying assembly as described above includes three types of multiply modules referred to as a first, second and third basic module, respectively. The first basic module is disposed for the loworder digit A_{o} of the multiplicand in the module group 21 of a first type referred to as a first module group corresponding to the loworder digit B_{o} of the multiplier. The first basic module has two inputs including a multiplicand input a_{i} and a multiplier input b_{i} and two outputs including a carryout output c_{o} and a productout output m_{o}.
The second basic modules are provided as the remaining multiply modules in the module group 21 and as the modules corresponding to the loworder digit A_{o} of the multiplicand in the other module groups 22, . . . ,2M of a second type each referred to as a second module group. The second basic modules each has a carryin input c_{i} additionally to the two operand inputs a_{i}, b_{i} and two outputs c_{o}, m_{o}. The third basic multiply modules are provided as the remaining multiply modules in the multiplying assembly of FIG. 2. The third basic module has two carryin inputs c_{i}, m_{i} additionally to the two operand inputs a_{i}, b_{i} and two outputs c_{o}, m_{o}.
FIG. 3 shows an embodiment of a multiply module according to the present invention applicable to the first basic multiply module in FIG. 2. The multiply module MPL1 of FIG. 3 is constituted by a memory such as a readonly memory comprising two address members a_{i} and b_{i} each supplied with a multiplicand A_{n} and a multiplier B_{m} each of a binarycoded decimal number of a single decimal digit, respectively, 10×10 memory elements which can be accessed by the multiplier A_{n} and the multiplicand B_{m}, and two output members c_{o} and m_{o}. The data stored in each memory element has a twodigit decimal data, i.e. a 8bit binary data.
The higher four bits of the data stored in a memory element represent the highorder decimal digit or carry component of the product of the two addresses accessing the memory element, while the lower four bits represent the loworder decimal digit or product component M_{n},m of the product of the addresses. Hence, the two outputs C_{n},m and M_{n},m of the multiply module MPL1, when combined together, have a data representing a binarycoded decimal product of the two inputs or operands A_{n} and B_{m}.
The data C_{n},m and M_{n},m stored in the memory element accessed by the operands A_{n} and B_{m} is shown in a decimal representation in Tables 1 and 2, respectively, with all possible combinations of inputs A_{n} and B_{m}.
(TABLE 1)______________________________________DATA TABLE of Cn,mBm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 02 0 0 0 0 0 1 1 1 1 13 0 0 0 0 1 1 1 2 2 24 0 0 0 1 1 2 2 2 3 35 0 0 1 1 2 2 3 3 4 46 0 0 1 1 2 3 3 4 4 57 0 0 1 2 2 3 4 4 5 68 0 0 1 2 3 4 4 5 6 79 0 0 1 2 3 4 5 6 7 8______________________________________
(TABLE 2)______________________________________DATA TABLE of Mn,mBm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 1 2 3 4 5 6 7 8 92 0 2 4 6 8 0 2 4 6 83 0 3 6 9 2 5 8 1 4 74 0 4 8 2 6 0 4 8 2 65 0 5 0 5 0 5 0 5 0 56 0 6 2 8 4 0 6 2 8 47 0 7 4 1 8 5 2 9 6 38 0 8 6 4 2 0 8 6 4 29 0 9 8 7 6 5 4 3 2 1______________________________________
The basic module as described above has no software program within the module, so that a highspeed calculation can be obtained.
A decimal multiply module according to another embodiment of the present invention, applicable to a first basic module in the multiplying assembly of FIG. 2, may be implemented by a set of logic gates, for example, a programmable logic array (PLA) instead of a memory. The PLA module is supplied with binarycoded decimal operand A_{n} and B_{m} each of a single decimal digit as its termforproducts, and outputs two binarycoded decimal data C_{n},m and M_{n},m as its sumofproducts.
Sumofproduct group (Cn,m)_{3}, (Cn,m)_{2} (Cn,m)_{1} and (Cn,m)_{o} follows the truth tables listed in Tables 31 to 34 with all possible combinations of inputs A_{n} and B_{m}, while sumofproduct group (Mn,m)_{3}, (Mn,m)_{2}, (Mn,m)_{1} and (Mn,m)_{o} follows the truth tables listed in Tables 41 to 44 with all possible combinations of inputs A_{n} and B_{m}.
(TABLE 31)______________________________________(Cn,m).sub.3Bm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 02 0 0 0 0 0 0 0 0 0 03 0 0 0 0 0 0 0 0 0 04 0 0 0 0 0 0 0 0 0 05 0 0 0 0 0 0 0 0 0 06 0 0 0 0 0 0 0 0 0 07 0 0 0 0 0 0 0 0 0 08 0 0 0 0 0 0 0 0 0 09 0 0 0 0 0 0 0 0 0 1______________________________________
(TABLE 32)______________________________________(Cn,m).sub.2Bm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 02 0 0 0 0 0 0 0 0 0 03 0 0 0 0 0 0 0 0 0 04 0 0 0 0 0 0 0 0 0 05 0 0 0 0 0 0 0 0 1 16 0 0 0 0 0 0 0 1 1 17 0 0 0 0 0 0 1 1 1 18 0 0 0 0 0 1 1 1 1 19 0 0 0 0 0 1 1 1 1 0______________________________________
(TABLE 33)______________________________________(Cn,m).sub.1Bm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 02 0 0 0 0 0 0 0 0 0 03 0 0 0 0 0 0 0 1 1 14 0 0 0 0 0 1 1 1 1 15 0 0 0 0 1 1 1 1 0 06 0 0 0 0 1 1 1 0 0 07 0 0 0 1 1 1 0 0 0 18 0 0 0 1 1 0 0 0 1 19 0 0 0 1 0 0 0 1 1 0______________________________________
(TABLE 34)______________________________________(Cn,m).sub.0Bm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 0 02 0 0 0 0 0 1 1 1 1 13 0 0 0 0 1 1 1 0 0 04 0 0 0 1 1 0 0 0 1 15 0 0 1 1 0 0 1 1 0 06 0 0 1 1 0 1 1 0 0 17 0 0 1 0 0 1 0 0 1 08 0 0 1 0 1 0 0 1 0 19 0 0 1 0 1 0 1 0 1 0______________________________________
(TABLE 41)______________________________________(Mn,m).sub.3Bm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 0 0 0 0 1 12 0 0 0 0 1 0 0 0 0 13 0 0 0 1 0 0 1 0 0 04 0 0 1 0 0 0 0 1 0 05 0 0 0 0 0 0 0 0 0 06 0 0 0 1 0 0 0 0 1 07 0 0 0 0 1 0 0 1 0 08 0 1 0 0 0 0 1 0 0 09 0 1 1 0 0 0 0 0 0 0______________________________________
(TABLE 42)______________________________________(Mn,m).sub.2Bm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 0 0 0 1 1 1 1 0 02 0 0 1 1 0 0 0 1 1 03 0 0 1 0 0 1 0 0 1 14 0 1 0 0 1 0 1 0 0 15 0 1 0 1 0 1 0 1 0 16 0 1 1 0 1 0 1 0 0 17 0 1 1 0 0 1 0 0 1 08 0 0 0 0 0 0 0 0 0 09 0 0 0 1 1 1 1 0 0 0______________________________________
(TABLE 43)______________________________________(mn,m).sub.1Bm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 0 1 1 0 0 1 1 0 02 0 1 0 1 0 0 1 0 1 03 0 1 1 0 1 0 0 0 0 14 0 0 0 1 1 0 0 0 1 15 0 0 0 0 0 0 0 0 0 06 0 1 1 0 0 0 1 1 0 07 0 1 0 0 0 0 1 0 1 18 0 0 1 0 1 0 0 1 0 19 0 0 0 1 1 0 0 1 1 0______________________________________
(TABLE 44)______________________________________Bm ↓0 1 2 3 4 5 6 7 8 9 ← An______________________________________0 0 0 0 0 0 0 0 0 0 01 0 1 0 1 0 1 0 1 0 12 0 0 0 0 0 0 0 0 0 03 0 1 0 1 0 1 0 1 0 14 0 0 0 0 0 0 0 0 0 05 0 1 0 1 0 1 0 1 0 16 0 0 0 0 0 0 0 0 0 07 0 1 0 1 0 1 0 1 0 18 0 0 0 0 0 0 0 0 0 09 0 1 0 1 0 1 0 1 0 1______________________________________
The PLA module implementing the first basic multiply module is shown separately in FIGS. 4A to 4H. FIGS. 4A to 4D correspond to Tables 31 to 34, respectively, while FIGS. 4E to 4H correspond to Tables 41 to 44, respectively. In each of FIGS. 4A to 4H, both input groups of the termforproduct group (A_{n})_{3}, (A_{n})_{2}, (A_{n})_{1} and (A_{n})_{o} representing binarycoded decimal multiplicand and the termforproduct (B_{m})_{3}, (B_{m})_{2}, (B_{m})_{1} and (B_{m})_{o} representing binarycoded decimal multiplier are inputted to the respective portions of the PLA module, through which both of the carryout bit group (C_{n})_{3}, (C_{n})_{2}, (C_{n})_{1} and (C_{n})_{o} and productout bit group (M_{n},m)_{3}, (M_{n},m)_{2}, (M_{n},m)_{1} and (M_{n},m)_{o} of the product of the multiplicand A_{n} by the multiplier B_{m} are separately outputted.
Now the construction of the PLA module will be described with reference to FIGS. 4A to 4H. Each of multiplicand input bit group (A_{n})_{3}, (A_{n})_{2}, (A_{1})_{1} and (A_{n})_{o} and multiplier input bit group (B_{m})_{3}, (B_{m})_{2}, (B_{m})_{1} and (B_{m})_{o} as well as each of the compliments thereof is supplied to a respective input line of the ANDplain 41. Those dots marked at the intersections of the input lines and a particular output line perpendicular to the input lines and connected to a particular AND gate of the AND gate group, such as AND gates 4A0 to 4A19 in FIG. 4A and AND gates 4B0 to 4B19 in FIG. 4B, show that the input lines on which those dots are marked at the particular output lines are inputted to the particular AND gate.
The output of each of the AND gates, such as AND gates 4A0 to 4A19 in FIG. 4A and 4B0 to 4B19 in FIG. 4B, is inputted to an ANDOR plain 42. In FIG. 4A, for example, each of the outputs of AND gates 4A0 to 4A9 are ANDed with each of the outputs of the AND gates 4A10 to 4A19 on the ANDOR plain 42 on condition that a dot is marked at the intersection of the both output lines. These dots on the ANDOR plain 42 are marked in FIGS. 4A to 4H correspondingly to the 1s of the data marked in Tables 31 to 34 and 41 to 44. The ANDs thus obtained are supplied to the respective OR gates, for example, 4A20 to 4A29, the output of which are ORed in an OR gate, for example, 4A30 in FIG. 4A and then outputted as a bit of a carry component C_{n},m or a product component M_{n},m.
With the embodiment of FIGS. 4A to 4H, time interval between the occurrence of the input and the occurrence of the output is very small due to the logic gate construction, so that a further highspeed calculation is obtained as compared to the first embodiment implemented by a memory member.
FIG. 5 shows still another embodiment of a decimal multiply module according to the present invention, applicable to the second basic multiply module in FIG. 2. The multiply module MPL2 shown in FIG. 5 functions multiplication of operands of a single decimal digit and can receive an input carry from another multiply module such as the first basic multiply module or another second basic multiply module.
The multiply module MPL2 is constituted by a memory such as a readonly memory comprising an address group including three address members a_{i}, b_{i} and c_{i} each supplied with a multiplicand A_{n}, a multiplier B_{m} and a carry input C_{n1}, respectively. Each of the inputs A_{n}, B_{m} and C_{n1} has a binarycoded decimal data of a single decimal digit. When the multiply module MPL2 is used in the multiplying assembly of FIG. 2, the carryin input c_{i} is supplied with either a carry C_{n1},m from a carryout c_{o} of an adjacent multiply module for a lower order digit in the same module group or a carry M_{n+1},m1 from a productout m_{o} of an adjacent multiply module for a lower order digit of the multiplicand disposed in a adjacent module group for a lower order digit of the multiplier.
Each of the memory elements accessed by the three inputs A_{n}, B_{m} and, for example, C_{n1},m has a 8bit data, and the data S1 is expressed in a decimal representation by the following equation:
S1=A.sub.n ×B.sub.m +C.sub.n1,m
The higher four bits of the data S1 is outputted from the carryout C_{n},m of the module outputs, while the lower four bits of the data S1 is outputted from the productout M_{n},m of the module outputs.
The second basic multiply module can be also implemented by a set of logic gates such as a PLA module instead of a memory. The PLA module is supplied with binarycoded decimal operands A_{n}, B_{m} and a carry C_{n1},m or M_{n+1},m1 as its termforproducts and outputts binarycoded decimal data S1' including a carry component C_{n},m and a product component M_{n},m as its sumofproducts. The PLA module is constructed in such a way that, when the PLA module is supplied with data A_{n}, B_{m} and, for example, C_{n1},m, the output data S1' is expressed in a decimal representation as follows:
S1'=A.sub.n ×B.sub.m C.sub.n1,m
FIG. 6 shows still another embodiment of a decimal multiply module according to the present invention, applicable to the third basic multiply module in FIG. 2. The multiply module MPL3 shown in FIG. 6 functions multiplication of binarycoded decimal operands and can receive two carries from other modules. This module MPL3 is constituted by a memory such as a readonly memory and has four address members each supplied with a multiplicand A_{n}, a multiplier B_{m}, a first input carry C_{n1},m and a second input carry M_{n+1},1, respectively.
When the multiply module MPL3 is used in the multiplying assembly of FIG. 2, the first input carry C_{n1},m is supplied from a carryout c_{o} of an adjacent module for a lower order digit in the same module group, while the second input carry M_{n+1},m1 is supplied from a productout m_{o} of an adjacent module for a lowerorder digit A_{o} of the multiplicand disposed in a adjacent module group for a lower order digit of the multiplier.
Each of the memory elements accessed by the four inputs A_{n}, B_{m}, C_{n1},m and M_{n+1},m1 has a twodigit decimal data S2 including a highorder digit C_{n},m and a loworder digit M_{n},m the data S2 being expressed by the following equation:
S2=A.sub.n ×B.sub.m +C.sub.n1,m +M.sub.n+1,m1.
The third basic multiply module may be also implemented by a PLA instead of a memory. The PLA is supplied with inputs A_{n}, B_{m}, C_{n1},m and M_{n+1},m1 as its termforproducts and outputts binarycoded decimal data S2' including a highorder digit C_{n},m and a loworder digit M_{n},m as its sumofproducts. The PLA module is constructed in such a way that, when the PLA is supplied with data A_{n}, B_{m}, C_{n1},m and M_{n+1},m1 as its termforproducts, the output sumofproducts S2' is expressed in a decimal representation as follows:
S2'=A.sub.n ×B.sub.m +C.sub.n1.m +M.sub.n+1.m1
FIG. 7 shows an embodiment of a multiply module group according to the present invention, applicable to the first module group 21 of the multiplying assembly of FIG. 2. The module group of FIG. 7 comprises a multiply module MPL1 of FIG. 3 as its loworder module 71 for the loworder digit A_{o} of the multiplicand and a plurality of multiply modules MPL2 of FIG. 5 as its remaining modules 72 to 7M for the other digits of the multiplicand. Each of the modules 71 to 7N is supplied with a corresponding digit AO, . . . ,AN1 of a multiplicand having decimal N digits (N>=1) and a common multiplier B_{o} having a single decimal digit.
A carry component outputted from the carryout c_{o} of each of the multiply modules 71 to 7N1 is supplied to the carryin c_{i} of each of the adjacent modules 72 to 7M of the higher order position, respectively, so that the output M_{o}.o to M_{N1}.0 of the decimal multiply module group of FIG. 7 is outputted through the productout m_{o} of each of the multiply modules 71 to 7N. The carry component C_{N1}.0 of the multiply module 7N is the highorder digit of the decimal output of the module group, which is supplied to another module for the highorder digit of the multiplicand in the adjacent higher order module group in FIG. 2.
FIG. 8 shows another embodiment of a multiply module group according to the present invention, applicable to the second module groups 21, . . ,2M in the multiplying assembly of FIG. 2. The module group of FIG. 8 comprises a multiply module MPL2 of FIG. 5 as its loworder module 81 for loworder digit A_{o} of the multiplicand and a plurality of multiply modules MPL3 of FIG. 6 as its remaining modules 82 to 8N. Each module 81 to 8N is supplied with a corresponding digit A_{o},. . . ,A_{n1} of a multiplicand having decimal N digits (N>=1) and a common multiplier B_{m} having a single decimal digit.
A carry component outputted from the carryout c_{o} of each of the multiply modules 81 to 8N1 is supplied to the carryin c_{i} of the adjacent module 82 to 8N of the higher order position. The carry component C_{N1},m from the carryout c_{o} of the multiply module 8N is supplied to the module for the highorder digit A_{n1} of the multiplicand disposed in the adjacent higher order module group. Each of the product components from productout m_{o} is supplied to the adjacent module in the adjacent module group or outputted as a digit of a final product.
Turning now to FIG. 2, the operation of the multiplying assembly will be described.
When a multiplicand and a multiplier is inputted to the multiplying assembly, the multiply module 211 of the loworder position first operates with the loworder digits A_{o} and B_{o} of the inputted operands. The module 211 outputts from its productout m_{o} the loworder digit M_{o} of the final decimal product and from its carryout c_{o} a carry component to the adjacent module 212 of the next loworder position in the same module group 21.
Next, the module 212 operates with the three data A_{1}, B_{o} and the input carry supplied from the module 211, and outputts a carry and a product components. Then, the module 221 disposed adjacent to the module 212 in the next loworder module group 22 operates, and outputts a next loworder digit M_{1} of the final output product as well as a carry component. The calculation is operated likewise in sequence in the multiplying assembly without any software program or a controller, hence a highspeed calculation can be obtained. Additionally, the time required for calculation depends only on the numbers of the digits of the two operands to be calculated, so that the calculation time does not depends on the result to be obtained.
At least one of the first and the second basic modules in the multiplying assembly may be substituted by a third basic module. In this case, the carryin input not necessary for the operation is fixed at zero. Employing this configuration provides ease of fabrication.
When the multiplying assembly of FIG. 2 is implemented by multiply modules of a set of logic gates, such as PLA modules, a further highspeed operation can be obtained, since the propagation delay of the logic gates is smaller than the access time of the memory.
Since above embodiments are described only for examples, the present invention is not limited to such embodiments and it will be obvious for those skilled in the art that various modifications or alterations can be easily made based on the above embodiments under the scope of the present invention.
Claims (15)
Priority Applications (2)
Application Number  Priority Date  Filing Date  Title 

JP43444  19920113  
JP344492A JP2830566B2 (en)  19920113  19920113  Decimal multiplier 
Publications (1)
Publication Number  Publication Date 

US5379245A true US5379245A (en)  19950103 
Family
ID=11557522
Family Applications (1)
Application Number  Title  Priority Date  Filing Date 

US08001079 Expired  Fee Related US5379245A (en)  19920113  19930106  Decimal multiplying assembly and multiply module 
Country Status (2)
Country  Link 

US (1)  US5379245A (en) 
JP (1)  JP2830566B2 (en) 
Cited By (6)
Publication number  Priority date  Publication date  Assignee  Title 

US20040230631A1 (en) *  20030512  20041118  International Business Machines Corporation  Modular binary multiplier for signed and unsigned operands of variable widths 
US20050010631A1 (en) *  20030710  20050113  International Business Machines Corporation  Decimal multiplication using digit recoding 
US20050022322A1 (en) *  20030512  20050203  Eduardo Jimenez  Powered toothbrush with curved neck and flexible shaft and single battery 
US20060259530A1 (en) *  20030512  20061116  International Business Machines Corporation  Decimal multiplication for superscaler processors 
US20090234900A1 (en) *  20040807  20090917  Ternarylogic Llc  MultiValue Digital Calculating Circuits, Including Multipliers 
US20100146031A1 (en) *  20081208  20100610  International Business Machines Corporation  Direct Decimal Number Tripling in Binary Coded Adders 
Citations (3)
Publication number  Priority date  Publication date  Assignee  Title 

US4566075A (en) *  19821221  19860121  Texas Instruments Incorporated  Table lookup multiplier employing compressed data read only memory 
US5060183A (en) *  19871119  19911022  Mitsubishi Denki Kabushiki Kaisha  Parallel multiplier circuit using matrices, including half and full adders 
US5258945A (en) *  19911223  19931102  Amdahl Corporation  Method and apparatus for generating multiples of BCD number 
Family Cites Families (2)
Publication number  Priority date  Publication date  Assignee  Title 

JPS592935B2 (en) *  19761007  19840121  Nippon Telegraph & Telephone  
JPS59174944A (en) *  19830325  19841003  Hitachi Ltd  Multiplying device 
Patent Citations (3)
Publication number  Priority date  Publication date  Assignee  Title 

US4566075A (en) *  19821221  19860121  Texas Instruments Incorporated  Table lookup multiplier employing compressed data read only memory 
US5060183A (en) *  19871119  19911022  Mitsubishi Denki Kabushiki Kaisha  Parallel multiplier circuit using matrices, including half and full adders 
US5258945A (en) *  19911223  19931102  Amdahl Corporation  Method and apparatus for generating multiples of BCD number 
NonPatent Citations (2)
Title 

Maholick, "Fast BCD Multiplication Logic", IBM Technical Disclosure Bulletin, vol. 20, No. 2, 1977. 
Maholick, Fast BCD Multiplication Logic , IBM Technical Disclosure Bulletin, vol. 20, No. 2, 1977. * 
Cited By (16)
Publication number  Priority date  Publication date  Assignee  Title 

US7412476B2 (en)  20030512  20080812  International Business Machines Corporation  Decimal multiplication for superscaler processors 
US7853635B2 (en)  20030512  20101214  International Business Machines Corporation  Modular binary multiplier for signed and unsigned operands of variable widths 
US20050022322A1 (en) *  20030512  20050203  Eduardo Jimenez  Powered toothbrush with curved neck and flexible shaft and single battery 
US7490121B2 (en)  20030512  20090210  International Business Machines Corporation  Modular binary multiplier for signed and unsigned operands of variable widths 
US20060259530A1 (en) *  20030512  20061116  International Business Machines Corporation  Decimal multiplication for superscaler processors 
US7167889B2 (en)  20030512  20070123  International Business Machines Corporation  Decimal multiplication for superscaler processors 
US7266580B2 (en)  20030512  20070904  International Business Machines Corporation  Modular binary multiplier for signed and unsigned operands of variable widths 
US20070214205A1 (en) *  20030512  20070913  International Business Machines Corporation  Modular binary multiplier for signed and unsigned operands of variable widths 
US20070233773A1 (en) *  20030512  20071004  International Business Machines Corporation  Modular binary multiplier for signed and unsigned operands of variable widths 
US20040230631A1 (en) *  20030512  20041118  International Business Machines Corporation  Modular binary multiplier for signed and unsigned operands of variable widths 
US7136893B2 (en)  20030710  20061114  International Business Machines Corporation  Decimal multiplication using digit recoding 
US20050010631A1 (en) *  20030710  20050113  International Business Machines Corporation  Decimal multiplication using digit recoding 
US20090234900A1 (en) *  20040807  20090917  Ternarylogic Llc  MultiValue Digital Calculating Circuits, Including Multipliers 
US8209370B2 (en) *  20040807  20120626  Ternarylogic Llc  Multivalue digital calculating circuits, including multipliers 
US20100146031A1 (en) *  20081208  20100610  International Business Machines Corporation  Direct Decimal Number Tripling in Binary Coded Adders 
US8417761B2 (en)  20081208  20130409  International Business Machines Corporation  Direct decimal number tripling in binary coded adders 
Also Published As
Publication number  Publication date  Type 

JP2830566B2 (en)  19981202  grant 
JPH076024A (en)  19950110  application 
Similar Documents
Publication  Publication Date  Title 

US3636334A (en)  Parallel adder with distributed control to add a plurality of binary numbers  
Garner  Number systems and arithmetic  
US6041340A (en)  Method for configuring an FPGA for large FFTs and other vector rotation computations  
US5764558A (en)  Method and system for efficiently multiplying signed and unsigned variable width operands  
US4074351A (en)  Variable function programmed calculator  
US4607176A (en)  Tally cell circuit  
US4620188A (en)  Multilevel logic circuit  
US5095460A (en)  Rotating priority encoder operating by selectively masking input signals to a fixed priority encoder  
US7467175B2 (en)  Programmable logic device with pipelined DSP slices  
US5187679A (en)  Generalized 7/3 counters  
US4485455A (en)  Singlechip semiconductor unit and key input for variable function programmed system  
US20050125478A1 (en)  Smaller and lower power static mux circuitry in generating multiplier partial product signals  
US5956265A (en)  Boolean digital multiplier  
US6021423A (en)  Method for parallelefficient configuring an FPGA for large FFTS and other vector rotation computations  
US5978827A (en)  Arithmetic processing  
Taylor  A VLSI residue arithmetic multiplier  
US4287566A (en)  Array processor with parallel operations per instruction  
US3711692A (en)  Determination of number of ones in a data field by addition  
US4626825A (en)  Logarithmic conversion apparatus  
US4682303A (en)  Parallel binary adder  
US5151875A (en)  MOS array multiplier cell  
US4354249A (en)  Processing unit for multiplying two mathematical quantities including at least one complex multiplier  
US4623982A (en)  Conditional carry techniques for digital processors  
US5465226A (en)  High speed digital parallel multiplier  
US3535502A (en)  Multiple input binary adder 
Legal Events
Date  Code  Title  Description 

AS  Assignment 
Owner name: NEC CORPORATION, JAPAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:UEDA, TSUGUO;REEL/FRAME:006395/0094 Effective date: 19921218 

SULP  Surcharge for late payment  
FPAY  Fee payment 
Year of fee payment: 4 

FPAY  Fee payment 
Year of fee payment: 8 

REMI  Maintenance fee reminder mailed  
LAPS  Lapse for failure to pay maintenance fees  
FP  Expired due to failure to pay maintenance fee 
Effective date: 20070103 