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US5221413A - Method for making low defect density semiconductor heterostructure and devices made thereby - Google Patents

Method for making low defect density semiconductor heterostructure and devices made thereby Download PDF

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US5221413A
US5221413A US07690429 US69042991A US5221413A US 5221413 A US5221413 A US 5221413A US 07690429 US07690429 US 07690429 US 69042991 A US69042991 A US 69042991A US 5221413 A US5221413 A US 5221413A
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silicon
ge
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substrate
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Daniel Brasen
Eugene A. Fitzgerald, Jr.
Martin L. Green
Ya-Hong Xie
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Nokia Bell Labs
AT&T Corp
Agere Systems Optoelectronics Guardian Corp
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Abstract

The present invention is predicated upon the discovery by applicants that by growing germanium-silicon alloy at high temperatures in excess of about 850° C. and increasing the germanium content at a gradient of less than about 25% per micrometer, one can grow on silicon large area heterostructures of graded Gex Si1-x alloy having a low level of threading dislocation defects. With low concentrations of germanium 0.10≦×≦0.50), the heterolayer can be used as a substrate for growing strained layer silicon devices such as MODFETS. With high concentrations of Ge (0.65≦×≦1.00) the heterolayer can be used on silicon substrates as a buffer layer for indium gallium phosphide devices such as light emitting diodes and lasers. At concentrations of pure germanium (X=1.00), the heterolayer can be used for GaAs or GaAs/AlGaAs devices.

Description

FIELD OF THE INVENTION

This invention relates to a method for making a semiconductor heterostructure of germanium-silicon alloy that has low threading dislocation density in the alloy layer and to devices made thereby. Such low defect structures are particularly useful as buffer layers for making semiconductor devices comprising indium gallium phosphide, gallium arsenide or strained layers of silicon.

BACKGROUND OF THE INVENTION

There is considerable interest in heterostructure devices involving greater epitaxial layer thickness and greater lattice misfit than present technology will allow. For example, it has long been recognized that germanium-silicon alloy Gex Sil-x grown on silicon substrates would permit a variety of optoelectronic devices, such as LEDs, marrying the electronic processing technology of silicon VLSI circuits with the optical component technology available in direct band semiconductors. Indeed, it has been proposed that an intermediate epitaxial layer of germanium-silicon alloy would permit the epitaxial deposition of gallium arsenide overlying a silicon substrate and thus permit a variety of new optoelectronic devices using silicon electronic components and gallium arsenide optical components. However, despite the widely recognized potential advantages of such combined structures and despite substantial efforts to develop them, their practical utility has been limited by high defect densities in heterostructure layers grown on silicon substrates.

Dislocation defects partition an otherwise monolithic crystal structure and introduce unwanted and abrupt changes in electrical and optical properties. Dislocation defects arise in efforts to epitaxially grow one kind of crystalline material on a substrate of a different kind of material due to different crystal lattice sizes of the two materials. Dislocations from at the mismatched interface to relieve the misfit strain. Many of the misfit dislocations have vertical components, termed threading segments, which extend at a slant angle through any subsequent layers. Such threading defects in the active regions of semiconductor devices seriously degrade device performance.

A variety of approaches have been used to reduce dislocations with varying degrees of success. One approach is to limit the heterolayer to a thin layer of material that has a lattice crystal structure closely matching the substrate. Typically the lattice mismatch is within 1% and thickness of the layer is kept below a critical thickness for defect formation. In such structures, the substrate acts as a template for growth of the heterolayer which elastically conforms to the substrate temperature. While this approach eliminates dislocations in a number of structures, there are relatively few near lattice-matched systems with large energy band offers. Thus with this approach the design options for new devices are limited.

A second approach set forth in the copending application of E. A. Fitzgerald, Ser. No. 07/561,774 filed Aug. 2, 1990 new U.S. Pat. No. 5,158,907 utilizers heterolayers of greater thickness but limited lateral area. By making the thickness sufficiently large as compared with the lateral dimension, threading dislocations are permitted to exit the sides of layer. The upper surface is thus left substantially free of defects. This approach permits the fabrication of a variety of devices and circuits which can be made on limited area surfaces having an area of less than about 10,000 square micrometers.

A third approach is to deposit successive layers of germanium-silicon alloy on a silicon substrate, increasing the germanium content with each successive layer. The goal is to avoid dislocations by spreading the strain among successive layers. Unfortunately this approach has not worked. For example, it has been found that step grading 20% Ge over 2000 angstroms to produce pure Ge results in substantially the same high dislocation density as depositing pure Ge on Si. See J. M. Baribeau et al., 63 Journal of Applied Physics 5738 (1988). Applicants believe that this approach fails because at conventional growth temperatures--typically about 550° C.--the initial layer of Si--Ge is almost entirely elastically strained. Thus when the next layer of Si--Ge with greater germanium content is applied, the mismatch between the two Si--Ge layers is nearly that between the initial Si--Ge layer and the Si substrate, resulting in high dislocation density. Accordingly, there is a need for a method of making large area, low defect heterostructures on silicon.

SUMMARY OF THE INVENTION

The present invention is predicated upon the discovery by applicants that by growing germanium-silicon alloy at high temperatures in excess of about 850° C. and increasing the germanium content at a gradient of less than about 25% per micrometer, one can grow on silicon large area heterostructures of graded Gex Sil-x alloy having a low level of threading dislocation defects. With low concentrations of germanium 0.10≦×≦0.50), the heterolayer can be used as a substrate for growing strained layer silicon devices such as MODFETS. With high concentrations of Ge (0.65≦x≦1.00) the heterolayer can be used on silicon substrates as a buffer layer for indium gallium phosphide devices such as light emitting diodes and lasers. At concentrations of pure germanium (X=1.00), the heterolayer can be used for GaAs or GaAs/AlGaAs devices.

BRIEF DESCRIPTION OF THE DRAWING

The advantages, nature and various additional features of the invention will appear more fully upon consideration of the illustrative embodiments now to be described in detail. In the drawings:

FIG. 1 is a block diagram illustrating the method of making a low defect density semiconductor heterostructure in accordance with the invention;

FIG. 2 is a schematic cross section of a strained silicon layer MODFET made in accordance with the invention;

FIG. 3 is a schematic cross section of an indium gallium arsenide surface emitting LED made in accordance with the invention; and

FIG. 4 is a schematic cross section of a gallium arsenide LED with integrated drive transistor made in accordance with the invention.

It is to be understood that these drawings are for purposes of illustrating the concepts of the invention and are not to scale.

DETAILED DESCRIPTION

Referring to the drawings. FIG. 1 is a flow diagram illustrating the process for making a low defect density semiconductor heterostructure in accordance with the invention. As shown, the first step is providing a silicon substrate. Preferably the substrate is a standard (100) oriented silicon wafer of the type typically used in the fabrication of integrated circuits. Advantageously, as a preliminary step, the substrate is provided with one or more large area recessed tubs by conventional photolithographic patterning and etching. The tubes can have an area in excess of 12,000 square micrometers and a depth of several micrometers, depending upon the thickness of germanium-silicon alloy to be grown. The objective is to provide a type of proper depth so that a germanium-silicon alloy layer grown in the tub will be substantially coplanar with the non-recessed portion of the silicon substrate.

The second step of the process is to grow at high temperature on the silicon substrate a large area, graded layer of germanium-silicon alloy, Gex Si1-x. The growth process is preferably chemical vapor deposition (CVD) or molecular beam epitaxy (MBE). The substrate growth starting temperature should be in the range 850° C.-1100° C., and the area of the graded alloy can exceed 12,000 square micrometers. The starting composition is preferably pure silicon. Germanium is introduced to form Gex Si1-x at a gradient of less than about 25% per micron. Preferably the grading is linear at a rate of about 10% per micron. Alternatively the grading can be stepwise at similar gradients. As the germanium content of the alloy increases, the growth temperature is advantageously scaled down in proportion to the reduced melting temperature of the alloy. The objective is to avoid melting the alloy. Graded growth of Gex Sil-x is continued until a desired final composition is reached.

The choice of final composition depends upon the intended use of the heterostructure. If, for example, the structure is to be used as a substrate for growing a strained layer silicon device, the final Ge concentration should fall within the range of 10-50%. If the structure is to be used as a substrate for an indium gallium phosphide device, the final Ge concentration should fall within the range of 65-100%. On the other hand, if the structure is to be used as a substrate for GaAs or GaAs/AlGaAs devices, the Ge concentration is preferably about 100%.

After the desired final composition is reached, an optional cap layer with the same final composition can be grown on the graded layer to a thickness in excess of 100 angstroms and preferably in excess of one micrometer. The effect of the cap layer is to further relax the low level of residual strain at the top of the graded layer.

The fabrication and structure of the invention can be understood in greater detail by consideration of the following specific examples.

EXAMPLE 1 Heterostructure Substrate (MBE)

A (100) oriented silicon substrate is provided with a large area rectangular tube approximately ten micrometers deep by covering the major surface with a masking layer of silicon oxide, etching a rectangular opening in the oxide mask to define the periphery of the tube, and then etching the exposed silicon with ethylene-diamine-pyrocatechol (EDP). The EDP etch produces smooth tube surfaces with sidewalls in the (111) planes of the silicon substrate. The substrate is then cleaned with a 3:1 mixture of H2 SO4 and H2 O2 for ten minutes and with buffered HF for 1 minutes.

The cleaned substrate is placed in a Riber EVA 32 Silicon MBE Apparatus controlled by a Sentinel 3 Deposition Rate Controller. The chamber is evacuated to a pressure of less than 10-9 Torr, and any oxide on the tube surfaces is dissociated by heating the substrate to about 800° C. and applying a low flux silicon beam at a rate of about 0.05 angstrom/s. Silicon growth at higher rate is continued to a thickness of about 0.1 micrometer to form a silicon buffer layer.

After formation of the buffer layer, the substrate temperature is increased to about 900° C. and the graded is grown. Graded growth is begun with pure silicon at a rate of about 3 angstroms per second. The total growth rate is kept constant while introducing germanium at a linear gradient of about 10% per micrometer. The objective is to keep growth near thermal equilibrium. The parameter variations for graded growth to 100% germanium at 10% per micrometer grading are set forth in the Table 1, giving thickness, percent of Germanium, temperature and current rates at various times into growth.

                                  TABLE 1__________________________________________________________________________PARAMETER VARIATIONS FOR 10%/micron GRADINGStarting Rates (Sentinel): Si/Ge = 67.8/0.5time into growth (min)       t(μ)          Ge %              liquidus (C/K)                      % T                         T substrate (C.)                                 Current Rates (Sentinel):__________________________________________________________________________                                 Si/Ge 0          0   0  1414/1687                      100                         900     67.8/0.5 27         0.486           5  1402/1675                      99.3                         892     64.4/3.5 54         0.972          10  1390/1663                      98.6                         884     61.0/6.7 81         1.458          15  1375/1648                      97.7                         873     57.6/10.5108         1.944          20  1362/1635                      96.9                         864     54.2/14.0135         2.430          25  1350/1623                      96.2                         855     50.9/17.5162         2.916          30  1335/1608                      95.3                         845     47.5/21.0189         3.402          35  1320/1593                      94.4                         834     44.1/24.5216         3.888          40  1305/1578                      93.5                         824     40.7/28.0243         4.374          45  1290/1563                      92.6                         813     37.3/31.5270         4.860          50  1270/1543                      91.5                         800     33.9/34.9297         5.346          55  1255/1528                      90.6                         790     30.5/38.4324         5.832          60  1235/1508                      89.4                         776     27.1/41.9351         6.318          65  1210/1483                      87.9                         758     23.7/45.4378         6.804          70  1185/1458                      86.4                         740     20.3/48.9405         7.290          75  1160/1433                      84.9                         722     17.0/52.4432         7.776          80  1130/1403                      83.2                         703     13.6/55.9459         8.262          85  1100/1373                      81.4                         681     10.2/59.4486         8.748          90  1055/1328                      78.7                         650      6.8/62.9513         9.234          95  1010/1283                      76.0                         618      3.4/66.4540         9.720          100  938/1211                      71.8                         569      0.5/69.9__________________________________________________________________________

After 100% germanium is reached, a final germanium cap layer having a thickness in the range between 1000 angstroms and one micrometer is grown on top.

Structures with less than 100% germanium can be obtained by terminating graded growth at the desired germanium concentration and growing the final cap layer at the concentration.

Example 2 Heterostructure Substrate (CVD)

As preliminary steps, a 100 mm (100) Si wafer was cleaned in dilute HF (1% in H2 O) and spin-dried in N2. The wafer was loaded into an RTCVD reactor and pumped down to a base pressure of 10-7 Torr. The wafer was heated to 1000° C. or 15 seconds in flowing H2 (3 lpm) to remove residual oxygen and carbon, and then cooled in 2 seconds to 900° C.

After these preliminary steps, deposition was commenced by depositing a Si buffer layer approximately 1000 Å thick. This was accomplished using SiH2 Cl2 (1% in H2, 1 lpm) for 1 minute at a pressure of about 4 Torr. Immediately thereafter, GeH4 (1%GeH4 in H2) was introduced gradually to create a Si--Ge alloy layer that increased from 0 to 50% Ge. The GeH4 flow can be increased by 4 sccm flow increments every 40 seconds. The SiH2 Cl2 was decreased by the same flow increment in the same time scale; thus, the total GeH4 and SiH2 Cl2 flow was maintained at 1 lpm. Deposition at 900° C. resulted in a Si--Ge graded alloy layer that continually relaxed as it was grown.

Heterostructures fabricated as described in Examples 1 and 2 demonstrate a reduction in defects as compared with conventionally fabricated heterostructures. Triple crystal X-ray diffraction shows that for 0.10<x<0.50, the layers are totally relaxed. The Gex Sil-x cap layers, when examined by plan-view and cross-sectional transmission electron microscopy are threading dislocation free. Electron beam induced current images revealed low threading dislocation densities of 4×105 ±5×104 cm-2 for X=0.25 and 3×104 ±2×106 cm-2 for x=0.50. Photoluminescence spectra from the cap layers are substantially identical to photoluminescence from bulk Gex Sil-x.

These low defect heterostructures can serve as buffer layers for epitaxially growing a wide variety of devices varying from those employing strained layers of silicon to those employing III-V semiconductors.

FIG. 2 is a schematic cross section of a device employing a low defect heterostructure to produce a strained silicon MODFET. In essence the MODFET is fabricated on a heterostructure comprising a Gex Sil-x cap layer 1 grown on a graded layer 2, all disposed on a silicon substrate 3. The heterostructure is fabricated as described above, with a maximum concentration of germanium in the range (0.10≦x≦0.50) and preferably with x=0.30.

The MODFET fabricated on the heterolayer comprises, in essence, a strained layer of silicon 4 epitaxially grown on layer 1. Another layer 5 of Gex Sil-x (initially intrinsic but n-doped after 50 to 900 angstroms) is grown over the silicon and, n+ spaced apart contact regions 6A and 6B are formed to contact the strained silicon layer 4. Ohmic contacts 8A and 8B are made with the n+ contact regions 6A and 6B, and a Schottky barrier contact 7 to layer 5 is disposed between the spaced apart ohmic contacts. A dielectric layer 9 advantageously separates the contacts 7, 8A, and 8B.

Silicon layer 4 preferably has a thickness in the range 100 angstroms to 1000 angstroms and is preferably undoped.

Gex Sil-x layer 5 preferably has a thickness in the range 50 angstroms to 1000 angstroms. Layer 5 is preferably intrinsic for 50 to 900 angstroms and then n+ doped with antimony, phosphorus or arsenic to a concentration in the range 1×1017 /cm3 -5×1018 /cm2. Layer 5 preferably has a concentration of Ge not less than that of cap layer 1.

The n+ contact regions 6A and 6B are preferably formed by implanting antimony, arsenic or phosphorus to silicon layer 4 at a concentration of 1019 /cm3. The ohmic contacts 8A and 8B can be layers of aluminum and the Schottky contact 7 can be a layer of platinum.

The resulting MODFET acts as a field effect transistor with the advantage of higher speed. The application of a signal voltage bias to the Schottky contact 7 (commonly known as the gate) changes the electron density inside the Si layer 4, which in turn changes the sheet conductance of the channel between 8A and 8B and results in transistor action. The strained silicon layer is a particularly high speed path for at least three reasons: 1) the straining of the silicon alters the energy bands of the silicon to favor conduction by low effective mass, high mobility electrons, 2) the silicon layer is free of impurities to interfere with electron flow, and 3) the silicon layer grown on a low defect substrate has a low concentration of defects to interfere with electron flow.

FIG. 3 is a schematic cross section of an indium gallium arsenide surface emitting LED fabricated on a heterolayer in accordance with the invention. Specifically, the LED 20 is fabricated on a heterostructure comprising a Gex Sil-x layer 12 grown within a large area tub 11 on a silicon substrate 10. The heterostructure is fabricated essentially as described above, except that the Gex Sil-x is doped with p-type impurities, such as Be, to a concentration of 1018 cm-3.

The LED 20 is fabricated on the Gex Sil-x using conventional processes such as chemical beam epitaxy to form the constituent layers 21-25 whose thicknesses, constituency and doping are set forth in table 2 below:

              TABLE 2______________________________________Lay-er                                   Concen-No.  Composition   Thickness   Dopant                                tration______________________________________21   In.sub.y (Ga.sub.1-z Al.sub.z).sub.1-y P                1 micrometer                          n.sup.+ (Si)                                10.sup.18 cm.sup.-322   In.sub.w (Ga.sub.1-x Al.sub.x).sub.1-w P              0.5 micrometer                          n(Si) 10.sup.17 cm.sup.-323   In.sub.u (Ga.sub.1-v Al.sub.v).sub.1-u P              0.2 micrometer                          none  intrinsic24   In.sub.w (Ga.sub.1-x Al.sub.x).sub.1-w P              0.5 micrometer                          p(Be) 10.sup.17 cm.sup.-325   In.sub.y (Ga.sub.1-z Al.sub.z).sub.1-y P                1 micrometer                          p.sup.+ (Be)                                10.sup.18 cm.sup.-3______________________________________

After the constituent layers are grown, the next step is to form ohmic contacts and to isolate the device. Ohmic contact 26 is formed to contact p-doped layer 25 by depositing a layer of gold-zinc alloy and photolithographically patterning the metal to form a annular ring.

To isolate the diode, the portion of layers 22-25 outside the metal contact ring 26 can be etched away. Using a photoresist circle as a mask, a mesa is etched around ring 26 terminating on n-doped layer 21. Preferably etching is by reactive ion etching in order to obtain a mesa with vertical side walls around the periphery of ring 26.

Next ohmic contact 27 is made with the now exposed n-doped layer 21 as by depositing a layer of gold-germanium alloy and photolithographically defining annular contact ring 27 around the mesa. For further isolation, a mesa concentric with ring 27 can be chemically etched through layer 21.

The final steps involve depositing passivating insulating layers 28 and forming metal interconnects 29 to contacts 26 and 27 in accordance with techniques well known in the art. The interconnects can advantageously extend to integrated electronic circuitry (not shown) formed on the silicon substrate.

In operation, a DC bias voltage applied between contacts 26 and 27 induces emission of light through the center of ring 26.

A particular advantage of this embodiment is that the composition of the Gex Sil-x layer can be chosen to lattice match a variety of indium gallium phosphide compounds giving a wide choice of emission wavelengths. For example, when the indium gallium phosphide compound matches a Ge--Si buffer with 65-70% Ge, the emission is green whereas a compound lattice matched to 100% Ge emits red. Thus much of the visible range can be covered.

FIG. 4 is a schematic cross section of a GaAs surface emitting LED fabricated on a heterolayer in accordance with the invention. In particular, the LED 30 is fabricated on a heterostructure comprising a Gex Sil-x layer 12 grown within a large area tube 11 on a silicon substrate 10. In addition the LED is shown connected via a metal lead 36 to a drive transistor 40 integrally formed in silicon substrate 10.

The Gex Sil-x layer is formed in tube 11 as described in Example 1 above. The Gex Sil-x is preferably undoped and achieves a final composition consisting essentially of pure germanium in order to lattice match the materials of LED 30.

LED 30 comprises a layer of n-doped Aly Gal-y As 31 grown on the Ge surface, as by MBE, a layer of p-doped GaAs 32 grown on layer 31 and a layer 33 of p+ doped Aly Gal-y As grown on layer 32. The LED has an annular p-type ohmic contact 34 to layer 33 and an n-type ohmic contact 35 to layer 31.

In a specific structure, n-layer 31 can be doped with silicon to a concentration of 1018 /cm3 and have a thickness of 0.5 micrometer, p-layer 32 can be doped with Be to a concentration of 1016 /cm3 and have a thickness of 0.6 micrometer. P+ layer 32 can be doped with Be to 1019 /cm3 and have a thickness of 0.5 micrometers. The n-contact 35 can be a composite layer of nickel, titanium and gold, and the p-contact 34 can be AuBe alloy. The LED 30 can be connected to transistor 40 with aluminum interconnects 36.

Drive transistor 40 consists essentially of an n-type emitter 41, a p-type base 42 and an n-type collector 43 integrally fabricated on silicon substrate 10 in accordance with conventional techniques well known in the art.

This example illustrates the important advantage that the invention permits silicon electronic components (e.g. transistor 40) and III-V semiconductor optical components (e.g. LED 30) to be fabricated on the same substrate. Clearly, much more complex circuits can be fabricated on the structure.

It is to be understood that the above-described embodiments are illustrative of only a few of the many possible specific embodiments which can represent applications of the principles of the invention. Numerous and varied other arrangements can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims (10)

We claim:
1. A method for making a semiconductor device comprising the steps of:
providing a monocrystalline silicon substrate;
epitaxially growing on said silicon substrate at a temperature in excess of 850° C. a graded layer of Gex Sil-x with increasing germanium content at a gradient of less than about 25% per micrometer to a final composition in the range 0.1≦x≦1.0; and
epitaxially growing a layer of semiconductor material above said graded layer of Gex Sil-x.
2. The method of claim 1 wherein said layer of semiconductor material comprises a cap layer of Ge--Si alloy having the same composition as the surface of the graded layer and a thickness in excess of 100 angstroms.
3. The method of claim 1 wherein said graded layer of Gex Sil-x has a final composition in the range 0.1≦x≦0.5 and said layer of semiconductor material comprises silicon.
4. The method of claim 1 wherein said graded layer of Gex Sil-x has a final composition in the range (0.65≦x≦1.0) and said layer of semiconductor material comprises indium gallium phosphide.
5. The method of claim 1 wherein said graded layer of Gex Sil-x has a final composition of pure germanium and said layer of semiconductor material comprises gallium arsenide or aluminum gallium arsenide.
6. The method of claim 1 wherein said epitaxial layers are grown by molecular beam epitaxy.
7. The method of claim 1 wherein said epitaxial layers are grown by chemical vapor deposition.
8. The method of claim 1 further comprising the step of providing said silicon substrate with a recessed to tub having a depth equal to the sum of the thickness of the graded layer of Gex Sil-x and the cap layer.
9. The method of claim 1 wherein the temperature of growth of said graded layer of Gex Sil-x is scaled in proportion to the melting temperature of the Gex Sil-x.
10. The method of claim 1 wherein the area of said graded Gex Sil-x layer exceeds 12,000 square microns.
US07690429 1991-04-24 1991-04-24 Method for making low defect density semiconductor heterostructure and devices made thereby Expired - Lifetime US5221413A (en)

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Cited By (80)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5273930A (en) * 1992-09-03 1993-12-28 Motorola, Inc. Method of forming a non-selective silicon-germanium epitaxial film
US5810924A (en) * 1991-05-31 1998-09-22 International Business Machines Corporation Low defect density/arbitrary lattice constant heteroepitaxial layers
US6039803A (en) * 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
US6154475A (en) * 1997-12-04 2000-11-28 The United States Of America As Represented By The Secretary Of The Air Force Silicon-based strain-symmetrized GE-SI quantum lasers
US6350993B1 (en) 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US20020084000A1 (en) * 1997-06-24 2002-07-04 Eugene A. Fitzgerald Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US6503773B2 (en) 2000-01-20 2003-01-07 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
US6515335B1 (en) * 2002-01-04 2003-02-04 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
US20030034529A1 (en) * 2000-12-04 2003-02-20 Amberwave Systems Corporation CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6525338B2 (en) 2000-08-01 2003-02-25 Mitsubishi Materials Corporation Semiconductor substrate, field effect transistor, method of forming SiGe layer and method of forming strained Si layer using same, and method of manufacturing field effect transistor
US20030077867A1 (en) * 2001-03-02 2003-04-24 Fitzergald Eugene A. Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6573126B2 (en) 2000-08-16 2003-06-03 Massachusetts Institute Of Technology Process for producing semiconductor article using graded epitaxial growth
US20030102498A1 (en) * 2001-09-24 2003-06-05 Glyn Braithwaite RF circuits including transistors having strained material layers
US6589335B2 (en) * 2001-02-08 2003-07-08 Amberwave Systems Corporation Relaxed InxGa1-xAs layers integrated with Si
US6602613B1 (en) 2000-01-20 2003-08-05 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US6645829B2 (en) * 2000-08-04 2003-11-11 Amberwave Systems Corporation Silicon wafer with embedded optoelectronic material for monolithic OEIC
US6649480B2 (en) 2000-12-04 2003-11-18 Amberwave Systems Corporation Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US20030215990A1 (en) * 2002-03-14 2003-11-20 Eugene Fitzgerald Methods for fabricating strained layers on semiconductor substrates
US20040000268A1 (en) * 1998-04-10 2004-01-01 Massachusetts Institute Of Technology Etch stop layer system
US20040007715A1 (en) * 2002-07-09 2004-01-15 Webb Douglas A. Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys
US20040040493A1 (en) * 2002-08-30 2004-03-04 Amberwave Systems Corporation Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy
WO2004019391A2 (en) 2002-08-23 2004-03-04 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US20040065943A1 (en) * 2002-10-02 2004-04-08 Steven Kirchoefer Semiconductor varactor diode with doped heterojunction
US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6723622B2 (en) 2002-02-21 2004-04-20 Intel Corporation Method of forming a germanium film on a semiconductor substrate that includes the formation of a graded silicon-germanium buffer layer prior to the formation of a germanium layer
WO2004049411A1 (en) 2002-11-28 2004-06-10 Sumitomo Mitsubishi Silicon Corporation Method for producing semiconductor substrate and method for fabricating field effect transistor and semiconductor substrate and field effect transistor
US6750130B1 (en) 2000-01-20 2004-06-15 Amberwave Systems Corporation Heterointegration of materials using deposition and bonding
US20040245552A1 (en) * 2001-08-23 2004-12-09 Ichiro Shiono Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor
US20040251458A1 (en) * 2001-08-06 2004-12-16 Kazuki Mizushima Semiconductor substrate, field-effect transistor, and their manufacturing methods
US6838728B2 (en) 2001-08-09 2005-01-04 Amberwave Systems Corporation Buried-channel devices and substrates for fabrication of semiconductor-based devices
US20050051795A1 (en) * 2003-07-30 2005-03-10 Chantal Arena Epitaxial growth of relaxed silicon germanium layers
US20050054168A1 (en) * 2001-09-21 2005-03-10 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US6897129B2 (en) 2002-05-31 2005-05-24 Renesas Technology Corp. Fabrication method of semiconductor device and semiconductor device
US20050132952A1 (en) * 2003-12-17 2005-06-23 Michael Ward Semiconductor alloy with low surface roughness, and method of making the same
US20050179028A1 (en) * 2004-02-17 2005-08-18 Pang-Shiu Chen Construction of thin strain-relaxed SiGe layers and method for fabricating the same
US6940089B2 (en) 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US20050208780A1 (en) * 2003-05-30 2005-09-22 International Business Machines Corporation High-quality SGOI by oxidation near the alloy melting temperature
US20050205954A1 (en) * 2002-12-18 2005-09-22 King Clifford A Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US20060011983A1 (en) * 2000-05-26 2006-01-19 Amberwave Systems Corporation Methods of fabricating strained-channel FET having a dopant supply region
US6995430B2 (en) 2002-06-07 2006-02-07 Amberwave Systems Corporation Strained-semiconductor-on-insulator device structures
US20060057856A1 (en) * 2004-09-09 2006-03-16 Toshiba Ceramics Co., Ltd. Manufacturing method for strained silicon wafer
US20060113542A1 (en) * 2004-11-30 2006-06-01 Massachusetts Institute Of Technology Method for forming low defect density alloy graded layers and structure containing such layers
US20060124961A1 (en) * 2003-12-26 2006-06-15 Canon Kabushiki Kaisha Semiconductor substrate, manufacturing method thereof, and semiconductor device
US20060132001A1 (en) * 2002-12-23 2006-06-22 Bertram Sugg Piezoelectric Actuator and a method for its manufacture
US7074623B2 (en) 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US20060185581A1 (en) * 2005-02-24 2006-08-24 Shin-Etsu Handotai Co., Ltd. Method for producing a semiconductor wafer
US20060225642A1 (en) * 2003-03-31 2006-10-12 Yoshihiko Kanzawa Method of forming semiconductor crystal
US7122449B2 (en) 2002-06-10 2006-10-17 Amberwave Systems Corporation Methods of fabricating semiconductor structures having epitaxially grown source and drain elements
US20060258126A1 (en) * 2003-02-04 2006-11-16 Sumco Corporation Semiconductor substrate, field-effect transistor, and their production methods
US20060255331A1 (en) * 2003-08-29 2006-11-16 Industrial Technology Research Institute Strained silicon forming method with reduction of threading dislocation density
US20070105256A1 (en) * 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated light emitting devices
US7217603B2 (en) 2002-06-25 2007-05-15 Amberwave Systems Corporation Methods of forming reacted conductive gate electrodes
US7238973B2 (en) 2003-12-26 2007-07-03 Canon Kabushiki Kaisha Semiconductor member, manufacturing method thereof, and semiconductor device
US20070161196A1 (en) * 2002-10-30 2007-07-12 Amberware Systems Methods for preserving strained semiconductor substrate layers during CMOS processing
US20070224786A1 (en) * 2003-03-13 2007-09-27 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US20070231488A1 (en) * 2004-04-30 2007-10-04 Hans Von Kaenel Method for Producing Virtual Ge Substrates for III/V-Integration on Si(001)
US20070252223A1 (en) * 2005-12-05 2007-11-01 Massachusetts Institute Of Technology Insulated gate devices and method of making same
US7307273B2 (en) 2002-06-07 2007-12-11 Amberwave Systems Corporation Control of strain in device layers by selective relaxation
US7332417B2 (en) 2003-01-27 2008-02-19 Amberwave Systems Corporation Semiconductor structures with structural homogeneity
US7335545B2 (en) 2002-06-07 2008-02-26 Amberwave Systems Corporation Control of strain in device layers by prevention of relaxation
US20080149915A1 (en) * 2006-06-28 2008-06-26 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
US7393733B2 (en) 2004-12-01 2008-07-01 Amberwave Systems Corporation Methods of forming hybrid fin field-effect transistor structures
US7402504B2 (en) 2003-03-13 2008-07-22 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
EP2026383A2 (en) 2007-08-17 2009-02-18 CSEM Centre Suisse d'Electronique et de Microtechnique SA X-Ray Imaging Device and Method for the Manufacturing thereof
US7504704B2 (en) 2003-03-07 2009-03-17 Amberwave Systems Corporation Shallow trench isolation process
US7615829B2 (en) 2002-06-07 2009-11-10 Amberwave Systems Corporation Elevated source and drain elements for strained-channel heterojuntion field-effect transistors
US20100254425A1 (en) * 2007-06-29 2010-10-07 International Business Machines Corporation Phase change material based temperature sensor
US20110017127A1 (en) * 2007-08-17 2011-01-27 Epispeed Sa Apparatus and method for producing epitaxial layers
US20110227129A1 (en) * 2008-11-28 2011-09-22 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate
WO2011135432A1 (en) 2010-04-27 2011-11-03 Von Kaenel Hans Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication
EP2595175A2 (en) 2005-05-17 2013-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
US8748292B2 (en) 2002-06-07 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of forming strained-semiconductor-on-insulator device structures
US8822282B2 (en) 2001-03-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabricating contact regions for FET incorporating SiGe
WO2014140082A1 (en) 2013-03-13 2014-09-18 Pilegrowth Tech S.R.L. High efficiency solar cells on silicon substrates
US20150090180A1 (en) * 2013-09-27 2015-04-02 Ultratech, Inc. Epitaxial growth of compound semiconductors using lattice-tuned domain-matching epitaxy
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
US9431243B2 (en) 2005-05-17 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US9859381B2 (en) 2005-05-17 2018-01-02 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication

Families Citing this family (50)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE4438380C1 (en) * 1994-10-27 1996-01-25 Inst Halbleiterphysik Gmbh Depositing single crystalline mixed crystal layer of germanium silicide
EP1036412A1 (en) * 1997-09-16 2000-09-20 Massachusetts Institute Of Technology CO-PLANAR Si AND Ge COMPOSITE SUBSTRATE AND METHOD OF PRODUCING SAME
JP2003517726A (en) * 1999-09-20 2003-05-27 アンバーウェーブ システムズ コーポレイション A method for manufacturing a relaxed silicon germanium layer
US7041170B2 (en) * 1999-09-20 2006-05-09 Amberwave Systems Corporation Method of producing high quality relaxed silicon germanium layers
US6392257B1 (en) 2000-02-10 2002-05-21 Motorola Inc. Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same
US6693033B2 (en) 2000-02-10 2004-02-17 Motorola, Inc. Method of removing an amorphous oxide from a monocrystalline surface
US6501973B1 (en) 2000-06-30 2002-12-31 Motorola, Inc. Apparatus and method for measuring selected physical condition of an animate subject
US6427066B1 (en) 2000-06-30 2002-07-30 Motorola, Inc. Apparatus and method for effecting communications among a plurality of remote stations
US6410941B1 (en) 2000-06-30 2002-06-25 Motorola, Inc. Reconfigurable systems using hybrid integrated circuits with optical ports
US6477285B1 (en) 2000-06-30 2002-11-05 Motorola, Inc. Integrated circuits with optical signal propagation
US6555946B1 (en) 2000-07-24 2003-04-29 Motorola, Inc. Acoustic wave device and process for forming the same
EP2276059A1 (en) 2000-08-04 2011-01-19 The Regents of the University of California Method of controlling stress in gallium nitride films deposited on substrates
US6638838B1 (en) 2000-10-02 2003-10-28 Motorola, Inc. Semiconductor structure including a partially annealed layer and method of forming the same
US6583034B2 (en) 2000-11-22 2003-06-24 Motorola, Inc. Semiconductor structure including a compliant substrate having a graded monocrystalline layer and methods for fabricating the structure and semiconductor devices including the structure
US6563118B2 (en) 2000-12-08 2003-05-13 Motorola, Inc. Pyroelectric device on a monocrystalline semiconductor substrate and process for fabricating same
US6649287B2 (en) * 2000-12-14 2003-11-18 Nitronex Corporation Gallium nitride materials and methods
WO2002063665A3 (en) * 2001-02-08 2003-01-23 Amberwave Systems Corp RELAXED InXGa1-xAs LAYERS INTEGRATED WITH Si
US6594293B1 (en) 2001-02-08 2003-07-15 Amberwave Systems Corporation Relaxed InxGa1-xAs layers integrated with Si
US6673646B2 (en) 2001-02-28 2004-01-06 Motorola, Inc. Growth of compound semiconductor structures on patterned oxide films and process for fabricating same
US7046719B2 (en) 2001-03-08 2006-05-16 Motorola, Inc. Soft handoff between cellular systems employing different encoding rates
US6709989B2 (en) 2001-06-21 2004-03-23 Motorola, Inc. Method for fabricating a semiconductor structure including a metal oxide interface with silicon
US6646293B2 (en) 2001-07-18 2003-11-11 Motorola, Inc. Structure for fabricating high electron mobility transistors utilizing the formation of complaint substrates
US6693298B2 (en) 2001-07-20 2004-02-17 Motorola, Inc. Structure and method for fabricating epitaxial semiconductor on insulator (SOI) structures and devices utilizing the formation of a compliant substrate for materials used to form same
US6472694B1 (en) 2001-07-23 2002-10-29 Motorola, Inc. Microprocessor structure having a compound semiconductor layer
US6667196B2 (en) 2001-07-25 2003-12-23 Motorola, Inc. Method for real-time monitoring and controlling perovskite oxide film growth and semiconductor structure formed using the method
US6594414B2 (en) 2001-07-25 2003-07-15 Motorola, Inc. Structure and method of fabrication for an optical switch
US6585424B2 (en) 2001-07-25 2003-07-01 Motorola, Inc. Structure and method for fabricating an electro-rheological lens
US6589856B2 (en) 2001-08-06 2003-07-08 Motorola, Inc. Method and apparatus for controlling anti-phase domains in semiconductor structures and devices
US6462360B1 (en) 2001-08-06 2002-10-08 Motorola, Inc. Integrated gallium arsenide communications systems
US6639249B2 (en) 2001-08-06 2003-10-28 Motorola, Inc. Structure and method for fabrication for a solid-state lighting device
US6673667B2 (en) 2001-08-15 2004-01-06 Motorola, Inc. Method for manufacturing a substantially integral monolithic apparatus including a plurality of semiconductor materials
DE10163394A1 (en) * 2001-12-21 2003-07-03 Aixtron Ag Method and device for depositing crystalline layers on crystalline substrates and
FR2836159B1 (en) * 2002-02-15 2004-05-07 Centre Nat Rech Scient Process for the carbure de silicium layer forming or element III nitride on a substrate adapts
GB0212616D0 (en) 2002-05-31 2002-07-10 Univ Warwick Formation of lattice-tuning semiconductor substrates
FR2842217A1 (en) * 2002-07-12 2004-01-16 St Microelectronics Sa Growing a single crystal region of a III-V compound on a monocrystalline silicon substrate
JP4557505B2 (en) * 2003-05-19 2010-10-06 コバレントマテリアル株式会社 A method of manufacturing a semiconductor substrate
KR100679737B1 (en) 2003-05-19 2007-02-07 도시바세라믹스가부시키가이샤 A method for manufacturing a silicon substrate having a distorted layer
US7247583B2 (en) 2004-01-30 2007-07-24 Toshiba Ceramics Co., Ltd. Manufacturing method for strained silicon wafer
JP2005244187A (en) * 2004-01-30 2005-09-08 Toshiba Ceramics Co Ltd Strained silicon wafer and manufacturing method thereof
GB2411047B (en) * 2004-02-13 2008-01-02 Iqe Silicon Compounds Ltd Compound semiconductor device and method of producing the same
US7229866B2 (en) 2004-03-15 2007-06-12 Velox Semiconductor Corporation Non-activated guard ring for semiconductor devices
US7417266B1 (en) 2004-06-10 2008-08-26 Qspeed Semiconductor Inc. MOSFET having a JFET embedded as a body diode
US7436039B2 (en) 2005-01-06 2008-10-14 Velox Semiconductor Corporation Gallium nitride semiconductor device
US8026568B2 (en) 2005-11-15 2011-09-27 Velox Semiconductor Corporation Second Schottky contact metal layer to improve GaN Schottky diode performance
US7939853B2 (en) 2007-03-20 2011-05-10 Power Integrations, Inc. Termination and contact structures for a high voltage GaN-based heterojunction transistor
US9362114B2 (en) 2008-12-15 2016-06-07 Sumco Corporation Epitaxial wafer and method of manufacturing the same
US8633094B2 (en) 2011-12-01 2014-01-21 Power Integrations, Inc. GaN high voltage HFET with passivation plus gate dielectric multilayer structure
US8940620B2 (en) 2011-12-15 2015-01-27 Power Integrations, Inc. Composite wafer for fabrication of semiconductor devices
US9177992B2 (en) 2013-01-09 2015-11-03 Nthdegree Technologies Worldwide Inc. Active LED module with LED and transistor formed on same substrate
US8928037B2 (en) 2013-02-28 2015-01-06 Power Integrations, Inc. Heterostructure power transistor with AlSiN passivation layer

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3615855A (en) * 1969-04-03 1971-10-26 Gen Motors Corp Radiant energy photovoltalic device
US3935040A (en) * 1971-10-20 1976-01-27 Harris Corporation Process for forming monolithic semiconductor display
US4357183A (en) * 1980-08-13 1982-11-02 Massachusetts Institute Of Technology Heteroepitaxy of germanium silicon on silicon utilizing alloying control
US4529455A (en) * 1983-10-28 1985-07-16 At&T Bell Laboratories Method for epitaxially growing Gex Si1-x layers on Si utilizing molecular beam epitaxy
US4711857A (en) * 1986-08-28 1987-12-08 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Tailorable infrared sensing device with strain layer superlattice structure
US4857270A (en) * 1987-05-19 1989-08-15 Komatsu Electronic Metals Co., Ltd. Process for manufacturing silicon-germanium alloys
US4876210A (en) * 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6232608B2 (en) * 1980-09-18 1987-07-15 Oki Electric Ind Co Ltd
JPS6164118A (en) * 1984-09-05 1986-04-02 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
DE3542482A1 (en) * 1985-11-30 1987-06-04 Licentia Gmbh Modulation doped field effect transistor
DE3830102A1 (en) * 1987-09-16 1989-03-30 Licentia Gmbh Si / SiGe halbleiterkoerper

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3615855A (en) * 1969-04-03 1971-10-26 Gen Motors Corp Radiant energy photovoltalic device
US3935040A (en) * 1971-10-20 1976-01-27 Harris Corporation Process for forming monolithic semiconductor display
US4357183A (en) * 1980-08-13 1982-11-02 Massachusetts Institute Of Technology Heteroepitaxy of germanium silicon on silicon utilizing alloying control
US4529455A (en) * 1983-10-28 1985-07-16 At&T Bell Laboratories Method for epitaxially growing Gex Si1-x layers on Si utilizing molecular beam epitaxy
US4711857A (en) * 1986-08-28 1987-12-08 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Tailorable infrared sensing device with strain layer superlattice structure
US4876210A (en) * 1987-04-30 1989-10-24 The University Of Delaware Solution growth of lattice mismatched and solubility mismatched heterostructures
US4857270A (en) * 1987-05-19 1989-08-15 Komatsu Electronic Metals Co., Ltd. Process for manufacturing silicon-germanium alloys

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
J. M. Baribeau, et al "Growth and characterization of Si1-x Gex and Ge epilayers on (100) Si", Journal of Applied Physics, vol. 63, pp. 5738-5746, (1988).
J. M. Baribeau, et al Growth and characterization of Si 1 x Ge x and Ge epilayers on (100) Si , Journal of Applied Physics, vol. 63, pp. 5738 5746, (1988). *
Kasper et al., "Acme Dimensional SiGe Superlattice Grown by UHV Epitaxy", Applied Physics 8,199, 1975 pp. 199-205.
Kasper et al., Acme Dimensional SiGe Superlattice Grown by UHV Epitaxy , Applied Physics 8,199, 1975 pp. 199 205. *

Cited By (181)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5810924A (en) * 1991-05-31 1998-09-22 International Business Machines Corporation Low defect density/arbitrary lattice constant heteroepitaxial layers
US5273930A (en) * 1992-09-03 1993-12-28 Motorola, Inc. Method of forming a non-selective silicon-germanium epitaxial film
US6039803A (en) * 1996-06-28 2000-03-21 Massachusetts Institute Of Technology Utilization of miscut substrates to improve relaxed graded silicon-germanium and germanium layers on silicon
US7081410B2 (en) 1997-06-24 2006-07-25 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US6876010B1 (en) 1997-06-24 2005-04-05 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US20020084000A1 (en) * 1997-06-24 2002-07-04 Eugene A. Fitzgerald Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US20040262631A1 (en) * 1997-06-24 2004-12-30 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US7250359B2 (en) 1997-06-24 2007-07-31 Massachusetts Institute Of Technology Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization
US6154475A (en) * 1997-12-04 2000-11-28 The United States Of America As Represented By The Secretary Of The Air Force Silicon-based strain-symmetrized GE-SI quantum lasers
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US20040000268A1 (en) * 1998-04-10 2004-01-01 Massachusetts Institute Of Technology Etch stop layer system
US6350993B1 (en) 1999-03-12 2002-02-26 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6858502B2 (en) 1999-03-12 2005-02-22 International Business Machines Corporation High speed composite p-channel Si/SiGe heterostructure for field effect devices
US6864115B2 (en) 2000-01-20 2005-03-08 Amberwave Systems Corporation Low threading dislocation density relaxed mismatched epilayers without high temperature growth
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US20060011983A1 (en) * 2000-05-26 2006-01-19 Amberwave Systems Corporation Methods of fabricating strained-channel FET having a dopant supply region
US6525338B2 (en) 2000-08-01 2003-02-25 Mitsubishi Materials Corporation Semiconductor substrate, field effect transistor, method of forming SiGe layer and method of forming strained Si layer using same, and method of manufacturing field effect transistor
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US6724008B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US8822282B2 (en) 2001-03-02 2014-09-02 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of fabricating contact regions for FET incorporating SiGe
US6723661B2 (en) 2001-03-02 2004-04-20 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US20030077867A1 (en) * 2001-03-02 2003-04-24 Fitzergald Eugene A. Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US6703688B1 (en) 2001-03-02 2004-03-09 Amberwave Systems Corporation Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits
US7501351B2 (en) 2001-03-02 2009-03-10 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US7256142B2 (en) 2001-03-02 2007-08-14 Amberwave Systems Corporation Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits
US6940089B2 (en) 2001-04-04 2005-09-06 Massachusetts Institute Of Technology Semiconductor device structure
US20040251458A1 (en) * 2001-08-06 2004-12-16 Kazuki Mizushima Semiconductor substrate, field-effect transistor, and their manufacturing methods
US7138650B2 (en) 2001-08-06 2006-11-21 Sumitomo Mitsubishi Silicon Corporation Semiconductor substrate, field-effect transistor, and their manufacturing method of the same
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US7056789B2 (en) 2001-08-23 2006-06-06 Sumitomo Mitsubishi Silicon Corporation Production method for semiconductor substrate and production method for field effect transistor and semiconductor substrate and field effect transistor
US7776697B2 (en) 2001-09-21 2010-08-17 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US20050054168A1 (en) * 2001-09-21 2005-03-10 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US7884353B2 (en) 2001-09-21 2011-02-08 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US20070293003A1 (en) * 2001-09-21 2007-12-20 Matthew Currie Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US7846802B2 (en) 2001-09-21 2010-12-07 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US7709828B2 (en) 2001-09-24 2010-05-04 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
US20030102498A1 (en) * 2001-09-24 2003-06-05 Glyn Braithwaite RF circuits including transistors having strained material layers
US6933518B2 (en) 2001-09-24 2005-08-23 Amberwave Systems Corporation RF circuits including transistors having strained material layers
US7906776B2 (en) 2001-09-24 2011-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. RF circuits including transistors having strained material layers
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US20030127646A1 (en) * 2002-01-04 2003-07-10 International Business Machines Corporation Method for fabrication of relaxed SiGe buffer layers on silicon-on-insulators and structures containing the same
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US7838392B2 (en) 2002-06-07 2010-11-23 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for forming III-V semiconductor device structures
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US20040007715A1 (en) * 2002-07-09 2004-01-15 Webb Douglas A. Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys
US6936869B2 (en) 2002-07-09 2005-08-30 International Rectifier Corporation Heterojunction field effect transistors using silicon-germanium and silicon-carbon alloys
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EP2267762A2 (en) 2002-08-23 2010-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor heterostructures having reduced dislocation pile-ups and related methods
WO2004019391A2 (en) 2002-08-23 2004-03-04 Amberwave Systems Corporation Semiconductor heterostructures having reduced dislocation pile-ups and related methods
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US20040065943A1 (en) * 2002-10-02 2004-04-08 Steven Kirchoefer Semiconductor varactor diode with doped heterojunction
US7416909B2 (en) 2002-10-30 2008-08-26 Amberwave Systems Corporation Methods for preserving strained semiconductor substrate layers during CMOS processing
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WO2004049411A1 (en) 2002-11-28 2004-06-10 Sumitomo Mitsubishi Silicon Corporation Method for producing semiconductor substrate and method for fabricating field effect transistor and semiconductor substrate and field effect transistor
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US20090072284A1 (en) * 2002-12-18 2009-03-19 Noble Peak Vision Corp. Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US8664739B2 (en) 2002-12-18 2014-03-04 Infrared Newco, Inc. Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US20050205954A1 (en) * 2002-12-18 2005-09-22 King Clifford A Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US9142585B2 (en) 2002-12-18 2015-09-22 Infrared Newco, Inc. Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US7973377B2 (en) 2002-12-18 2011-07-05 Infrared Newco, Inc. Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US7453129B2 (en) 2002-12-18 2008-11-18 Noble Peak Vision Corp. Image sensor comprising isolated germanium photodetectors integrated with a silicon substrate and silicon circuitry
US20060132001A1 (en) * 2002-12-23 2006-06-22 Bertram Sugg Piezoelectric Actuator and a method for its manufacture
US7332417B2 (en) 2003-01-27 2008-02-19 Amberwave Systems Corporation Semiconductor structures with structural homogeneity
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US7402504B2 (en) 2003-03-13 2008-07-22 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US20070224786A1 (en) * 2003-03-13 2007-09-27 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US8530340B2 (en) 2003-03-13 2013-09-10 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US7682947B2 (en) 2003-03-13 2010-03-23 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US20100006024A1 (en) * 2003-03-13 2010-01-14 Asm America, Inc. Epitaxial semiconductor deposition methods and structures
US20060225642A1 (en) * 2003-03-31 2006-10-12 Yoshihiko Kanzawa Method of forming semiconductor crystal
US20050208780A1 (en) * 2003-05-30 2005-09-22 International Business Machines Corporation High-quality SGOI by oxidation near the alloy melting temperature
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US7514372B2 (en) * 2003-07-30 2009-04-07 Asm America, Inc. Epitaxial growth of relaxed silicon germanium layers
US20090189185A1 (en) * 2003-07-30 2009-07-30 Asm America, Inc. Epitaxial growth of relaxed silicon germanium layers
US7666799B2 (en) 2003-07-30 2010-02-23 Asm America, Inc. Epitaxial growth of relaxed silicon germanium layers
US20050051795A1 (en) * 2003-07-30 2005-03-10 Chantal Arena Epitaxial growth of relaxed silicon germanium layers
US7498224B2 (en) 2003-08-29 2009-03-03 Industrial Technology Research Institute Strained silicon forming method with reduction of threading dislocation density
US20060255331A1 (en) * 2003-08-29 2006-11-16 Industrial Technology Research Institute Strained silicon forming method with reduction of threading dislocation density
US20050132952A1 (en) * 2003-12-17 2005-06-23 Michael Ward Semiconductor alloy with low surface roughness, and method of making the same
US20070272944A1 (en) * 2003-12-26 2007-11-29 Canon Kabushiki Kaisha Semiconductor member, manufacturing method thereof, and semiconductor device
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US20060124961A1 (en) * 2003-12-26 2006-06-15 Canon Kabushiki Kaisha Semiconductor substrate, manufacturing method thereof, and semiconductor device
US20050179028A1 (en) * 2004-02-17 2005-08-18 Pang-Shiu Chen Construction of thin strain-relaxed SiGe layers and method for fabricating the same
US7202512B2 (en) 2004-02-17 2007-04-10 Industrial Technology Research Institute Construction of thin strain-relaxed SiGe layers and method for fabricating the same
US20070231488A1 (en) * 2004-04-30 2007-10-04 Hans Von Kaenel Method for Producing Virtual Ge Substrates for III/V-Integration on Si(001)
US8882909B2 (en) 2004-04-30 2014-11-11 Dichroic Cell S.R.L. Method for producing virtual Ge substrates for III/V-integration on Si(001)
US7250357B2 (en) 2004-09-09 2007-07-31 Toshiba Ceramics Co., Ltd. Manufacturing method for strained silicon wafer
US20060057856A1 (en) * 2004-09-09 2006-03-16 Toshiba Ceramics Co., Ltd. Manufacturing method for strained silicon wafer
US20060113542A1 (en) * 2004-11-30 2006-06-01 Massachusetts Institute Of Technology Method for forming low defect density alloy graded layers and structure containing such layers
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US8183627B2 (en) 2004-12-01 2012-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Hybrid fin field-effect transistor structures and related methods
US20060185581A1 (en) * 2005-02-24 2006-08-24 Shin-Etsu Handotai Co., Ltd. Method for producing a semiconductor wafer
EP2595177A3 (en) * 2005-05-17 2013-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
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EP2595176A3 (en) * 2005-05-17 2013-07-17 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
EP2595177A2 (en) 2005-05-17 2013-05-22 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities related methods for device fabrication
US9431243B2 (en) 2005-05-17 2016-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lattice-mismatched semiconductor structures with reduced dislocation defect densities and related methods for device fabrication
US8120060B2 (en) 2005-11-01 2012-02-21 Massachusetts Institute Of Technology Monolithically integrated silicon and III-V electronics
US20070105274A1 (en) * 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated semiconductor materials and devices
US8012592B2 (en) 2005-11-01 2011-09-06 Massachuesetts Institute Of Technology Monolithically integrated semiconductor materials and devices
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US20070105335A1 (en) * 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated silicon and III-V electronics
US7535089B2 (en) 2005-11-01 2009-05-19 Massachusetts Institute Of Technology Monolithically integrated light emitting devices
US20090242935A1 (en) * 2005-11-01 2009-10-01 Massachusetts Institute Of Technology Monolithically integrated photodetectors
US20070105256A1 (en) * 2005-11-01 2007-05-10 Massachusetts Institute Of Technology Monolithically integrated light emitting devices
US20070252223A1 (en) * 2005-12-05 2007-11-01 Massachusetts Institute Of Technology Insulated gate devices and method of making same
US20080149915A1 (en) * 2006-06-28 2008-06-26 Massachusetts Institute Of Technology Semiconductor light-emitting structure and graded-composition substrate providing yellow-green light emission
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US20100254425A1 (en) * 2007-06-29 2010-10-07 International Business Machines Corporation Phase change material based temperature sensor
US20110017127A1 (en) * 2007-08-17 2011-01-27 Epispeed Sa Apparatus and method for producing epitaxial layers
EP2026383A2 (en) 2007-08-17 2009-02-18 CSEM Centre Suisse d'Electronique et de Microtechnique SA X-Ray Imaging Device and Method for the Manufacturing thereof
US20090045346A1 (en) * 2007-08-17 2009-02-19 Hans Von Kanel X-ray imaging device and method for the manufacturing thereof
US8237126B2 (en) 2007-08-17 2012-08-07 Csem Centre Suisse D'electronique Et De Mictrotechnique Sa X-ray imaging device and method for the manufacturing thereof
US20110227129A1 (en) * 2008-11-28 2011-09-22 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate
US8729677B2 (en) 2008-11-28 2014-05-20 Sumitomo Chemical Company, Limited Semiconductor substrate, electronic device and method for manufacturing semiconductor substrate
WO2011135432A1 (en) 2010-04-27 2011-11-03 Von Kaenel Hans Dislocation and stress management by mask-less processes using substrate patterning and methods for device fabrication
US9127345B2 (en) 2012-03-06 2015-09-08 Asm America, Inc. Methods for depositing an epitaxial silicon germanium layer having a germanium to silicon ratio greater than 1:1 using silylgermane and a diluent
WO2014140082A1 (en) 2013-03-13 2014-09-18 Pilegrowth Tech S.R.L. High efficiency solar cells on silicon substrates
US20150090180A1 (en) * 2013-09-27 2015-04-02 Ultratech, Inc. Epitaxial growth of compound semiconductors using lattice-tuned domain-matching epitaxy
US9218963B2 (en) 2013-12-19 2015-12-22 Asm Ip Holding B.V. Cyclical deposition of germanium
US9929009B2 (en) 2013-12-19 2018-03-27 Asm Ip Holding B.V. Cyclical deposition of germanium
US9576794B2 (en) 2013-12-19 2017-02-21 Asm Ip Holding B.V. Cyclical deposition of germanium

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