US5008676A - Digital/analog converter - Google Patents

Digital/analog converter Download PDF

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US5008676A
US5008676A US07551994 US55199490A US5008676A US 5008676 A US5008676 A US 5008676A US 07551994 US07551994 US 07551994 US 55199490 A US55199490 A US 55199490A US 5008676 A US5008676 A US 5008676A
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digital
analog
changeover
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circuit
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Kenji Kanoh
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Mitsubishi Electric Corp
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Mitsubishi Electric Corp
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/68Digital/analogue converters with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
    • H03M1/687Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/78Simultaneous conversion using ladder network
    • H03M1/785Simultaneous conversion using ladder network using resistors, i.e. R-2R ladders
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03MCODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66Digital/analogue converters
    • H03M1/74Simultaneous conversion
    • H03M1/80Simultaneous conversion using weighted impedances
    • H03M1/808Simultaneous conversion using weighted impedances using resistors

Abstract

The present invention is a digital/analog converter which converts a digital signal of a binary number consisting of NL low-order bits and NU high-order bits into an analog signal, in which a first digital/analog converting circit driven in accordance with a digital data of low-order bits employs, as conventional, an R-2R system while a second digital/analog converting circuit driven in accordance with a digital data of high-order bits employs a 2R system. As a result, the influence of an error included in the variation in an output of the analog signal which is caused by the variation in the digital data for the least significant bit can be decreased, whereby a high resolution is obtained, keeping a monotonicity, without a high matching of registors.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a digital/analog converter converting a digital signal of a binary number into an analog signal.

2. Prior Art

As an applied-voltage digital/analog converter, that which employs an R-2R system is conventionally known. FIG. 11 shows an 8- bit digital/analog converter employing such an R-2R system.

As shown in FIG. 11, the digital/analog converter is provided with eight changeover switches S0 to S7 corresponding to a bit in each order of an 8-bit digital signal to be D/A-converted. One of contact points of each of the changeover switches S0 to S7 is connected with a first input terminal 1 to which reference voltage VREF is applied, while the other is connected to a second input terminal 2 to which ground potential GND is applied. Between the second input terminal 2 and an output terminal 3, a single resistor which has a resistance value 2R and seven resistors each of which has a resistance value R are connected in series. Between respective nodes between the above-mentioned resistors and respective common contact points of the changeover switches S0 to S7, eight resistors each of which has a resistance value 2R are connected, respectively.

With the digital/analog converter, the changeover switches S0 to S7 change their respective connections between the respective first contact points to which the reference voltage VREF is applied and the respective second contact points to which the ground potential GND is applied depending upon a state of a corresponding bit of a digital signal, and an analog signal having a voltage value corresponding to the digital signal is outputted from the output terminal 3.

In this way, the digital/analog converter employing the conventional R-2R system do not have to have a large number of elements such as the resistors, the changeover switches S0 to S7 and so on, and thus this type of digital/analog converter has the advantage that it can be controlled in a simple way. However, it also has the disadvantage as mentioned below: Practically, the resistors have slightly different resistance values from their desirable resistance values R or 2R, and an error arises in a variation in an output of the analog signal corresponding to a variation in a digital data. With the conventional digital/analog converter, an error included in the variation in an output of an analog signal which is caused by the variation in the digital data for the least significant bit exerts a large influence on the performance of the digital/analog converter, and therefore, it is necessary to accomplish a very high matching of resistors to obtain a converter which has a high resolution, keeping a monotonicity that the analog value of the analog signal monotonously increase or decrease in accordance with the monotonous change of the digital value of the digital signal.

SUMMARY OF THE INVENTION

The present invention is a digital/analog converter which converts a digital signal of a binary number consisting of the NL low-order bits and the NU high-order bits into an analog signal, comprising a first input terminal to which first reference potential is applied, a second input terminal to which second reference potential is applied, an output terminal, a first digital/analog converting circuit driven in accordance with a digital data of the low-order bits and a second digital/analog converting circuit driven in accordance with a digital data of the high-order bits.

The first digital/analog converting circuit consists of a first resistor, R-2R circuitry and a first switch group. Specifically, the first resistor has a resistance value 2R and has its one end connected to the second input terminal. The R-2R circuitry has NL second resistors of resistance value R connected in series and NL third resistors of resistance value 2R having their respective one ends connected to one ends of the second resistors. A junction of the one end of the second resistor and the one end of the third resistor disposed on one side is connected to the other end of the first resistor, while the other end of the second resistor disposed on the other side is connected to the output terminal. The first switch group consists of NL first changeover switches each of which has first and second changeover contact points and a common contact point. Each of the first changeover switches has its first changeover contact point connected to the first input terminal, its second changeover contact point connected to the second input terminal and its common contact point connected to the other end of the corresponding third resistor, respectively, and each of the first changeover switches change the connection between the first and second changeover contact points in accordance with a state of each bit of the low-order bits.

On the other hand, the second digital/analog converting circuit consists of 2R circuitry and a second switch group. The 2R circuitry consists of (2N -1) fourth resistors each of which has a resistance value of 2R and which have their respective one ends commonly connected, and one end of each of the fourth resistors is connected to the output terminal. The second switch group consists of (2N -1) second changeover switches each of which has first and second changeover contact point and a common contact point. Each of the second changeover switches has its respective first changeover contact point connected to the first input terminal, the second changeover contact point connected to the second input terminal and the common contact point connected to the other end of each of the fourth corresponding resistor, respectively, and the number of the second changeover switches changing their respective connections to the first changeover contact points is determined in accordance with a state of the high-order bits.

Accordingly, it is a major object of the present invention to provide a digital/analog converter which has a high resolution, keeping a monotonicity, without high matching of resistors.

With the digital/analog converter according to the present invention, the first digital/analog converting circuit driven in accordance with the digital data of the low-order bits is formed employing the R-2R system as usual, while the second digital/analog converting circuit driven in accordance with the digital data of the high-order bits is formed employing the 2R system, whereby the influence of an error included in the variation in an output of an analog signal which is caused by the variation in the digital data for the least significant bit can be decreased. Thus, a high resolution can be attained keeping a monotonicity, without a high matching of registors.

These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing an embodiment of an 8 bit digital/analog converter according to the present invention;

FIG. 2 is an equivalent circuit diagram to FIG. 1;

FIG. 3 is a circuit diagram showing a state in which resistances vary widely in a conventional circuit;

FIG. 4 is a circuit diagram showing a state in which the circuit of FIG. 1 has resistances varied widely;

FIGS. 5 to 8 are circuit diagrams for calculating amounts of a variation in output voltage, respectively;

FIG. 9 is a diagram showing an equivalent circuit diagram of a digital/analog converter represented through generalization;

FIG. 10 is a circuit diagram showing another embodiment of a 9 bit digital/analog converter according to the present invention; and

FIG. 11 is a circuit diagram showing a conventional 8 bit digital/analog converter.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

FIG. 1 is an embodiment of an 8 bit digital/analog converter according to the present invention.

The digital/analog converter converts a digital signal of a binary number of 6 low-order bits and 2 high-order bits into an analog signal, and is provided with a first digital/analog converting circuit 4 driven in accordance with a digital data of the 6 low-order bits and a second digital/analog converting circuit 5 driven in accordance with a digital data of the 2 high-order bits.

The first digital/analog converting circuit 4 is provided with six changeover switches S0 to S5 changing their respective connections in accordance with a state of the digital data of the 6 low-order bits. One of changeover contact points of each of the changeover switches S0 to S5 is connected with a first input terminal 1 to which reference voltage VREF is applied, while the other thereof is connected to a second input terminal 2 to which ground potential GND is applied. A single resistance R1 having a resistance value 2R and six resistances R2 to R7 each of which has a resistance value R are connected in series between the second input terminal 2 and an output terminal 3. Furthermore, six resistances R8 to R13 each of which has a resistance value 2R are connected between one ends of the resistances R2 to R7 and the common contact points of the changeover switches S0 to S5. Thus, an R-2R circuit 6 is composed of the resistances R2 to R13, while a first switch group 7 is composed of the changeover switches S0 to S5.

On the other hand, the second digital/analog converting circuit 5 is provided with three changeover switches SM0, SM1, SM2 which change their respective connections in accordance with a state of the digital data of the 2 high-order bits. One of changeover contact points of each of the changeover switches SM0, SM1, SM2 is connected to the first input terminal 1 to which the reference voltage VREF is applied, while the other thereof is connected to the second input terminal GND to which the ground potential GND is applied. Furthermore, three resistances RM0, RM1, RM2 each of which has a resistance value 2R are connected between the common contact points of the changeover switches SM0, SM1, SM2 and the output terminal 3, respectively. Thus, a 2R circuit 8 is composed of the resistances RM0, RM1, RM2, while a second switch group 9 is composed of the changeover switches SM0, SM1, SM2.

The changeover switches S0 to S5 of the first switch group 7 change their respective connections to the reference voltage VREF when a bit corresponding to each of the 6 low-order bits is "1", while they are connected to the ground potential GND when it is "0". The changeover switches SM0, SM1, SM2 of the second switch group 9 change their respective connections in accordance with a state of the 2 high-order bits as shown in a table below.

______________________________________B.sub.6  B.sub.7          S.sub.M0     S.sub.M1                             S.sub.M2______________________________________0        0     GND          GND   GND1        0     V.sub.REF    GND   GND0        1     V.sub.REF    V.sub.REF                             GND1        1     V.sub.REF    V.sub.REF                             V.sub.REF______________________________________

In the table, B7 represents the most significant bit, while B6 represents the second most significant bit. GND represents the changeover switches SM0, SM1, SM2 change their respective connections to the ground potential GND, while VREF represents they change their respective connections to the reference voltage VREF.

A function of the digital/analog converter will be explained, comparing with a conventional digital/analog converter shown in FIG. 11.

Now, in the digital/analog converter shown in FIG. 11, a case where the changeover switch, for example, S3 changes its connection to the reference voltage VREF while other changeover switches S0 to S2 and S4 to S7 change their respective connections to the ground potential GND will be discussed. In this case, since a combined resistance on the left of a point C in FIG. 11 is R, a combined resistance on the left of a point D is 2R. Also, a resistance on a part above a point D is 2R. Thus, a combined resistance of both on the left of and above the point D is R. As a result, the voltage at the point D is found to be 1/2 of the voltage at a point E. This relation covers all the cases related to all points A to H in FIG. 11.

Thus, an output voltage VOUT of the analog/digital converter can be generally expressed by an equation as follows: ##EQU1## "b0 " to "b7 " are numbers that are "1"s when the changeover switches S0 to S7 are connected to the reference voltage VREF but are "0"s when they are connected to the ground potential GND.

Thus, the changeover switches S0 to S7 change their respective connections in accordance with a state of corresponding bits of the digital signal, whereby the 8 bit digital/analog converter is implemented.

On the other hand, a digital/analog converter of an embodiment of the present invention, shown in FIG. 1, can also be drawn as in FIG. 2. In FIG. 2, V1 denotes a voltage on the left of a point G of FIG. 1, while V2 denotes a voltage on the right of the point G.

The voltage V1 can be obtained in a way similar to VOUT in the equation (1) and be expressed by an equation as follows: ##EQU2##

The voltage V2 can be expressed by an equation as follows: ##EQU3## where bM0, bM1, bM2 are numbers that are "1"s when the changeover switches SM0, SM1, SM2 are connected to the reference voltage VREF but are "0"s when they are connected to the ground potential GND.

Thus, the output voltage VOUT is expressed, using the Thevenin's theorem, by an equation as follows: ##EQU4##

When the expressions (2), (3) are substituted for V1 and V2 in the equation (4), an equation is obtained as follows: ##EQU5## "b6 and b7 " in the equation (1) and "bM0, bM1, bM2 " in the equation (5) are related as in the table below:

______________________________________b.sub.6   b.sub.7           b.sub.M0     b.sub.M1                             b.sub.M2______________________________________0         0     0            0    01         0     1            0    00         1     1            1    01         1     1            1    1______________________________________

The relation is expressed with an equation as follows:

2.sup.6 ·b.sub.6 +2.sup.7 ·b.sub.7 =2.sup.6 ·(b.sub.M0 +b.sub.M1 +b.sub.M2)

Then, an improvement of a monotonicity by virtue of the digital/analog converter of the present invention will be described. FIG. 3 shows a state in which the conventional circuit in FIG. 11 has its resistances varied only by (1+δ) in the resistance values, R and 2R, while FIG. 4 shows a state in which a circuit of the embodiment according to the present invention in FIG. 1 has its resistances R1 to R13 and RM0 to RM2 varied only by (1+δ) in the resistance values, R and 2R.

A monotonicity of the conventional circuit in FIG. 3 is most easily impeded when the changeover switch S7 having the largest weight changes the connection; that is, a state satisfying b7 =0, b6 =b5 =b4 =b3 =b2 =b1 =b0 =1 turns to a state satisfying b7 =1, b6 =b5 =b4 =b3 =b2 =b1 =b0 =0.

When the digital signals (b7, b6, b5, b4, b3, b2, b1, b0) is applied with (1, 0, 0, 0, 0, 0, 0, 0), the circuit in FIG. 3 is shown as that in FIG. 5.

An impedance ZA seen from a point A to the left is obtained as follows: ##EQU6## where ##EQU7##

Now, assuming that δ2, δ1 <<1 and terms of the second degree or more is neglected (Newton's linear approximation), ZA is obtained as follows: ##EQU8##

Similarly, an impedance ZB seen from a point B to the left is obtained as follows: ##EQU9##

Similarly, an impedance ZC seen from a point C to the left is obtained as follows: ##EQU10##

With this equation, the impedance decreases initially by 1/2 and then by 1/4 as it goes to each less significant bit, for the resistance of resistance value 2R (the resistance between the contact point and the ground). On the other hand, the impedance decreases initially by 1/4 and further by 1/4 as it goes to each less significant bit, for the resistance of resistance value R (the resistance between the contact points).

Thus, an impedance ZG seen from a point G to the left is obtained as follows: ##EQU11##

Thus, an impedance ZH seen from a point H to the left is obtained as follows: ##EQU12##

Thus, the output voltage VOUT (1, 0, 0, 0, 0, 0, 0, 0) when the digital signal (1, 0, 0, 0, 0, 0, 0, 0) was applied is obtained as follows: ##EQU13##

On the other hand, when the digital signal is applied with (0, 1, 1, 1, 1, 1, 1, 1), a circuit in FIG. 3 is shown as that in FIG. 6.

With the principle of superposition, an output voltage of the circuit in FIG. 6 is an output voltage VOUT7 of a circuit in FIG. 7 subtracted by an output voltage VOUT8 of a circuit in FIG. 8.

The output voltage VOUT7 in FIG. 7 is obtained as follows:

V.sub.OUT7 =V.sub.REF -V.sub.OUT (1, 0, 0, 0, 0, 0, 0, 0)

The expression in the equation (6) is substituted for the VOUT (1, 0, 0, 0, 0, 0, 0, 0): ##EQU14##

The output voltage VOUT8 in FIG. 8 is obtained as follows. In this case, a circuit in FIG. 8 is in a state where a resistance 2R(1+δ1) equivalent to 1 bit is connected to VREF as compared with a state where resistances 2R(1+δi) (i=1, 2, 4, 6, 8, 10, 12, 14, 16) are grounded. ##EQU15## where δerror is an error component caused by δ0 to δ15.

Thus, an output voltage of the circuit in FIG. 6, or the output voltage VOUT (0, 1, 1, 1, 1, 1, 1, 1) when the digital signal is applied with (0, 1, 1, 1, 1, 1, 1, 1), can be expressed, using the above equations (7) and (8), as follows: ##EQU16##

Then, a difference voltage ΔVOUT between VOUT (1, 0, 0, 0, 0, 0, 0, 0) and VOUT (0, 1, 1, 1, 1, 1, 1, 1) is obtained, using the above equations (6) and (9), as follows: ##EQU17##

The δerror is negligible because it is a very small value, and can be expressed as follows: ##EQU18##

The equation (10) shows an amount of a variation in the output voltage VOUT when the digital signal is altered from (0, 1, 1, 1, 1, 1, 1, 1) to (1, 0, 0, 0, 0, 0, 0, 0), and in the case where the conventional circuit in FIG. 3 is used, its monotonicity is impeded when δ16 is 1/27 or more.

Meanwhile, in a circuit of an embodiment according to the present invention shown in FIG. 4, its monotonicity is impeded most when the changeover switches SM0, SM1, SM2 having the largest weight change their respective connections as in three cases below:

(1) A state where bM2 =0, bM1 =0, bM0 =0, b5 =b4 =b3 =b2 =b1 =1 are satisified is changed into a state where bM2 =0, bM1 =0, bM0 =1, b5 =b4 =b3 =b2 =b1 =b0 =0 are satisfied.

(2) A state where bM2 =0, bM1 =0, bM0 =1, b5 =b4 =b3 =b2 =b1 =1 are satisfied is changed into a state where bM2 =0, bM1 =1, bM0 =1, b5 =b4 =b3 =b2 =b1 =b0 =0 are satisfied.

(3) A state where bM2 =0, bM1 =1, bM0 =1, b5 =b4 =b3 =b2 =b1 =b0 =1 are satisfied is changed into a state where bM2 =1, bM1 =1, bM0 =1, b5 =b4 =b3 =b2 =b1 =b0 =0 are satisfied.

An amount of a variation in the output voltage VOUT in these cases is obtained in the same way as employed for the conventional circuit in FIG. 3, as follows:

In the case of (1): ##EQU19##

As will be recognized from the above equations (11), (12) and (13), in the circuit of the embodiment according to the present invention, a monotonicity is impeded when δM0, δM1 and δM2 are 1/26 or more.

In other words, it will be recognized that the circuit of the embodiment according to the present invention in FIG. 4 requires the matching of resistors in a half degree varied to a range of to that of the conventional circuit in FIG. 3, so as to maintain its monotonicity, compared with the conventional circuit in FIG. 3.

In this way, it is easy to maintain a monotonicity in a circuit of the embodiment according to the present invention shown in FIG. 1, and this is because an amount of a variation in the output voltage VOUT caused by a changeover of the changeover switch S7 is 27 times as large as that caused by a changeover of the changeover switch S0 in the circuit in FIG. 11, while an amount of variation in the output voltage VOUT caused by a changeover of each of the changeover switches SM0, SM1 and SM2 is only 26 times as large as that caused by a changeover of the changeover switch S0.

Thus, the first digital/analog converting circuit 4 has a specified number of changeover switchs S0 to S5 and the same number of resistances R2 to R13 corresponding to the number of low order bits, while the second digital/analog converting circuit 5 has more changeover switches SM0 to SM2 and RM0 to RM2 than the number of high order bits, so that the monotonicity can be maintained without enhancing a matching of resistors.

A case in which an 8 bit digital signal is converted into an analog signal has been described. In general, when a digital signal consisting of NL low-order bits and NU high-order bits is converted into an analog signal, the circuit in FIG. 1 may be provided with the first switch group 7 consisting of NL changeover switches and the R-2R circuit 6 including the same number of R- and 2R-resistances, and may be further provided with the second switch group 9 consisting of (2N -1) changeover switches and the 2R circuit 8 including the same number of 2R-resistances. Each of the changeover switches of the first switch group 7 may change its connection to the reference voltage VREF or the ground potential GND in accordance with a state of corresponding bit of the low-order bits, and the number of the changeover switches of the second switch group 9 which change the connections to the reference voltage VREF is determined in accordance with a state of the high-order bits.

Thus, when the digital signal is generally represented by the low-order NL bits and the high-order NU bits, a digital/analog circuit equivalent to that shown in FIG. 2 is shown as a circuit in FIG. 9. A point N in FIG. 9 corresponds to a junction of the first and second digital/analog converting circuits 4 and 5, while V1 and V2 denote voltages when the first and second digital/analog converting circuits 4 and 5 are seen from the point N, respectively.

The V1 and V2 are expressed as follows: ##EQU20## Thus, the output voltage VOUT is expressed as follows: ##EQU21##

For a reference, a digital/analog converter for converting a 9 bit digital signal into an analog signal is shown in FIG. 10, where NL which is the number of the low-order bits is set "6" and NU which is the number of the high-order bits is set "3". In this case, the number of the changeover switches and that of the resistances provided in the second digital/analog converting circuit 5 are calculated as follows:

2.sup.Nu -1=2.sup.3 -1=7

Thus, there are seven of the changeover switches SM0 to SM6 and seven of the resistances RM0 ˜RM6 in the second digital/analog converting circuit 5.

The changeover switches SM0 to SM6 of the second switch group 9 change their respective connections in accordance with the state of the high-order 3 bits, as shown in a table below.

__________________________________________________________________________B.sub.6  B.sub.7    B.sub.8 S.sub.M0      S.sub.M1          S.sub.M2               S.sub.M3                   S.sub.M4                       S.sub.M5                           S.sub.M6__________________________________________________________________________0 0 0 GND  GND GND  GND GND GND GND1 0 0 V.sub.REF      GND GND  GND GND GND GND0 1 0 V.sub.REF      V.sub.REF          GND  GND GND GND GND1 1 0 V.sub.REF      V.sub.REF          V.sub.REF               GND GND GND GND0 0 1 V.sub.REF      V.sub.REF          V.sub.REF               V.sub.REF                   GND GND GND1 0 1 V.sub.REF      V.sub.REF          V.sub.REF               V.sub.REF                   V.sub.REF                       GND GND0 1 1 V.sub.REF      V.sub.REF          V.sub.REF               V.sub.REF                   V.sub.REF                       V.sub.REF                           GND1 1 1 V.sub.REF      V.sub.REF          V.sub.REF               V.sub.REF                   V.sub.REF                       V.sub.REF                           V.sub.REF__________________________________________________________________________

In the above table, B6, B7 and B8 denote the high-order 3 bits. GND represents that the changeover switches SM0 to SM6 change their respective connections to the ground potential GND, while VREF represents that they change their respective connections to the reference voltage VREF.

The output voltage VOUT of the digital/analog converter is expressed, substituting NL =6 and NU =3 for the corresponding character elements in the equation (14), as follows: ##EQU22##

The digital/analog converter attains the same effect as the above-mentioned embodiment.

In the above embodiment, although the reference voltage VREF is applied to the first input terminal 1 while the ground potential GND is applied to the second input terminal 2, the present invention does not limit the voltage applied to the first and second input terminals 1 and 2 to the aforementioned voltage; first and second reference potentials of mutually different values have only to be applied to the first and second input terminals 1 and 2, respectively.

Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.

Claims (4)

What is claimed is:
1. A digital/analog converter which converts a digital signal of a binary number consisting of NL low-order bits and NU high-order bits into an analog signal, comprising:
a first input terminal to which first reference potential is applied;
a second input terminal to which second reference potential is applied;
an output terminal;
a first digital/analog converting circuit driven in accordance with a digital data of said low-order bits; and
a second digital/analog converting circuit driven in accordance with a digital data of said high-order bits;
said first digital/analog converting circuit including:
a first resistor of resistance value 2R having its one end connected to said second input terminal;
R-2R circuitry which includes NL second resistors of resistance value R connected in series and NL third resistors of resistance value 2R having their respective one ends connected to one ends of said second resistors; a junction of the one end of said second resistor and the one end of said third resistor disposed on one side being connected to the other end of said first resistor, and the other end of said second resistor disposed on the other side being connected to said output terminal; and
a first switch group which consists of NL first changeover switches having their respective first and second changeover contact points and common contact points; in each of said first changeover switches, said first changeover contact point being connected to said first input terminal, said second changeover contact point being connected to said second input terminal and said common contact point being connected to the other end of said corresponding third resistor, and each of said first changeover switches changing its connection between said first and second changeover contact points in accordance with a state of each bit of said low-order bits;
said second digital/analog converting circuit including:
2R circuitry which consists of (2N -1) fourth resistors of resistance value 2R having their respective one ends commonly connected and having said one ends connected to said output terminal; and
a second switch group which consists of (2N -1) second changeover switches having their respective first and second changeover contact points and common contact points; in each of said second changeover switches, said first changeover contact point being connected to said first input terminal, said second changeover contact point being connected to said second input terminal and said common contact point being connected to the other end of said corresponding fourth resistor, and the number of said second changeover switches changing their respective connections to said first changeover contact points being determined in accordance with a state of said high-order bits.
2. A digital/analog converter according to claim 1, wherein the number NL of said low-order bits is 6, while the number NU of said high-order bits is 2.
3. A digital/analog converter according to claim 1, wherein the number NL of said low-order bits is 6, while the number NU of said high-order bits is 3.
4. A digital/analog converter according to claim 1, wherein said first reference potential is reference voltage VREF having a specified positive voltage, while said second reference potential is ground potential.
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Cited By (7)

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US5175548A (en) * 1990-10-12 1992-12-29 Nec Corporation Digital-analog converter including a reduced number of resistors arranged in a string
US5467036A (en) * 1993-09-01 1995-11-14 Rohm Co., Ltd. Integrated circuit device for driving elements and light emitting device
WO1999021281A1 (en) * 1997-10-21 1999-04-29 Lautzenhiser Lloyd L Adaptive frequency-hopping oscillators
US6411237B1 (en) 1997-10-21 2002-06-25 Emhiser Research Ltd Nonlinear digital-to-analog converters
US20120201284A1 (en) * 2009-10-13 2012-08-09 Advantest Corporation Multi-valued driver circuit
CN103166645A (en) * 2011-12-14 2013-06-19 上海华虹Nec电子有限公司 R-2R type digital analog converter circuit
RU2546557C2 (en) * 2013-07-08 2015-04-10 Корпорация "САМСУНГ ЭЛЕКТРОНИКС Ко., Лтд." Digital-to-analogue converter

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US3755807A (en) * 1972-02-15 1973-08-28 Collins Radio Co Resistor-ladder circuit
US4580131A (en) * 1983-06-03 1986-04-01 Harris Corporation Binarily weighted D to a converter ladder with inherently reduced ladder switching noise
US4631518A (en) * 1984-09-24 1986-12-23 Tektronix, Inc. Digital-to-analog converter biasing control circuit
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US4833473A (en) * 1987-10-05 1989-05-23 Harris Semiconductor Patents, Inc. Digital to analog converter with switch function compensation
US4843394A (en) * 1988-01-21 1989-06-27 Advanced Micro Devices, Inc. Digital-to-analog converter with no offset-induced errors

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5175548A (en) * 1990-10-12 1992-12-29 Nec Corporation Digital-analog converter including a reduced number of resistors arranged in a string
US5467036A (en) * 1993-09-01 1995-11-14 Rohm Co., Ltd. Integrated circuit device for driving elements and light emitting device
WO1999021281A1 (en) * 1997-10-21 1999-04-29 Lautzenhiser Lloyd L Adaptive frequency-hopping oscillators
US6411237B1 (en) 1997-10-21 2002-06-25 Emhiser Research Ltd Nonlinear digital-to-analog converters
US6417738B1 (en) 1997-10-21 2002-07-09 Emhiser Research Limited Adaptive frequency-hopping oscillators
US20120201284A1 (en) * 2009-10-13 2012-08-09 Advantest Corporation Multi-valued driver circuit
US8575961B2 (en) * 2009-10-13 2013-11-05 Advantest Corporation Multi-valued driver circuit
CN103166645A (en) * 2011-12-14 2013-06-19 上海华虹Nec电子有限公司 R-2R type digital analog converter circuit
CN103166645B (en) * 2011-12-14 2016-02-10 上海华虹宏力半导体制造有限公司 R-2r one kind of digital-analogue converter circuit
RU2546557C2 (en) * 2013-07-08 2015-04-10 Корпорация "САМСУНГ ЭЛЕКТРОНИКС Ко., Лтд." Digital-to-analogue converter

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JP2837726B2 (en) 1998-12-16 grant
JPH03238927A (en) 1991-10-24 application

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