US4786904A - Electronically programmable gate array having programmable interconnect lines - Google Patents

Electronically programmable gate array having programmable interconnect lines Download PDF

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Publication number
US4786904A
US4786904A US06941765 US94176586A US4786904A US 4786904 A US4786904 A US 4786904A US 06941765 US06941765 US 06941765 US 94176586 A US94176586 A US 94176586A US 4786904 A US4786904 A US 4786904A
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Prior art keywords
programmable
cells
logic
voltage
interconnect
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US06941765
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Hatch Graham, III
Daniel Seltz
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Zoran Corp
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Zoran Corp
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    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K19/00Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/1733Controllable logic circuits
    • H03K19/1735Controllable logic circuits by wiring, e.g. uncommitted logic arrays
    • H03K19/1736Controllable logic circuits by wiring, e.g. uncommitted logic arrays in which the wiring can be modified

Abstract

An electronically programmable gate array comprises a plurality of rows of logic cells with each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell. A plurality of sets of interconnect lines are formed in the array with one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable contacts connecting inputs and an output of each cell in a row of cells with two adjacent sets of interconnect lines. Each row of logic cells preferably includes alternating three-input cells and two-input cells. Each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials. Each electronically programmable interconnect comprises a voltage alterable resistor.

Description

BACKGROUND OF THE INVENTION

This invention relates generally to programmable logic circuitry, and more particularly the invention relates to circuitry which is flexible in application and efficient in circuit implementation.

Programmable logic circuits are important design tools and also provide a convenient replacement for small and medium scale integrated circuits. They allow the circuit designer to reduce package count with attendant lower cost and higher reliability. They also reduce inventory costs since a single programmable circuit can be used for many different applications.

A number of integrated circuits are known which offer programming flexibility. The electrically programmable logic array (PLA) and the field programmable logic array (FPLA) offer circuit flexibility but require complex circuitry which is not cost effective. The PLA comprises an array of logical AND gates and OR gates which can be programmed by mask during manufacture or by fusible links for a specific function in random logic networks, data routing, code converters, decoders, and the like.

The programmable array logic (PAL) was introduced to improve cost effectiveness but has substantially less flexibility in use. As described in U.S. Pat. No. 4,124,899, the PAL comprises a matrix of circuit inputs and the inputs to a plurality of AND gates. Outputs from subgroups of AND gates are non-programmably connected as inputs to individual, specific OR gates.

Copending application Ser. No. 754,653 filed July 15, 1985, now abandoned, discloses an electronically programmable gate array which has instant field programming features and includes universal (i.e. versatile configurable or programmable) logic cells. Moreover, the array is inexpensive and permits quick logic design and implementation. Since the array provides fast return time, circuits can be designed, fabricated, tested and installed more quickly than custom circuitry (e.g. gate array, standard cells, and full custom) and permit lower relative costs of producing a final product when non-recurring expenses are included.

Briefly, the electronically programmable gate array includes a plurality of cells with each cell including a plurality of gates which can provide at least one programmable logic function such as a gate, a flip-flop, and the like. A programmable interconnect structure is provided to selectively interconnect the gates of each cell and the plurality of cells. The selectively interconnected cells are interconnected by means of address and programming lines, with input/output pins, clock, and reset lines. Each of the cells is programmable to alter the specific functions thereof. Accordingly, a wide variety of programming options are provided. In accordance with one feature of the invention, electrically programmable elements determine the interconnect pattern and the specific function of the cells (e.g. gates and flip-flops).

SUMMARY OF THE INVENTION

The present invention is directed to an electonically programmable gate array and a unique array architecture whereby the interconnection of gates is facilitated. In accordance with a preferred embodiment, the gate array comprises a plurality of rows, each containing a plurality of logic cells, each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell. A plurality of sets of interconnect lines are provided with one set of interconnect lines being provided between adjacent rows of logic cells and with electronically programmable means selectively connecting inputs and an output of each cell in a row of cells with two adjacent sets of interconnect lines.

In a preferred embodiment each row of logic cells includes alternating three input cells and two input cells. Each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials with means connecting the common terminal of the resistors to the logic cell.

In accordance with another feature of the invention the programmable means interconnecting inputs and an output of each cell in a row of cells with the adjacent sets of interconnect lines comprises a voltage variable resistor having minimum capacitance associated therewith.

The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawing.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a functional block overview of an electronically programmable gate array in accordance with the invention.

FIG. 2 is a functional block diagram of a portion of the array of FIG. 1 further illustrating rows of logic cells and rows of programmable interconnect lines therein.

FIG. 3 is a schematic of voltage alterable resistors in the interconnect lines of FIGS. 1 and 2.

FIGS. 4A and 4B are a block diagram and a circuit schematic of a two-unit cell for use in the array of FIG. 1.

FIGS. 5A and 5B are a block diagram and a circuit schematic of a three-input cell for use in the array of FIG. 1.

FIG. 6 is a schematic of an electronically programmable voltage level as used in the cells of FIGS. 4 and 5.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENT

Referring now to the drawings, FIG. 1 is a functional block overview of an electronically programmable gate array in accordance with the invention. The array is fabricated in a monolithic semiconductor chip 10 and comprises a plurality of logic cells 12 and a plurality of interconnect lines 14. Each row of logic cells has a set of interconnect lines 14 on either side thereof. The periphery of the semiconductor chip 10 surrounding the gate array structure accommodates test and programming circuitry for the array, and means for handling input and output signals.

FIG. 2 is a functional block diagram of a portion of the array of FIG. 1 and further illustrates the logic cells in each row and the interconnect channels between rows. In a preferred embodiment each row of logic cells includes alternating three-input cells 20 and two-input cells 22. The inputs and output for each cell are interconnected with lines in each adjacent interconnect channel by means of programmable interconnects illustrated by the circles 24. In this embodiment each interconnect channel comprises ten lines, and each input and each output of the cells is interconnectable with any one of the lines by means of the programmable elements 24. While various programming elements are known in the art, the preferred programming element is the voltage variable resistor disclosed in Gerzberg U.S. Pat. No. 4,590,589. The voltage programmable structure disclosed therein comprises a resistor structure including a body of semiconductor material having high electrical conductance and a surface contact region having a crystalline structure characterized by relatively high electrical resistance. The relatively high electrical resistance can be established by amorphotizing the surface region or by forming lattice defects in the crystalline structure such as by ion implantation. In programming the resistor device a sufficient voltage is applied across the resistor whereby the surface region becomes heated sufficiently to reduce the relatively high electrical resistance. Such a programming device has the advantages of being readily manufactured using conventional semiconductor processing techniques and low capacitance associated therewith.

FIG. 3 is a schematic representation of circuitry for programming the voltage variable resistors of FIG. 2. Each vertical Y-select line has associated therewith a programming transistor 28, and each horizontal X-select line has associated therewith a transistor 30. By selectively biasing a transistor 28 and a transistor 30, a programming voltage (e.g., +15 V) and a ground potential are applied across a variable resistor 24 which is sufficient to convert the resistance state of the resistor to a lower conductive level. During programming of the selected variable resistor the unselected horizontal interconnect lines 33 are connected to a supply equal to half the programming voltage (e.g., 7.5 V selected by transistors 31). The unselected vertical interconnect lines 35 are floating. The variable resistor's programming threshold is greater than 7.5 V but less than 15 V Only one horizontal interconnect line can be programmably connected to each vertical interconnect line.

In order that each input and output of each cell can be connected to a horizontal interconnect line in both of the two interconnect channels adjacent to (e.g. above and below) the row of cells, additional means can be provided for isolating the two portions of the vertical interconnect line associated with the respective adjacent horizontal interconnect channels. However, interconnection to both interconnect channels is not essential to operation. The vertical interconnect lines are the inputs and outputs of the cells.

FIGS. 4A and 4B and FIGS. 5A and 5B are a block diagram and circuit schematic of a two-input and a three-input logic cell useful in the array of FIG. 1. The logic functions realized with the two-input logic cell 40 of FIG. 4 is given in accordance with the following table:

__________________________________________________________________________      INPUTSLOGIC FUNCTION      A.sup.1        B.sup.1          C.sup.1            D.sup.1                E.sup.1                  MCLKH.sup.3                        MRESH.sup.3                             IN.sup.1                                 IN.sup.2__________________________________________________________________________2-IN OR    H L L H   L MCLK  MRES INP INP2-IN AND   L L L L   L MCLK  MRES INP INP2-IN IAND  L L L H   L MCLK  MRES INP INP2-IN IOR   H L L L   L MCLK  MRES INP INP2-IN EXOR  L H L H   L MCLK  MRES INP INP2-IN EXNOR L H L L   L MCLK  MRES INP INPINVERTER   H H L L   L MCLK  MRES TRI INPD-TYPE LATCH      L L H H/L.sup.4                H MCLK  MRES DATA                                 CLKD-TYPE LATCH      L L H H/L.sup.4                H MCLK  MRES DATA                                 TRIW/MCLK,MRES__________________________________________________________________________ .sup.1 Input must be permanently fixed by means of "EPVL" modules. .sup.2 Input may be tristated or driven depending on desired logic cell function. .sup.3 Input must be driven. .sup.4 A high (H) or low (L) respectively configure the latch as a slave or master.

The logic functions realizable with the three-input logic cell are given in accordance with the following table:

______________________________________LOGIC     INPUTSFUNCTION  A.sup.1 B.sup.1                   C.sup.1                         D.sup.1                             IN2.sup.2                                   IN1.sup.2                                        IN0______________________________________2-IN OR   L       L     L     L   INP   TRI  INP2-IN NOR  H       L     L     L   INP   TRI  INP2-IN AND  L       L     H     H   TRI   INP  INP2-IN NAND H       L     H     H   TRI   INP  INP2-IN EXOR L       H     L     H   INP   TRI  INP2-IN EXNOR     H       H     L     H   INP   TRI  INP3-IN MUX  L       L     L     H   INP   INP  INPINVERTER  H       H     H     H   TRI   TRI  INP______________________________________ .sup.1 Input must be permanently fixed by means of "EPVL" modules. .sup.2 Input may be tristated or driven depending on desired logic cell function.

The programming of the two-input logic cell 40 and a three-input logic cell 50 illustrated in FIGS. 4 and 5 is effected through use of electronically programmable voltage levels (EPVL) between a low voltage state (L) and a high voltage state (H). A schematic of the EPVL is given in FIG. 6. Two voltage programmable resistors 34 and 36 are serially connected between a high voltage potential, +V, and a low voltage potential, ground. By applying a suitable voltage on the control signal line and selectively rendering one of the voltage programmable resistors conductive, such as described above with reference to FIG. 3, either the high voltage level or the ground potential can be applied to a circuit terminal. Thus, the programming of the voltage variable resistors 34, 36 is effected through the voltage on the control signal line and the ground or +V potentials.

The design of an electronically programmable gate array in accordance with the invention with interconnect channels provided between rows of programmable logic cells facilitates the fabrication and programming of large and complex gate arrays. The programming of a cell by electronically programmable voltage levels and the interconnection of cells using the voltage variable resistors facilitates programming and minimizes the capacitance associated with the programming elements. While the invention has been described with reference to a specific embodiment, the description is illustrative of the invention and is not to be construed as limiting. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.

Claims (2)

We claim:
1. An electronically programmable gate array comprising
a plurality of rows of logic cells, each row of logic cells includes alternating three-input cells of programmable gates and two-input cells of programmable gates, each cell having a plurality of inputs, at least one output, and a plurality of electronically programmable voltage levels for configuring the cell, wherein each electronically programmable voltage level comprises two voltage alterable resistors serially connected between first and second voltage potentials, and
a plurality of sets of interconnect lines, one set of interconnect lines provided between adjacent rows of logic cells with electronically programmable means connecting inputs and an output of each cell in a row of cells with either of two adjacent sets of interconnect lines, each electronically programmable means comprises a voltage alterable resistor.
2. The electronically programmable gate array as defined by claim 1 wherein each two-input logic cell is programmable for the following functions:
2-IN OR
2-IN AND
2-IN IAND
2-IN IOR
2-IN EXOR
2-IN EXNOR
INVERTER
D-TYPE LATCH
and each three-input logic cell is programmable for the following functions:
2-IN OR
2-IN NOR
2-IN AND
2-IN NAND
2-IN EXOR
2-IN EXNOR
3-IN MUX
INVERTER.
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Cited By (125)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873459A (en) * 1986-09-19 1989-10-10 Actel Corporation Programmable interconnect architecture
US4963770A (en) * 1987-11-20 1990-10-16 Kawasaki Steel Corporation Programmable logic device
US4982114A (en) * 1988-04-27 1991-01-01 Hitachi, Ltd. Semiconductor logic device having two-dimensional logic arrays and logic cell chains alternately arranged
US5001368A (en) * 1988-12-09 1991-03-19 Pilkington Micro-Electronics Limited Configurable logic array
US5003200A (en) * 1988-09-20 1991-03-26 Kawasaki Steel Corporation Programmable logic device having programmable wiring for connecting adjacent programmable logic elements through a single switch station
US5015885A (en) * 1986-09-19 1991-05-14 Actel Corporation Reconfigurable programmable interconnect architecture
WO1991007015A1 (en) * 1989-10-25 1991-05-16 Concurrent Logic, Inc. Programmable logic cell and array
US5036473A (en) * 1988-10-05 1991-07-30 Mentor Graphics Corporation Method of using electronically reconfigurable logic circuits
WO1991013495A1 (en) * 1990-03-01 1991-09-05 Plus Logic, Inc. Programmable logic device with programmable inverters at input/output pads
US5056053A (en) * 1988-02-11 1991-10-08 The Mitre Corporation Algebraic transform machine
US5068823A (en) * 1988-07-11 1991-11-26 Star Semiconductor Corporation Programmable integrated circuit using topological and parametric data to selectively connect and configure different high level functional blocks thereof
US5073729A (en) * 1990-06-22 1991-12-17 Actel Corporation Segmented routing architecture
US5089973A (en) * 1986-11-07 1992-02-18 Apple Computer Inc. Programmable logic cell and array
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5122685A (en) * 1991-03-06 1992-06-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5128871A (en) * 1990-03-07 1992-07-07 Advanced Micro Devices, Inc. Apparatus and method for allocation of resoures in programmable logic devices
US5132571A (en) * 1990-08-01 1992-07-21 Actel Corporation Programmable interconnect architecture having interconnects disposed above function modules
US5144166A (en) * 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
WO1992017001A1 (en) * 1991-03-18 1992-10-01 Crosspoint Solutions, Inc. A field programmable gate array
US5153463A (en) * 1990-04-11 1992-10-06 Kawasaki Steel Corporation Programmable logic device having a reduced switching matrix
US5166556A (en) * 1991-01-22 1992-11-24 Myson Technology, Inc. Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits
US5185706A (en) * 1989-08-15 1993-02-09 Advanced Micro Devices, Inc. Programmable gate array with logic cells having configurable output enable
WO1993005577A1 (en) * 1991-08-30 1993-03-18 Concurrent Logic, Inc. Programme logic cell and array
WO1993006559A1 (en) * 1991-09-23 1993-04-01 Aptix Corporation Universal interconnect matrix array
US5208491A (en) * 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
US5218240A (en) * 1990-11-02 1993-06-08 Concurrent Logic, Inc. Programmable logic cell and array with bus repeaters
US5220213A (en) * 1991-03-06 1993-06-15 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5221865A (en) * 1991-06-21 1993-06-22 Crosspoint Solutions, Inc. Programmable input/output buffer circuit with test capability
DE4211162A1 (en) * 1992-03-31 1993-10-07 Krone Ag Asic Prototyper
US5255203A (en) * 1989-08-15 1993-10-19 Advanced Micro Devices, Inc. Interconnect structure for programmable logic device
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
US5260611A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic array having local and long distance conductors
US5260881A (en) * 1989-10-30 1993-11-09 Advanced Micro Devices, Inc. Programmable gate array with improved configurable logic block
US5294846A (en) * 1992-08-17 1994-03-15 Paivinen John O Method and apparatus for programming anti-fuse devices
US5321322A (en) * 1991-11-27 1994-06-14 Aptix Corporation Programmable interconnect architecture without active devices
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US5341043A (en) * 1992-09-30 1994-08-23 Actel Corporation Series linear antifuse array
US5341092A (en) * 1986-09-19 1994-08-23 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5347519A (en) * 1991-12-03 1994-09-13 Crosspoint Solutions Inc. Preprogramming testing in a field programmable gate array
US5359536A (en) * 1989-08-15 1994-10-25 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5365165A (en) * 1986-09-19 1994-11-15 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5371390A (en) * 1990-10-15 1994-12-06 Aptix Corporation Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
US5371422A (en) * 1991-09-03 1994-12-06 Altera Corporation Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements
US5377124A (en) * 1989-09-20 1994-12-27 Aptix Corporation Field programmable printed circuit board
US5381058A (en) * 1993-05-21 1995-01-10 At&T Corp. FPGA having PFU with programmable output driver inputs
US5384481A (en) * 1991-01-17 1995-01-24 Crosspoint Solutions, Inc. Antifuse circuit structure for use in a field programmable gate array and method of manufacture thereof
US5400262A (en) * 1989-09-20 1995-03-21 Aptix Corporation Universal interconnect matrix array
US5416367A (en) * 1991-03-06 1995-05-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5424655A (en) * 1994-05-20 1995-06-13 Quicklogic Corporation Programmable application specific integrated circuit employing antifuses and methods therefor
US5436575A (en) * 1991-09-03 1995-07-25 Altera Corporation Programmable logic array integrated circuits
US5440245A (en) * 1990-05-11 1995-08-08 Actel Corporation Logic module with configurable combinational and sequential blocks
US5448493A (en) * 1989-12-20 1995-09-05 Xilinx, Inc. Structure and method for manually controlling automatic configuration in an integrated circuit logic block array
US5448496A (en) * 1988-10-05 1995-09-05 Quickturn Design Systems, Inc. Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system
US5451887A (en) * 1986-09-19 1995-09-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5465055A (en) * 1994-10-19 1995-11-07 Crosspoint Solutions, Inc. RAM-logic tile for field programmable gate arrays
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5483178A (en) * 1993-03-29 1996-01-09 Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
US5485031A (en) * 1993-11-22 1996-01-16 Actel Corporation Antifuse structure suitable for VLSI application
US5495181A (en) * 1994-12-01 1996-02-27 Quicklogic Corporation Integrated circuit facilitating simultaneous programming of multiple antifuses
US5502315A (en) * 1989-09-07 1996-03-26 Quicklogic Corporation Electrically programmable interconnect structure having a PECVD amorphous silicon element
US5510730A (en) 1986-09-19 1996-04-23 Actel Corporation Reconfigurable programmable interconnect architecture
US5527745A (en) * 1991-03-20 1996-06-18 Crosspoint Solutions, Inc. Method of fabricating antifuses in an integrated circuit device and resulting structure
US5537108A (en) * 1994-02-08 1996-07-16 Prolinx Labs Corporation Method and structure for programming fuses
US5552720A (en) * 1994-12-01 1996-09-03 Quicklogic Corporation Method for simultaneous programming of multiple antifuses
US5561367A (en) * 1992-07-23 1996-10-01 Xilinx, Inc. Structure and method for testing wiring segments in an integrated circuit device
US5572409A (en) * 1994-02-08 1996-11-05 Prolinx Labs Corporation Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board
US5590349A (en) * 1988-07-11 1996-12-31 Logic Devices, Inc. Real time programmable signal processor architecture
US5592106A (en) * 1995-05-17 1997-01-07 Altera Corporation Programmable logic array integrated circuits with interconnection conductors of overlapping extent
US5614756A (en) * 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
US5629636A (en) * 1994-10-19 1997-05-13 Crosspoint Solutions, Inc. Ram-logic tile for field programmable gate arrays
US5633806A (en) * 1992-10-12 1997-05-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit and method of designing same
US5644496A (en) * 1989-08-15 1997-07-01 Advanced Micro Devices, Inc. Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses
US5684980A (en) * 1992-07-29 1997-11-04 Virtual Computer Corporation FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
US5726482A (en) * 1994-02-08 1998-03-10 Prolinx Labs Corporation Device-under-test card for a burn-in board
US5744979A (en) * 1992-07-23 1998-04-28 Xilinx, Inc. FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses
US5744980A (en) * 1996-02-16 1998-04-28 Actel Corporation Flexible, high-performance static RAM architecture for field-programmable gate arrays
US5767575A (en) * 1995-10-17 1998-06-16 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US5777489A (en) * 1995-10-13 1998-07-07 Mentor Graphics Corporation Field programmable gate array with integrated debugging facilities
US5780323A (en) * 1990-04-12 1998-07-14 Actel Corporation Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
US5780919A (en) * 1989-09-07 1998-07-14 Quicklogic Corporation Electrically programmable interconnect structure having a PECVD amorphous silicon element
US5808351A (en) * 1994-02-08 1998-09-15 Prolinx Labs Corporation Programmable/reprogramable structure using fuses and antifuses
US5813881A (en) * 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
US5834824A (en) * 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5872338A (en) * 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
US5884066A (en) * 1994-02-16 1999-03-16 Quickturn Design Systems, Inc. Method and apparatus for a trace buffer in an emulation system
US5883850A (en) * 1991-09-03 1999-03-16 Altera Corporation Programmable logic array integrated circuits
US5906043A (en) * 1995-01-18 1999-05-25 Prolinx Labs Corporation Programmable/reprogrammable structure using fuses and antifuses
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5907697A (en) * 1995-10-13 1999-05-25 Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network
US5917229A (en) * 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
US5936426A (en) * 1997-02-03 1999-08-10 Actel Corporation Logic function module for field programmable array
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US5990502A (en) * 1995-12-29 1999-11-23 Lsi Logic Corporation High density gate array cell architecture with metallization routing tracks having a variable pitch
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6014038A (en) * 1997-03-21 2000-01-11 Lightspeed Semiconductor Corporation Function block architecture for gate array
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6034427A (en) * 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US6223313B1 (en) 1997-12-05 2001-04-24 Lightspeed Semiconductor Corporation Method and apparatus for controlling and observing data in a logic block-based asic
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6421251B1 (en) 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US6611932B2 (en) 1997-12-05 2003-08-26 Lightspeed Semiconductor Corporation Method and apparatus for controlling and observing data in a logic block-based ASIC
US6696856B1 (en) 2001-10-30 2004-02-24 Lightspeed Semiconductor Corporation Function block architecture with variable drive strengths
US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
US20060095886A1 (en) * 1993-08-03 2006-05-04 Ting Beniamin S Architecture and interconnect scheme for programmable logic circuits
US20060097240A1 (en) * 2004-11-08 2006-05-11 Tyler Lowrey Programmable matrix array with chalcogenide material
US20060202716A1 (en) * 1996-09-04 2006-09-14 Pani Peter M Method and apparatus for universal program controlled bus architecture
US20080191739A1 (en) * 1996-09-04 2008-08-14 Pani Peter M Method and apparatus for universal program controlled bus architecture
US20080278678A1 (en) * 2003-10-09 2008-11-13 Howell Thomas A Eyeglasses with user monitoring
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US9274984B2 (en) 2002-09-06 2016-03-01 Pact Xpp Technologies Ag Multi-processor with selectively interconnected memory units
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9690747B2 (en) 1999-06-10 2017-06-27 PACT XPP Technologies, AG Configurable logic integrated circuit having a multidimensional structure of configurable elements

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4124899A (en) * 1977-05-23 1978-11-07 Monolithic Memories, Inc. Programmable array logic circuit
US4531066A (en) * 1974-08-20 1985-07-23 Kearns Robert W Variable bias logic circuit
US4590589A (en) * 1982-12-21 1986-05-20 Zoran Corporation Electrically programmable read only memory
US4596938A (en) * 1982-09-30 1986-06-24 Rca Corporation Electrically erasable programmable electronic circuits using programmable-threshold-voltage FET pairs
US4612459A (en) * 1984-05-31 1986-09-16 Rca Corporation Programmable buffer selectively settable to operate in different modes
US4631686A (en) * 1983-08-31 1986-12-23 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US4642487A (en) * 1984-09-26 1987-02-10 Xilinx, Inc. Special interconnect for configurable logic array
US4670749A (en) * 1984-04-13 1987-06-02 Zilog, Inc. Integrated circuit programmable cross-point connection technique
US4689654A (en) * 1985-04-19 1987-08-25 Nixdorf Computer Ag Logic array chip

Patent Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4531066A (en) * 1974-08-20 1985-07-23 Kearns Robert W Variable bias logic circuit
US4124899A (en) * 1977-05-23 1978-11-07 Monolithic Memories, Inc. Programmable array logic circuit
US4124899B1 (en) * 1977-05-23 1987-04-28
US4596938A (en) * 1982-09-30 1986-06-24 Rca Corporation Electrically erasable programmable electronic circuits using programmable-threshold-voltage FET pairs
US4590589A (en) * 1982-12-21 1986-05-20 Zoran Corporation Electrically programmable read only memory
US4631686A (en) * 1983-08-31 1986-12-23 Kabushiki Kaisha Toshiba Semiconductor integrated circuit device
US4670749A (en) * 1984-04-13 1987-06-02 Zilog, Inc. Integrated circuit programmable cross-point connection technique
US4612459A (en) * 1984-05-31 1986-09-16 Rca Corporation Programmable buffer selectively settable to operate in different modes
US4642487A (en) * 1984-09-26 1987-02-10 Xilinx, Inc. Special interconnect for configurable logic array
US4689654A (en) * 1985-04-19 1987-08-25 Nixdorf Computer Ag Logic array chip

Cited By (196)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5600265A (en) * 1986-09-19 1997-02-04 Actel Corporation Programmable interconnect architecture
US5365165A (en) * 1986-09-19 1994-11-15 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US4873459A (en) * 1986-09-19 1989-10-10 Actel Corporation Programmable interconnect architecture
US5570041A (en) * 1986-09-19 1996-10-29 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5015885A (en) * 1986-09-19 1991-05-14 Actel Corporation Reconfigurable programmable interconnect architecture
US5451887A (en) * 1986-09-19 1995-09-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5510730A (en) 1986-09-19 1996-04-23 Actel Corporation Reconfigurable programmable interconnect architecture
US5606267A (en) * 1986-09-19 1997-02-25 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US5698992A (en) * 1986-09-19 1997-12-16 Actel Corporation Programmable logic module and architecture for field programmable gate array device
US6160420A (en) 1986-09-19 2000-12-12 Actel Corporation Programmable interconnect architecture
US5432441A (en) * 1986-09-19 1995-07-11 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5341092A (en) * 1986-09-19 1994-08-23 Actel Corporation Testability architecture and techniques for programmable interconnect architecture
US5089973A (en) * 1986-11-07 1992-02-18 Apple Computer Inc. Programmable logic cell and array
US5019736A (en) * 1986-11-07 1991-05-28 Concurrent Logic, Inc. Programmable logic cell and array
US4963770A (en) * 1987-11-20 1990-10-16 Kawasaki Steel Corporation Programmable logic device
US5056053A (en) * 1988-02-11 1991-10-08 The Mitre Corporation Algebraic transform machine
US4982114A (en) * 1988-04-27 1991-01-01 Hitachi, Ltd. Semiconductor logic device having two-dimensional logic arrays and logic cell chains alternately arranged
US5590349A (en) * 1988-07-11 1996-12-31 Logic Devices, Inc. Real time programmable signal processor architecture
US6202197B1 (en) 1988-07-11 2001-03-13 Logic Devices Incorporated Programmable digital signal processor integrated circuit device and method for designing custom circuits from same
US5068823A (en) * 1988-07-11 1991-11-26 Star Semiconductor Corporation Programmable integrated circuit using topological and parametric data to selectively connect and configure different high level functional blocks thereof
US5003200A (en) * 1988-09-20 1991-03-26 Kawasaki Steel Corporation Programmable logic device having programmable wiring for connecting adjacent programmable logic elements through a single switch station
US5796623A (en) * 1988-10-05 1998-08-18 Quickturn Design Systems, Inc. Apparatus and method for performing computations with electrically reconfigurable logic devices
US5734581A (en) * 1988-10-05 1998-03-31 Quickturn Design Systems, Inc. Method for implementing tri-state nets in a logic emulation system
US5448496A (en) * 1988-10-05 1995-09-05 Quickturn Design Systems, Inc. Partial crossbar interconnect architecture for reconfigurably connecting multiple reprogrammable logic devices in a logic emulation system
US5812414A (en) * 1988-10-05 1998-09-22 Quickturn Design Systems, Inc. Method for performing simulation using a hardware logic emulation system
US5036473A (en) * 1988-10-05 1991-07-30 Mentor Graphics Corporation Method of using electronically reconfigurable logic circuits
US5452231A (en) * 1988-10-05 1995-09-19 Quickturn Design Systems, Inc. Hierarchically connected reconfigurable logic assembly
US5657241A (en) * 1988-10-05 1997-08-12 Quickturn Design Systems, Inc. Routing methods for use in a logic emulation system
US5612891A (en) * 1988-10-05 1997-03-18 Quickturn Design Systems, Inc. Hardware logic emulation system with memory capability
US6377911B1 (en) 1988-12-02 2002-04-23 Quickturn Design Systems, Inc. Apparatus for emulation of electronic hardware system
US5963735A (en) * 1988-12-02 1999-10-05 Quickturn Design Systems, Inc. Hardware logic emulation system
US5329470A (en) * 1988-12-02 1994-07-12 Quickturn Systems, Inc. Reconfigurable hardware emulation system
US6842729B2 (en) 1988-12-02 2005-01-11 Quickturn Design Systems, Inc. Apparatus for emulation of electronic systems
US5477475A (en) * 1988-12-02 1995-12-19 Quickturn Design Systems, Inc. Method for emulating a circuit design using an electrically reconfigurable hardware emulation apparatus
US5644515A (en) * 1988-12-02 1997-07-01 Quickturn Design Systems, Inc. Hardware logic emulation system capable of probing internal nodes in a circuit design undergoing emulation
US5109353A (en) * 1988-12-02 1992-04-28 Quickturn Systems, Incorporated Apparatus for emulation of electronic hardware system
US5001368A (en) * 1988-12-09 1991-03-19 Pilkington Micro-Electronics Limited Configurable logic array
US5185706A (en) * 1989-08-15 1993-02-09 Advanced Micro Devices, Inc. Programmable gate array with logic cells having configurable output enable
US5644496A (en) * 1989-08-15 1997-07-01 Advanced Micro Devices, Inc. Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses
US5255203A (en) * 1989-08-15 1993-10-19 Advanced Micro Devices, Inc. Interconnect structure for programmable logic device
US5359536A (en) * 1989-08-15 1994-10-25 Advanced Micro Devices, Inc. Programmable gate array with improved interconnect structure, input/output structure and configurable logic block
US5740069A (en) * 1989-08-15 1998-04-14 Advanced Micro Devices, Inc. Logic device (PLD) having direct connections between configurable logic blocks (CLBs) and configurable input/output blocks (IOBs)
US6150199A (en) * 1989-09-07 2000-11-21 Quicklogic Corporation Method for fabrication of programmable interconnect structure
US5717230A (en) * 1989-09-07 1998-02-10 Quicklogic Corporation Field programmable gate array having reproducible metal-to-metal amorphous silicon antifuses
US5780919A (en) * 1989-09-07 1998-07-14 Quicklogic Corporation Electrically programmable interconnect structure having a PECVD amorphous silicon element
US5502315A (en) * 1989-09-07 1996-03-26 Quicklogic Corporation Electrically programmable interconnect structure having a PECVD amorphous silicon element
US20020100010A1 (en) * 1989-09-20 2002-07-25 Aptix Corporation Field programmable printed circuit board
US5400262A (en) * 1989-09-20 1995-03-21 Aptix Corporation Universal interconnect matrix array
US5377124A (en) * 1989-09-20 1994-12-27 Aptix Corporation Field programmable printed circuit board
US20010009032A1 (en) * 1989-09-20 2001-07-19 Mohsen Amr M. Structure having multiple levels of programmable integrated circuits for interconnecting electronic components
US5544069A (en) * 1989-09-20 1996-08-06 Aptix Corporation Structure having different levels of programmable integrated circuits interconnected through bus lines for interconnecting electronic components
WO1991007015A1 (en) * 1989-10-25 1991-05-16 Concurrent Logic, Inc. Programmable logic cell and array
US5260881A (en) * 1989-10-30 1993-11-09 Advanced Micro Devices, Inc. Programmable gate array with improved configurable logic block
US5448493A (en) * 1989-12-20 1995-09-05 Xilinx, Inc. Structure and method for manually controlling automatic configuration in an integrated circuit logic block array
WO1991013495A1 (en) * 1990-03-01 1991-09-05 Plus Logic, Inc. Programmable logic device with programmable inverters at input/output pads
US5128871A (en) * 1990-03-07 1992-07-07 Advanced Micro Devices, Inc. Apparatus and method for allocation of resoures in programmable logic devices
US5153463A (en) * 1990-04-11 1992-10-06 Kawasaki Steel Corporation Programmable logic device having a reduced switching matrix
US5614756A (en) * 1990-04-12 1997-03-25 Actel Corporation Metal-to-metal antifuse with conductive
US5780323A (en) * 1990-04-12 1998-07-14 Actel Corporation Fabrication method for metal-to-metal antifuses incorporating a tungsten via plug
US5440245A (en) * 1990-05-11 1995-08-08 Actel Corporation Logic module with configurable combinational and sequential blocks
US5781033A (en) * 1990-05-11 1998-07-14 Actel Corporation Logic module with configurable combinational and sequential blocks
US5610534A (en) * 1990-05-11 1997-03-11 Actel Corporation Logic module for a programmable logic device
US5073729A (en) * 1990-06-22 1991-12-17 Actel Corporation Segmented routing architecture
US5132571A (en) * 1990-08-01 1992-07-21 Actel Corporation Programmable interconnect architecture having interconnects disposed above function modules
US5371390A (en) * 1990-10-15 1994-12-06 Aptix Corporation Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
US6160276A (en) * 1990-10-15 2000-12-12 Aptix Corporation Double-sided programmable interconnect structure
US5973340A (en) * 1990-10-15 1999-10-26 Aptix Corporation Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
US5654564A (en) * 1990-10-15 1997-08-05 Aptix Corporation Interconnect structure with programmable IC for interconnecting electronic components, including circuitry for controlling programmable IC
US5504354A (en) * 1990-10-15 1996-04-02 Aptix Corporation Interconnect substrate with circuits for field-programmability and testing of multichip modules and hybrid circuits
US5218240A (en) * 1990-11-02 1993-06-08 Concurrent Logic, Inc. Programmable logic cell and array with bus repeaters
US5245227A (en) * 1990-11-02 1993-09-14 Atmel Corporation Versatile programmable logic cell for use in configurable logic arrays
US5144166A (en) * 1990-11-02 1992-09-01 Concurrent Logic, Inc. Programmable logic cell and array
US5493147A (en) * 1991-01-17 1996-02-20 Crosspoint Solutions, Inc. Antifuse circuit structure for use in a field programmable gate array and method of manufacture thereof
US5384481A (en) * 1991-01-17 1995-01-24 Crosspoint Solutions, Inc. Antifuse circuit structure for use in a field programmable gate array and method of manufacture thereof
US5166556A (en) * 1991-01-22 1992-11-24 Myson Technology, Inc. Programmable antifuse structure, process, logic cell and architecture for programmable integrated circuits
WO1992016053A1 (en) * 1991-03-06 1992-09-17 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5594364A (en) * 1991-03-06 1997-01-14 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5122685A (en) * 1991-03-06 1992-06-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5396127A (en) * 1991-03-06 1995-03-07 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5220213A (en) * 1991-03-06 1993-06-15 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5726586A (en) * 1991-03-06 1998-03-10 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5416367A (en) * 1991-03-06 1995-05-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5986468A (en) * 1991-03-06 1999-11-16 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5430390A (en) * 1991-03-06 1995-07-04 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5587669A (en) * 1991-03-06 1996-12-24 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US5280202A (en) * 1991-03-06 1994-01-18 Quicklogic Corporation Programmable application specific integrated circuit and logic cell therefor
US6078191A (en) * 1991-03-06 2000-06-20 Quicklogic Corporation Programmable application specific integrated circuit and logic cell
WO1992017001A1 (en) * 1991-03-18 1992-10-01 Crosspoint Solutions, Inc. A field programmable gate array
US5394103A (en) * 1991-03-18 1995-02-28 Crosspoint Solutions, Inc. Field programmable gate array
US5313119A (en) * 1991-03-18 1994-05-17 Crosspoint Solutions, Inc. Field programmable gate array
US5527745A (en) * 1991-03-20 1996-06-18 Crosspoint Solutions, Inc. Method of fabricating antifuses in an integrated circuit device and resulting structure
US5221865A (en) * 1991-06-21 1993-06-22 Crosspoint Solutions, Inc. Programmable input/output buffer circuit with test capability
WO1993005577A1 (en) * 1991-08-30 1993-03-18 Concurrent Logic, Inc. Programme logic cell and array
US5260610A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic element interconnections for programmable logic array integrated circuits
US5436575A (en) * 1991-09-03 1995-07-25 Altera Corporation Programmable logic array integrated circuits
US5883850A (en) * 1991-09-03 1999-03-16 Altera Corporation Programmable logic array integrated circuits
US5376844A (en) * 1991-09-03 1994-12-27 Altera Corporation Programmable logic device with multiplexer-based programmable interconnections
US6759870B2 (en) 1991-09-03 2004-07-06 Altera Corporation Programmable logic array integrated circuits
US5371422A (en) * 1991-09-03 1994-12-06 Altera Corporation Programmable logic device having multiplexers and demultiplexers randomly connected to global conductors for interconnections between logic elements
US5485103A (en) * 1991-09-03 1996-01-16 Altera Corporation Programmable logic array with local and global conductors
US5260611A (en) * 1991-09-03 1993-11-09 Altera Corporation Programmable logic array having local and long distance conductors
WO1993006559A1 (en) * 1991-09-23 1993-04-01 Aptix Corporation Universal interconnect matrix array
US5321322A (en) * 1991-11-27 1994-06-14 Aptix Corporation Programmable interconnect architecture without active devices
US5623501A (en) * 1991-12-03 1997-04-22 Crosspoint Solutions Inc. Preprogramming testing in a field programmable gate array
US5347519A (en) * 1991-12-03 1994-09-13 Crosspoint Solutions Inc. Preprogramming testing in a field programmable gate array
US5208491A (en) * 1992-01-07 1993-05-04 Washington Research Foundation Field programmable gate array
DE4211162A1 (en) * 1992-03-31 1993-10-07 Krone Ag Asic Prototyper
US5744979A (en) * 1992-07-23 1998-04-28 Xilinx, Inc. FPGA having logic cells configured by SRAM memory cells and interconnect configured by antifuses
US5561367A (en) * 1992-07-23 1996-10-01 Xilinx, Inc. Structure and method for testing wiring segments in an integrated circuit device
US5684980A (en) * 1992-07-29 1997-11-04 Virtual Computer Corporation FPGA virtual computer for executing a sequence of program instructions by successively reconfiguring a group of FPGA in response to those instructions
US5469109A (en) * 1992-08-17 1995-11-21 Quicklogic Corporation Method and apparatus for programming anti-fuse devices
US5294846A (en) * 1992-08-17 1994-03-15 Paivinen John O Method and apparatus for programming anti-fuse devices
US5341043A (en) * 1992-09-30 1994-08-23 Actel Corporation Series linear antifuse array
US5633806A (en) * 1992-10-12 1997-05-27 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit and method of designing same
US5483178A (en) * 1993-03-29 1996-01-09 Altera Corporation Programmable logic device with logic block outputs coupled to adjacent logic block output multiplexers
US5381058A (en) * 1993-05-21 1995-01-10 At&T Corp. FPGA having PFU with programmable output driver inputs
US20080265938A1 (en) * 1993-08-03 2008-10-30 Ting Benjamin S Architecture and interconnect scheme for programmable logic circuits
US7409664B2 (en) 1993-08-03 2008-08-05 Actel Corporation Architecture and interconnect scheme for programmable logic circuits
US20100073024A1 (en) * 1993-08-03 2010-03-25 Ting Benjamin S Architecture and interconnect scheme for programmable logic circuits
US7646218B2 (en) 1993-08-03 2010-01-12 Actel Corporation Architecture and interconnect scheme for programmable logic circuits
US8289047B2 (en) 1993-08-03 2012-10-16 Actel Corporation Architecture and interconnect scheme for programmable logic circuits
US20110050282A1 (en) * 1993-08-03 2011-03-03 Ting Benjamin S Architecture and interconnect scheme for programmable logic circuits
US20060095886A1 (en) * 1993-08-03 2006-05-04 Ting Beniamin S Architecture and interconnect scheme for programmable logic circuits
US5485031A (en) * 1993-11-22 1996-01-16 Actel Corporation Antifuse structure suitable for VLSI application
US6111302A (en) * 1993-11-22 2000-08-29 Actel Corporation Antifuse structure suitable for VLSI application
US5808351A (en) * 1994-02-08 1998-09-15 Prolinx Labs Corporation Programmable/reprogramable structure using fuses and antifuses
US5537108A (en) * 1994-02-08 1996-07-16 Prolinx Labs Corporation Method and structure for programming fuses
US5726482A (en) * 1994-02-08 1998-03-10 Prolinx Labs Corporation Device-under-test card for a burn-in board
US5572409A (en) * 1994-02-08 1996-11-05 Prolinx Labs Corporation Apparatus including a programmable socket adapter for coupling an electronic component to a component socket on a printed circuit board
US5917229A (en) * 1994-02-08 1999-06-29 Prolinx Labs Corporation Programmable/reprogrammable printed circuit board using fuse and/or antifuse as interconnect
US5813881A (en) * 1994-02-08 1998-09-29 Prolinx Labs Corporation Programmable cable and cable adapter using fuses and antifuses
US5834824A (en) * 1994-02-08 1998-11-10 Prolinx Labs Corporation Use of conductive particles in a nonconductive body as an integrated circuit antifuse
US5884066A (en) * 1994-02-16 1999-03-16 Quickturn Design Systems, Inc. Method and apparatus for a trace buffer in an emulation system
US5682106A (en) * 1994-05-20 1997-10-28 Quicklogic Corporation Logic module for field programmable gate array
US5892684A (en) * 1994-05-20 1999-04-06 Quicklogic Corporation Programmable application specific integrated circuit employing antifuses and methods therefor
US5477167A (en) * 1994-05-20 1995-12-19 Quicklogic Corporation Programmable application specific integrated circuit using logic circuits to program antifuses therein
US5424655A (en) * 1994-05-20 1995-06-13 Quicklogic Corporation Programmable application specific integrated circuit employing antifuses and methods therefor
US5654649A (en) * 1994-05-20 1997-08-05 Quicklogic Corporation Programmable application specific integrated circuit employing antifuses and methods therefor
US5629636A (en) * 1994-10-19 1997-05-13 Crosspoint Solutions, Inc. Ram-logic tile for field programmable gate arrays
US5465055A (en) * 1994-10-19 1995-11-07 Crosspoint Solutions, Inc. RAM-logic tile for field programmable gate arrays
US5552720A (en) * 1994-12-01 1996-09-03 Quicklogic Corporation Method for simultaneous programming of multiple antifuses
US5600262A (en) * 1994-12-01 1997-02-04 Quicklogic Corporation Integrated circuit facilitating simultaneous programming of multiple antifuses
US5495181A (en) * 1994-12-01 1996-02-27 Quicklogic Corporation Integrated circuit facilitating simultaneous programming of multiple antifuses
US5962815A (en) * 1995-01-18 1999-10-05 Prolinx Labs Corporation Antifuse interconnect between two conducting layers of a printed circuit board
US5906043A (en) * 1995-01-18 1999-05-25 Prolinx Labs Corporation Programmable/reprogrammable structure using fuses and antifuses
US5592106A (en) * 1995-05-17 1997-01-07 Altera Corporation Programmable logic array integrated circuits with interconnection conductors of overlapping extent
US5906042A (en) * 1995-10-04 1999-05-25 Prolinx Labs Corporation Method and structure to interconnect traces of two conductive layers in a printed circuit board
US5777489A (en) * 1995-10-13 1998-07-07 Mentor Graphics Corporation Field programmable gate array with integrated debugging facilities
US5907697A (en) * 1995-10-13 1999-05-25 Mentor Graphics Corporation Emulation system having a scalable multi-level multi-stage hybrid programmable interconnect network
US20040178820A1 (en) * 1995-10-13 2004-09-16 Jean Barbier Reconfigurable integrated circuit with integrated debugging facilities and scalable programmable interconnect
US6717433B2 (en) 1995-10-13 2004-04-06 Jean Barbier Reconfigurable integrated circuit with integrated debugging facilities and scalable programmable interconnect
US5767575A (en) * 1995-10-17 1998-06-16 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US5990502A (en) * 1995-12-29 1999-11-23 Lsi Logic Corporation High density gate array cell architecture with metallization routing tracks having a variable pitch
US5744980A (en) * 1996-02-16 1998-04-28 Actel Corporation Flexible, high-performance static RAM architecture for field-programmable gate arrays
US5872338A (en) * 1996-04-10 1999-02-16 Prolinx Labs Corporation Multilayer board having insulating isolation rings
US5987744A (en) * 1996-04-10 1999-11-23 Prolinx Labs Corporation Method for supporting one or more electronic components
US7830173B2 (en) 1996-09-04 2010-11-09 Actel Corporation Method and apparatus for universal program controlled bus architecture
US20110043248A1 (en) * 1996-09-04 2011-02-24 Pani Peter M Method and apparatus for universal program controlled bus architecture
US7915918B2 (en) 1996-09-04 2011-03-29 Actel Corporation Method and apparatus for universal program controlled bus architecture
US20060202716A1 (en) * 1996-09-04 2006-09-14 Pani Peter M Method and apparatus for universal program controlled bus architecture
US20080191739A1 (en) * 1996-09-04 2008-08-14 Pani Peter M Method and apparatus for universal program controlled bus architecture
US7382156B2 (en) 1996-09-04 2008-06-03 Actel Corporation Method and apparatus for universal program controlled bus architecture
US5841967A (en) * 1996-10-17 1998-11-24 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US6058492A (en) * 1996-10-17 2000-05-02 Quickturn Design Systems, Inc. Method and apparatus for design verification using emulation and simulation
US5936426A (en) * 1997-02-03 1999-08-10 Actel Corporation Logic function module for field programmable array
US6014038A (en) * 1997-03-21 2000-01-11 Lightspeed Semiconductor Corporation Function block architecture for gate array
US5977574A (en) * 1997-03-28 1999-11-02 Lsi Logic Corporation High density gate array cell architecture with sharing of well taps between cells
US6389379B1 (en) 1997-05-02 2002-05-14 Axis Systems, Inc. Converification system and method
US6026230A (en) * 1997-05-02 2000-02-15 Axis Systems, Inc. Memory simulation system and method
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6421251B1 (en) 1997-05-02 2002-07-16 Axis Systems Inc Array board interconnect system and method
US6134516A (en) * 1997-05-02 2000-10-17 Axis Systems, Inc. Simulation server system and method
US6321366B1 (en) 1997-05-02 2001-11-20 Axis Systems, Inc. Timing-insensitive glitch-free logic system and method
US6377912B1 (en) 1997-05-30 2002-04-23 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5960191A (en) * 1997-05-30 1999-09-28 Quickturn Design Systems, Inc. Emulation system with time-multiplexed interconnect
US5970240A (en) * 1997-06-25 1999-10-19 Quickturn Design Systems, Inc. Method and apparatus for configurable memory emulation
US9092595B2 (en) 1997-10-08 2015-07-28 Pact Xpp Technologies Ag Multiprocessor having associated RAM units
US6611932B2 (en) 1997-12-05 2003-08-26 Lightspeed Semiconductor Corporation Method and apparatus for controlling and observing data in a logic block-based ASIC
US6223313B1 (en) 1997-12-05 2001-04-24 Lightspeed Semiconductor Corporation Method and apparatus for controlling and observing data in a logic block-based asic
US6034427A (en) * 1998-01-28 2000-03-07 Prolinx Labs Corporation Ball grid array structure and method for packaging an integrated circuit chip
US9690747B2 (en) 1999-06-10 2017-06-27 PACT XPP Technologies, AG Configurable logic integrated circuit having a multidimensional structure of configurable elements
US9552047B2 (en) 2001-03-05 2017-01-24 Pact Xpp Technologies Ag Multiprocessor having runtime adjustable clock and clock dependent power supply
US9436631B2 (en) 2001-03-05 2016-09-06 Pact Xpp Technologies Ag Chip including memory element storing higher level memory data on a page by page basis
US9250908B2 (en) 2001-03-05 2016-02-02 Pact Xpp Technologies Ag Multi-processor bus and cache interconnection system
US9141390B2 (en) 2001-03-05 2015-09-22 Pact Xpp Technologies Ag Method of processing data with an array of data processors according to application ID
US9037807B2 (en) 2001-03-05 2015-05-19 Pact Xpp Technologies Ag Processor arrangement on a chip including data processing, memory, and interface elements
US9075605B2 (en) 2001-03-05 2015-07-07 Pact Xpp Technologies Ag Methods and devices for treating and processing data
US6696856B1 (en) 2001-10-30 2004-02-24 Lightspeed Semiconductor Corporation Function block architecture with variable drive strengths
US9170812B2 (en) 2002-03-21 2015-10-27 Pact Xpp Technologies Ag Data processing system having integrated pipelined array data processor
US9274984B2 (en) 2002-09-06 2016-03-01 Pact Xpp Technologies Ag Multi-processor with selectively interconnected memory units
US20080278678A1 (en) * 2003-10-09 2008-11-13 Howell Thomas A Eyeglasses with user monitoring
US7646630B2 (en) * 2004-11-08 2010-01-12 Ovonyx, Inc. Programmable matrix array with chalcogenide material
US20060097240A1 (en) * 2004-11-08 2006-05-11 Tyler Lowrey Programmable matrix array with chalcogenide material
US8438522B1 (en) 2008-09-24 2013-05-07 Iowa State University Research Foundation, Inc. Logic element architecture for generic logic chains in programmable devices
US8661394B1 (en) 2008-09-24 2014-02-25 Iowa State University Research Foundation, Inc. Depth-optimal mapping of logic chains in reconfigurable fabrics

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