US4725876A - Semiconductor device having at least two resistors with high resistance values - Google Patents

Semiconductor device having at least two resistors with high resistance values Download PDF

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US4725876A
US4725876A US06/867,422 US86742286A US4725876A US 4725876 A US4725876 A US 4725876A US 86742286 A US86742286 A US 86742286A US 4725876 A US4725876 A US 4725876A
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resistor
region
regions
ion
implanted
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Jun Kishi
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NEC Electronics Corp
NEC Corp
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Nippon Electric Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/0802—Resistors only

Definitions

  • the present invention relates to a semiconductor device, and more particularly to a resistor having a high resistance value in a monolithic integrated circuit (hereinafter called a "monolithic IC").
  • a resistor in a monolithic IC for instance, in a bipolar monolithic IC comprising circuit elements formed in an N-type epitaxial layer on a P-type substrate, is normally constructed of a P-type strip-shaped region formed in the N-type epitaxial layer simultaneously with formation of a base region of a NPN transistor.
  • the sheet resistance and junction depth of the strip-shaped region are uniquely determined depending upon a characteristic of the NPN transistor. Therefore, a predetermined resistance value is realized by adjusting the width and/or length of the strip-shaped region.
  • the sheet resistance of the strip-shaped region is low. For this reason, in order to obtain a resistor having a high resistance value, the length of the strip-shaped region would become very long. As a result, the area occupied by the strip-shaped region would become very large.
  • the so-called pinch resistor and ion-implanted resistor have been used. These resistors have been employed in MOS-type monolithic ICs.
  • the pinch resistor is such that an N + -type region is formed on the P-type strip-shaped resistor region so as to overlap with a part of the P-type strip-shaped resistor region and to connect with the N-type region in which the P-type resistor region has been formed, and electrical connection is provided at both ends of the strip-shaped resistor region.
  • the thickness of the strip-shaped region is partially reduced by the overlapping N + -type region, and moreover, the portion having a relatively high impurity concentration along the surface of the strip-shaped region does not substantially contribute to the determination of the resistance value.
  • the resistance value is substantially determined by the sheet resistance of a P-type portion under the overlapping N + -type region and the width and length of this overlapped P-type portion.
  • the sheet resistance of the P-type portion is increased by about one order of magnitude.
  • the ion-implanted resistor is constituted by an ion-implanted region having a high sheet resistance, i.e., by a strip-shaped region formed by implanting P-type impurity ions into a surface portion of an N-type region at a low concentration. Since the sheet resistance of the ion-implanted region is relatively high, good ohmic contact between an electrode and the ion-implanted region cannot be realized. Hence, contact regions having a low sheet resistance are formed at both ends of the strip-shaped region, and electrodes for the ion-implanted resistor are formed on the contact regions.
  • the resistance value of the ion-implanted resistor is substantially determined by the portion of the ion-implanted region that is located between the contact regions.
  • the formation of the ion-implanted region by the ion-implantation of an impurity is effected before the formation of the electrodes but after active regions for circuit elements have been formed. If heat treatments for forming the active regions are effected after ion-implantation of impurities, the implanted impurities would be rediffused by the heat treatments, so that a desired high sheet resistance could not be obtained.
  • a thickness of a surface insulating film on the ion-implanted region is extremely thin as compared to that of the surface insulating film on its surrounding region which has been formed through several heat treatments included in the diffusion steps effected before the ion implantation step.
  • the difference in thickness between the surface insulating film on the ion-implanted region and that on its surrounding region is considerably large. For this reason, in the event that an interconnection conductor passes over an ion-implanted resistor, it may possibly occur thsat the interconnection conductor is broken at the steps of the insulating films.
  • a semiconductor region is additionally formed simultaneously with the contact regions in the ion-implanted resistor.
  • the interconnection conductor crosses above this semiconductor region, the insulating film on which is thick during the subsequent steps including the heat treatment. Since this semiconductor region has a low sheet resistance, the ion-implanted region is elongated by the length corresponding to the length of that semiconductor region. Consequently, an ion-implanted resistor over which an interconnection conductor passes includes at least two ion-implanted resistor regions, two contact regions and a semiconductor region having a low sheet resistance for connecting the two ion-implanted resistor regions to each other. This semiconductor region is referred to, hereinafter, as a connecting region.
  • pinch resistors and ion-implanted resistors are used as resistors in a circuit such as, for example, a differential amplifier, a flip-flop or resistance divider circuit which requires a precise resistance ratio, a current flowing through the circuit could be reduced for a low power consumption, and further the design of a desired heat dissipation capacity of a package for sealing a semiconductor chip could become easy.
  • the expansion of contact regions and the connecting region in the ion-implanted resistor undesirably decreases the length of the ion-implanted resistor region between them, so that the resistance value of the ion-implanted resistor becomes lower.
  • the intended ratio is one, it is difficult to form two resistors in a congruent shape desired from the point of view of a pattern layout including transistors and other elements, and it is impossible to realize the ratio of one with two resistors of different configurations.
  • Another object of the present invention is to provide a semiconductor device in which a resistance ratio between resistors having different configurations can be precisely achieved.
  • a semiconductor device comprises first and second resistor regions of one conductivity type formed in a semiconductor region of opposite conductivity type.
  • the first and second resistor regions have different configurations from each other.
  • the first resistor region includes a plurality of first portions which contribute to the determination of the resistance value of the first resistor
  • the second resistor region includes at least one second portion which contributes to the determination of the resistance value of the second resistor.
  • the ratio of the number (two or more) of the first portions to the number (one or more) of the second portions is made identical to the intended ratio of the resistance value of the first resistor to the second resistor. It is preferable that the first and second resistor regions have the same width.
  • the width of the respective first portions is the same and substantially equal to the width of the at least one second portion, and that the ratio of the sum of the lengths of all the first portions to the total length of the at least one second portion is made equal to the intended resistance ratio of the first and second resistors.
  • a semiconductor device in the case where the first and second resistors are pinch resistors, a semiconductor device according to the present invention further comprises a plurality of third semiconductor regions of the opposite conductivity type overlapping the respective first portions and at least one fourth semiconductor region overlapping the second portion. Consequently, the first and second portions in the first and second resistor regions are pinched between the common semiconductor region and the third and fourth semiconductor regions, respectively.
  • the first and second resistors are ion-implanted resistors
  • the first and second portions are the portions in the first and second resistor regions having an inherent sheet resistance obtained by ion implantation, respectively, located between two of the contact regions and connection region.
  • two third semiconductor regions are provided in the case of pinch resistors, while in the case of ion-implanted resistors there are two portions in the first resistor region having the inherent sheet resistance obtained by ion implantation and located between contact regions and a connecting region.
  • the two first portions in the pinch resistors are connected by the portion in the first resistor region on which the third semiconductor region is not formed, while the two first portions in the ion-implanted resistors are connected by the portion (i.e. a connecting region) in the first resistor region having a sheet resistance lower than that obtained by the ion implantation.
  • the portion for connecting the two first portions to each other does not substantially contribute to the determination of the resistance value of the first resistor, because it has a considerably small sheet resistance as compared to that of the first portions.
  • the ratio of the number of the first portions to that of the second portion or portions is determined so as to coincide with the intended ratio of the resistance value of the first resistor to that of the second resistor. For instance, if the resistsance ratio is 2, then the ratio of the number of first portions to that of the second portion or portions is also chosen to be 2. Accordingly, in the case of pinch resistors, the ratio of the error caused by the expansion of the third semiconductor regions in the first resistor to that caused by the expansion of the fourth semiconductor region in the second resistor becomes identical to the resistance ratio of the first resistor to the second resistor. In other words, the resistance ratio between the pinch resistors can be precisely obtained.
  • the ratio of the error caused by the expansions of the contact regions and the connecting region in the first resistor to that caused by the expansion of the contact regions and the connecting region in the second resistor becomes identical to the resistance ratio of the first resistor to the second resistor, so that the resistance ratio between the ion-implanted resistors can be precisely achieved. Therefore, the pinch resistors or ion-implanted resistors according to the present invention can be used as the resistors in a circuit which requires a precise resistance ratio. As a result, the reduction of a circuit current can be achieved, and freedom in the design of a package having a desired heat dissipation capacity can also be enhanced.
  • FIG. 1 is a plan view showing two pinch resistors formed in accordance with the prior art technique aiming at a resistance ratio of 1:1;
  • FIG. 2 is a plan view showing two ion-implanted resistors formed in accordance with the prior art technique aiming at a resistance ratio of 1:1;
  • FIGS. 3 and 4 are plan views showing two pinch resistors and two ion-implanted resistors, respectively, having a precise resistance ratio of 1:1 which can be formed in accordance with the prior art technique;
  • FIGS. 5 and 6 are plan views demonstrating the principle of the present invention applied to the two resistors shown in FIGS. 1 and 2, respectively;
  • FIG. 7 is a plan view showing a first preferred embodiment of the present invention.
  • FIGS. 8, 9 and 10 are cross-section views taken along lines A-A', B-B' and C-C' in FIG. 7, respectively;
  • FIG. 11 is a plan view showing a second preferred embodiment of the present invention.
  • FIG. 12 is a plan view showing a third preferred embodiment of the present invention.
  • FIGS. 13, 14 and 15 are cross-section views taken along lines A-A' B-B' and C-C' in FIG. 12, respectively;
  • FIGS. 16, 17, 18 and 19 are plan views showing fourth, fifth, sixth and seventh preferred embodiments of the present invention, respectively.
  • FIG. 1 shows two pinch resistors R 1 and R 2 which have been produced in accordance with the prior art technique aiming at a resistance ratio of 1:1.
  • the pinch resistors R 1 and R 2 are produced by forming, for instance, P-type diffused layers 2 and 5 in an N-type semiconductor layer and further forming N + -type diffused layers 3 and 6 so as to partly overlap with the diffused layers 2 and 5, respectively. Both end portions of the diffused layers 2 and 5 are broadened, and contact windows 4 and 7 for electrodes are formed on the broadened portions.
  • an IC typically includes a great number of circuit elements such as transistors and diodes, together with the pinch resistors R 1 and R 2 , with all of the elements and pinch resistors being formed on the same substrate. Accordingly, a limited area on the substrate is allotted to the resistor R 1 and another limited area is allotted to the resistor R 2 , both surrounded by other circuit elements.
  • the two areas allotted for the resistors R 1 and R 2 will most often be of different shapes and sizes, and it only rarely happens that the allotted areas have the same shape.
  • the P-type diffused layer 2 in the resistor R 1 is formed in an S-shape
  • the P-type diffused layer 5 in the resistor R 2 is formed in a W-shape.
  • the N + -type diffused layer 3 overlaps with three portions of the P-type diffused layer 2, and the N + -type diffused layer 6 overlaps four portions of the P-type diffused layer 5. Since P-type portions 8 and 9 pinched between the N + -type diffused layers 3 and 6 and the N-type semiconductor layer have a high sheet resistance, these portions essentially determine the resistance values of resistors R 1 and R 2 .
  • the portions of the P-type diffused layers 2 and 5 other than the P-type portions 8 and 9 do not substantially contribute to the resistance values of the resistors R 1 and R 2 due to their low sheet resistances.
  • the resistance value of the resistor R 1 is substantially determined by the four P-type portions 9.
  • the diffused layers take the configurations, as indicated by the chain line contours 2', 5', 3' and 6', after impurities have been diffused, although they are designed to have configurations as shown in solid line contours 2, 5, 3 and 6 in a mask pattern.
  • the configurations of the diffused layers are, in practice, enlarged as compared to the designed configurations because of the lateral diffusion of the impurities.
  • the impurity concentration of the N + -type diffused layers 3 and 6 is high, and therefore the lateral enlargement of the N + -type diffused layers 3 and 6 is larger than that of layers 2 and 5.
  • the inventor has thus considered and analyzed the resistance ratio between the pinch resistors R 1 and R 2 having the aforementioned configurations, as detailed below.
  • ⁇ PINCH represents the sheet resistance of a P-type portion pinched between two N-type layers
  • W and L represent the width and length on a mask pattern of the P-type portion, respectively
  • ⁇ W and ⁇ L represent increments of the width W and the length L caused by the lateral diffusion of the impurities, respectively.
  • the ⁇ W and ⁇ L have a positive sign due to the expansion of the upper N + -type layer as well as the expansion of the P-type layer.
  • L 1 , L 2 , L 3 lengths of the P-type portions 8 on a mask
  • ⁇ L 1 , ⁇ L 2 , ⁇ L 3 increments of lengths of the P-type portions 8 by the expansion of the N + -type layer 3;
  • W the width of the P-type portion 8 on a mask
  • ⁇ W the increment of the width of the P-type portion 8 by the expansion of the P-type layer 2;
  • ⁇ a sum of the contact resistances of electrodes (not shown) connected to the layer 2 through the contact windows 4 and the resistances of the portions of the P-type diffused layer 2 on which the N + -type diffused layer 3 is not formed.
  • Equation-(2) The second term on the right side of Equation-(2) is negligibly small as compared to the first term on the right side. Hence, Equation-(2) can be reduced into the following equation: ##EQU3##
  • Equation-(6) the widths of the resistor sections are equal to each other: ##EQU7## where n: the number of the overlapped portions between the N + -type diffused layer 3 and the P-type diffused layer 2 in the resistor R 1 , that is, the number of P-type portions 8;
  • n' the number of the overlapped portions between the N + -type diffused layer 6 and the P-type diffused layer 5 in the resistor R 2 , that is, the number of the P-type portions 9;
  • ⁇ the ratio of the total length of the P-type portions 9 in the resistor R 2 to that of the P-type portions 8 in the resistor R 1 .
  • the inventor had discovered that, since the ratio between the numbers n and n' differs from an intended resistance ratio, that is, from the total length ratio ⁇ of the P-type portions, the resistance ratio between the resistors R 1 and R 2 given by Equation-(6) would deviate from the intended resistance ratio. Therefore, in order to eliminate the deviation of the resistance ratio between the resistors R 1 and R 2 , it is necessary to select the numbers n and n' of the overlapped portions in Equation-(6) in accordance with the resistance ratio. In the case where the resistance ratio is one, the number n should be selected to equal the number n'.
  • the P-type diffused layer 2 was formed in the same W-shape as the P-type diffused layer 5 or the P-type diffused layer 5 was formed in the same S-shape as the P-type diffused layer 2.
  • the resistor Rhd 1 and the resistor R 2 were formed in congruent configurations.
  • the resistance ratio is larger than 1 or the configurations between two resistors are different as shown in FIG. 2, a precise resistance ratio could not be realized due to the different configurations of the two resistors.
  • the ion-implanted resistors have P-type ion-implanted regions 11 and 15 having a high sheet resistance which are formed in an N-type layer through the ion-implantation of P-type impurities, and further have P-type contact regions 12 and 16 having a high impurity concentration which are formed at both ends of the P-type ion-implanted regions 11 and 15 simultaneously with formation of a base region, respectively.
  • the resistors R 3 and R 4 are formed in an S-shape and in a U-shape, respectively.
  • the resistor configurations shown in FIG. 2. are suitable for the case where interconnection conductors have to pass over the ion-implanted resistors R 3 and R 4 due to wiring pattern considerations. More particularly, the ion-implanted resistors R 3 and R 4 are provided with respective regions 13 and 17 having a low sheet resistance. The interconnection conductor passing over the resistor R 3 crosses over the region 13, while the interconnection conductor passing over the resistor R 4 crosses over the region 17. Since no wiring crosses over a region 14 in the resistor R 3 , it will be seen that this region 14 may be formed as an ion-implanted region connected to the ion-implanted regions 11.
  • the region 14 formed simultaneously with the region 13 is provided in order that the number of the bent corners in the resistor R 3 is also zero.
  • the resistance value of the resistor R 3 is substantially determined by three ion-implanted regions 11, while that of the resistor R 4 is substantially determined by two ion-implanted regions 15.
  • the regions 12, 13, 14, 16 and 17 are formed simultaneously. Further, in order to control the sheet resistances of the ion-implanted regions 11 and 15, the regions 12, 13, 14, 16 and 17 are formed earlier than the ion-implanted regions 11 and 15.
  • Contact windows 18 and 19 are provided in surface insulating films (not shown) on the contact regions 12 and 16, respectively.
  • the respective regions take the configurations, as indicated by chain line contours 12', 13', 14', 16' and 17', after impurities have been diffused, although they are designed to have configurations as shown in solid line contours 12, 13, 14, 16 and 17 in a mask pattern.
  • solid line contours of the regions 11 and 15 indicate the configurations on a mask pattern to be used for ion-implantation
  • chain line contours 11' and 15' indicate the configurations of the ion-implanted regions actually produced by the annealing treatment for activating the ion-implanted impurities. Since the impurity concentration in regions 12, 13, 14, 16 and 17 is high, these regions expand more than the ion-implanted regions 11 and 15.
  • ⁇ S represents a sheet resistance of an ion-implanted region
  • L and W represent the length and a width of the ion-implanted region on a mask pattern
  • ⁇ W represents an increment of the width of the ion implanted region caused by the annealing treatment
  • ⁇ L represents a decrement of the length of the ion-implanted region caused by expansion of the contact regions 12 and 16 and the regions 13, 14 and 17, whereby the actual length of the ion-implanted region is reduced.
  • ⁇ represents the sum of the contact resistances of electrodes (not shown) connected to contact regions 12 and 16 through the windows 18 and 19 and the resistances of the regions 13, 14, and 17.
  • Equation-(10) which represents the resistance ratio R 4 /R 3 between the resistors R 4 and R 3 : ##EQU10##
  • the inventor has found that, even if the respective resistors R 3 and R 4 are designed to have the same total resistor length L in order to precisely realize a resistance ratio of 1:1, the actual resistance is not 1:1 but includes an error due to the terms 3 ⁇ L and 2 ⁇ L in Equation-(10).
  • This is due to the fact that the ion-implanted regions 11 in the resistor R 3 are connected through two high concentration regions 13 and 14, whereas the ion-implanted regions 15 in the resistor R 4 are connected by a single high concentration region 17, and therefore the errors in the total resistor length L due to the lateral expansion of these high concentration regions 13, 14 and 17 are different between the two resistors R 3 and R 4 .
  • Equation-(10) n and n' represent the numbers of the ion-implanted regions 11 and 15, respectively, and ⁇ represents the ratio of the total length of all the ion-implanted regions 15 in the resistor R 4 to that of all the ion-implanted regions 11 in the resistor R 3 .
  • Equation-(11) From Equation-(11) the inventor has discovered that as the ratio between the numbers n and n' differs from an intended resistance ratio, that is, from the total length ratio ⁇ of the ion-implanted regions, the resistance ratio between the resistors R 3 and R 4 would deviate from the intended resistance ratio. Therefore, in order to eliminate the deviation of the resistance ratio between the resistors R 3 and R 4 in the case where the intended resistance ratio is one, it is necessary to select the numbers n and n' in Equation-(11) to be equal to each other.
  • the numbers of the ion-implanted regions 11 and 15 were equalized either by adding one ion-implanted region in one resistor or reducing one ion-implanted region in the other resistor, and also the numbers of bent corners of the ion-implanted regions in the respective resistors were equalized.
  • this measure taken in the prior art implies that the resistors R 3 and R 4 are formed in a congruent shape, resulting in a severe restriction in the pattern layout.
  • the shapes of two resistors are different as shown in FIG. 2 or a resistance ratio larger than 1 is required, it is absolutely impossible to realize a precise resistance ratio.
  • FIGS. 3 and 4 show the configurations of the two resistors.
  • FIG. 3 shows the pinch resistor
  • FIG. 4 shows the ion-implanted resistors.
  • FIG. 3 shows the pinch resistor
  • FIG. 4 shows the ion-implanted resistors.
  • FIG. 3 shows the pinch resistor
  • FIG. 4 shows the ion-implanted resistors.
  • such cases are actually rare, and it often occurs that an area allotted to one resistor is different in shape and size from that allotted to another resistor on the same IC chip, depending upon the layout of the other circuit elements surrounding the allotted resistor areas as described above.
  • the configuration of the pinch resistors must be different from each other with the lengths being equal to each other, if a resistance ratio of 1:1 is to be obtained, and an inaccurate resistance ratio has conventionally been obtained. Further, if the resistance ratio to be obtained is 1:2 or more, the configurations of the two resistors are inevitably different.
  • FIG. 5 shows the application of the present invention to two resistors R 1 and R 2 shown in FIG. 1.
  • reference symbols similar to those appearing in FIG. 1 designate like physical quantities and reference numerals similar to those appearing in FIG. 1 designate like component parts.
  • the number n of the P-type portions 8 pinched between the N-type epitaxial layer and the N + -type diffused layer 3 in the resistor R 1 ' is increased to 4 by modifying the shape of the N + -type diffused layer in the resistor R 1 ' without varying the shapes of the P-type diffused layers 2 and 5 in the resistors R 1 ' and R 2 '.
  • four P-type portions 8 determine the resistance value of the resistor R 1 ' like the resistor R 2 '.
  • the lengths L 2 ' and L 3 ' of two P-type portions 8 are chosen to be equal to the lengths L 2 and L 3 of the P-type portions 8 in FIG. 1, then the sum L'+L 8 of the lengths of other two P-type portions 8 is selected to be equal to the length L 1 in FIG. 1.
  • the numbers n and n' of the overlapped portions between the N + -type diffused layers 3 and 6 and the P-type diffused layers 2 and 5 in the resistors R 1 ' and R 2 ' are both equal to 4.
  • the resistance ratio R 2 '/R 1 ' between the resistors R 1 ' and R 2 ' in FIG. 5 is derived as follows: ##EQU12## In other words, a precise resistance ratio of one can be realized regardless of the shapes of the P-type diffused layers 2 and 5 and independently of lateral extension of the impurity diffusion.
  • FIG. 6 shows an application of the present invention to the two ion-implanted resistors R 3 and R 4 shown in FIG. 2.
  • reference numerals similar to those appearing in FIG. 2 designate like component parts.
  • the number n' of the ion-implanted regions which contribute to determination of the resistance value of the resistor R 4 ' is increased by 3 by additionally forming a P-type region 17' in one part of the left side ion-implanted region 15' in the resistor R 4 '.
  • the resistance ratio R 4 '/R 3 ' between the resistors R 3 ' and R 4 ' can be derived as follows: ##EQU13## In other words, even if the configurations of the ion-implanted regions are different, there are provided two resistors R 3 ' and R 4 ' having a precisely defined resistance ratio therebetween.
  • FIG. 7 is a plan view showing two pinch resistors R 10 and R 11 fabricated according to one preferred embodiment of the present invention. Cross-sectional views taken along lines A-A', B-B' and C-C' in FIG. 7 are shown in FIGS. 8, 9 and 10, respectively. These two resistors R 10 and R 11 are formed in a bipolar monolithic IC. More particularly, formed on a P-type substrate 30 is an N-type epitaxial layer 31 of 8.6 ⁇ to 9.7 ⁇ in thickness having a resistivity of 0.88 ohm-cm to 1.18 ohm-cm. The N-type epitaxial layer 31 is divided into a plurality of island regions by isolation regions 32.
  • a P-type impurity such as boron or the like is selectively diffused into one island region 31' simultaneously with the formation of base regions (not shown) of NPN transistors, and thereby P-type regions 33 and 33' are formed in the shapes shown in FIG. 7.
  • the P-type region 33 bends substantially at a right angle 6 times between the electrodes at both ends, while the P-type region 33' bends substantially at a right angle 4 times between the electrodes at both ends.
  • the regions 33 and 33' both have a depth of about 2.8 ⁇ and a sheet resistance of 150 to 250 ohm/.sub. ⁇ .
  • N + -type regions 34 and 34' are formed in the shapes shown in FIG.
  • the N-type impurity such as phosphorus or the like simultaneously with the formation of emitter regions (not shown) of the NPN transistors.
  • the depth of the regions 34 and 34' is 2.0 ⁇ and their sheet resistance is 2 to 10 ohm/.sub. ⁇ .
  • the P-type portions under the regions 34 and 34' have a depth of 0.8 ⁇ and a sheet resistance of 4 kohm/.sub. ⁇ . Since the N + -type region 34 in the resistor R 4 is formed in the shape shown in FIG. 7, the resistance value of the resistor R 10 is determined by the resistance of two P-type portions 33-1 and 33-2 pinched between the N + -type region 34 and the N-type epitaxial layer 31.
  • the length of the P-type portions 33-1 and 33-2 are represented by L 10 and L 11 , respectively. It is to be noted that the P-type portion 33-1 includes 4 bent corners, and the P-type portion 33-2 has no bent corner.
  • the resistor R 11 which is required to have a precisely defined resistance ratio of 1:1 with respect to the resistor R 10 having the above-described configuration, has its resistance value determined by the shape of the N + -type region 34' as will be described in the following.
  • the P-type portion 33-1 which determines the resistance value of the resistor R 10 in cooperation with the P-type portion 33-2 has four bent corners, and the P-type portion 33-2 has no bent corner. Therefore, it is preferable that the resistor R 11 also have four bent corners in the P-type portions determining its resistance value.
  • the shape of the N + -type region 34' is determined such that, in the resistor R 11 , a P-type portion 33'-1 pinched between the N + -type region 34' and the N + -type epitaxial layer 31, and which determines the resistance value of the resistor R 11 , also has four bent corners.
  • a desired resistance value of the resistor R 10 is realized by two P-type portions 33-1 and 33-2.
  • the N + -type region 34' is shaped so as to include a portion overlapping with the P-type region 33' and a portion not overlapping with the P-type region 33'.
  • two P-type portions 33'-1 and 33'-2 determine the resistance value of the resistor R 11 .
  • the resistance ratio R 11 /R 10 between the resistors R 10 and R 11 is derived as follows: ##EQU14## In other words, a precise resistance ratio of 1:1 can be realized regardless of the lateral diffusion of impurities in the N + -type regions 34 and 34'.
  • FIG. 11 A second preferred embodiment of the present invention is illustrated in FIG. 11.
  • the resistance value of a pinch resistor R 20 is designed to be twice as large as that of a pinch resistor R 21 .
  • the pinch resistors R 20 and R 21 are formed in an epitaxial layer 40.
  • the pinch resistor R 20 comprises a rectilinear P-type diffused layer 41 and a comb-shaped N + -type diffused layer 42 having 6 teeth intermittently overlapping with the surface of the P-type diffused layer 41.
  • Contact window 45 for electrodes are formed at both ends of the P-type diffused layer 41.
  • the pinch resistor R 21 comprises a P-type diffused layer 41' having 4 bent corners and a rectilinear N + -type diffused layer 42' overlapping with the surface of the P-type diffused layer 41' at 3 locations.
  • contact windows 46 for electrodes are formed at both ends of the P-type diffused layer 41'.
  • the total length of the six P-type portions overlapped with the N + -type region 42 is chosen to be twice as large as that of the three P-type portions overlapped with the N-type region 42'.
  • the illustrated embodiment provides a design of two pinch resistors R 20 and R 21 in the case where the P-type region 41 should have an elongated shape while the P-type region 41' should have an S-shape from the viewpoint of a desired pattern layout, and it is desired to select the resistance ratio between the resistors R 21 and R 20 to be 1:2.
  • the resistance ratio R 21 /R 20 of the resistor R 21 to the resistor R 20 is derived by substituting these parameters into Equation-(6) as follows: ##EQU15##
  • a resistance ratio between two ion-implanted resistors R 30 and R 31 is chosen to be 1:1.
  • Cross-section views taken along lines A-A', B-B' and C-C' in FIG. 12 are respectively shown in FIGS. 13, 14 and 15.
  • the two ion-implanted resistors R 30 and R 31 are formed in a bipolar monolithic IC. More particularly, formed on a P-type semiconductor substrate 50 is an N-type epitaxial layer 51, and the epitaxial layer 51 is divided into a plurality of island regions by an isolation region 52.
  • electrode contact regions 53 and a region 54 in the resistor R 30 Formed in one island region 51' are electrode contact regions 53 and a region 54 in the resistor R 30 , and electrode contact regions 53' and a region 57' in the resistor R 31 , by selectively diffusing a P-type impurity into the island region 51' simultaneously with the formation of base regions (not shown) of NPN transistors.
  • the depth of these regions is 2.8 ⁇ and the surface impurity concentration of these regions is 5 ⁇ 10 18 cm -3 .
  • a P-type impurity is selectively ion-implanted under an acceleration energy of 50 KeV and a dosage of 1 ⁇ 10 13 cm -2 and then annealed, so that ion-implanted regions 55 and 55' of the shapes shown in FIG. 12 can be formed.
  • the ion-implanted region 55 in the resistor R 30 extends from one contact region 53, then bends at a substantially right angle 4 times, and further is connected via the P-type region 54 to the other contact region 53.
  • the P-type region 54 is provided for the purpose of allowing an interconnection conductor to pass over the resistor R 30 .
  • the interconnection conductor crosses over the P-type region 54.
  • the resistance of the resistor R 30 is determined by two ion-implanted regions 55-1 and 55-2. It is to be noted that the ion-implanted region 55-1 has 4 bent corners, and the ion-implanted region 55-2 has no bent corner.
  • the ion-implanted region 55' in the resistor R 31 also includes 4 bent corners. Hence, fluctuations in the resistance ratio caused by a difference in the number of bent corners would not arise between the resistors R 30 and R 31 .
  • the resistance value of the resistor R 30 is determined by two ion-implanted regions 55-1 and 55-2, whereas that of the resistor R 31 is determined by the single ion-implanted region 55' if the region 57' is not provided, resulting in an inaccurate resistance ratio.
  • a P-type region 57 formed simultaneously with the P-type regions 53, 53' and 54 is provided in a part of the ion-implanted region 55'.
  • the resistance value of the resistor R 31 is determined equivalently by two ion-implanted regions 55'-1 and 55'-2.
  • FIG. 16 A fourth preferred embodiment of the present invention is illustrated in FIG. 16. From the viewpoint of a pattern layout, a resistor R 40 must have a rectilinear shape consisting of one ion-implanted region 60, while an ion-implanted resistor R 41 must be formed in an S-shape consisting of three ion-implanted regions 60' connected through two high concentration layers 62. Moreover, the resistance ratio R 41 /R 40 of the resistor R 40 is desired to be equal to 1/2. Since the resistance value of the resistor R 41 is determined by the three ion-implanted regions 60', the resistance value of the resistor R 40 should be determined by six ion-implanted regions in order to obtain a precise resistance ratio.
  • the resistor R 40 is twice as large as that of the three ion-implanted partial regions 60' in the resistor R 41 .
  • regions 63 and 64 are contact regions for electrodes formed simultaneously with P-type regions 61 and 62.
  • FIG. 17 Another preferred embodiment of the present invention in the case where the intended resistance ratio between two resistors is not an integral ratio, is illustrated in FIG. 17 and will be described in detail in the following.
  • the resistance ratio of two resistors R 50 and R 51 is selected to be 1.75.
  • the preferable shapes of the respective resistors R 50 and R 51 are shown in FIG. 17.
  • the resistor R 50 comprises two ion-implanted regions 60 connected to each other through a high concentration region 62, and each of the ion-implanted partial regions 60 is divided into two regions by a high concentration region 61.
  • the resistor R 50 has equivalently four ion-implanted regions 60.
  • the resistor R 51 comprises three ion-implanted partial regions 60' connected to each other through two high concentration regions 62', and two of the three ion-implanted partial regions 60' are divided into three regions by two high concentration regions 61'.
  • the resistor R 51 has equivalently seven ion-implanted regions 60'.
  • Equation-(11)" it can be seen that even in the case where the desired resistance ratio is not an integral ratio, the resistance can be realized with high precision.
  • the desired resistance ratio is 2.
  • This resistance ratio is realized by forming one resistor R 61 as a series connection of three ion-implanted regions via two high concentration layers 80 and the other resistor R 60 as a series-parallel connection of three ion-implanted partial regions 78 via a high concentration layer 77 and contact region 79, respectively. Contact regions 79 and 82 and connecting regions 77 and 80 are formed simultaneously.
  • the two resistors R 70 and R 71 to be fabricated are realized in the form of combinations of series-parallel connections according to the desired resistance ratio.
  • the resistor R 70 has five ion-implanted regions 90, one connecting region 91 and two contact regions 92.
  • the resistor R 71 has three ion-implanted regions 95, one connecting region and two contact regions 97.
  • the ratio can be realized with high precision regardless of the shapes of the resistors.
  • the ion-implanted resistors shown in FIGS. 17 to 19 can be substituted for pinch resistors by regarding ion-implanted regions as P-type portions pinched between two N-type layers.
  • the above-described principle of the present invention is also valid in the case where a P-type epitaxial layer is formed on an N-type semiconductor substrate.
  • the same analysis can be made by merely inverting the conductivity types of the respective regions.
  • the resistance ratio among more than three resistors is obtained accurately by using the present invention.
  • the resistors according to the present invention can also be used in a MOS-type monolithic IC.

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Integrated Circuits (AREA)
US06/867,422 1981-05-27 1986-05-15 Semiconductor device having at least two resistors with high resistance values Expired - Lifetime US4725876A (en)

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JP56-80408 1981-05-27
JP8040881A JPS57196558A (en) 1981-05-27 1981-05-27 Semiconductor integrated circuit device
JP16533881A JPS5867058A (ja) 1981-10-16 1981-10-16 半導体装置
JP56-165338 1981-10-16

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Cited By (10)

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US5047827A (en) * 1990-08-20 1991-09-10 Hughes Aircraft Company Integrated circuit resistor fabrication using focused ion beam
US5218225A (en) * 1990-03-30 1993-06-08 Dallas Semiconductor Corp. Thin-film resistor layout
US5321279A (en) * 1992-11-09 1994-06-14 Texas Instruments Incorporated Base ballasting
US6169310B1 (en) * 1998-12-03 2001-01-02 National Semiconductor Corporation Electrostatic discharge protection device
US6313515B1 (en) * 1998-07-16 2001-11-06 Nec Corporation Reference voltage supply circuit
US6784747B1 (en) 2003-03-20 2004-08-31 Analog Devices, Inc. Amplifier circuit
US6816015B2 (en) 2003-03-27 2004-11-09 Analog Devices, Inc. Amplifier circuit having a plurality of first and second base resistors
US20100072574A1 (en) * 2008-09-25 2010-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Manufacturing Method Thereof
US20150035097A1 (en) * 2011-05-09 2015-02-05 Kabushiki Kaisha Toshiba Semiconductor storage device
US11694742B2 (en) * 2018-09-28 2023-07-04 Micron Technology, Inc. Apparatuses and methods for internal voltage generating circuits

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GB1250988A (de) * 1969-08-14 1971-10-27
US3666995A (en) * 1969-05-10 1972-05-30 Philips Corp Integrated semiconductor device
US3906430A (en) * 1974-08-29 1975-09-16 Nippon Electric Co Matrix resistors for integrated circuit

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US3644802A (en) * 1968-05-31 1972-02-22 Rca Corp Ratio-compensated resistors for integrated circuit
US3771095A (en) * 1972-12-21 1973-11-06 Ibm Monolithic integrated circuit resistor design for optimum resistor tracking
US4161742A (en) * 1975-08-02 1979-07-17 Ferranti Limited Semiconductor devices with matched resistor portions

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US3666995A (en) * 1969-05-10 1972-05-30 Philips Corp Integrated semiconductor device
GB1250988A (de) * 1969-08-14 1971-10-27
US3906430A (en) * 1974-08-29 1975-09-16 Nippon Electric Co Matrix resistors for integrated circuit

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5218225A (en) * 1990-03-30 1993-06-08 Dallas Semiconductor Corp. Thin-film resistor layout
US5047827A (en) * 1990-08-20 1991-09-10 Hughes Aircraft Company Integrated circuit resistor fabrication using focused ion beam
US5321279A (en) * 1992-11-09 1994-06-14 Texas Instruments Incorporated Base ballasting
US6313515B1 (en) * 1998-07-16 2001-11-06 Nec Corporation Reference voltage supply circuit
US6511889B2 (en) 1998-07-16 2003-01-28 Nec Corporation Reference voltage supply circuit having reduced dispersion of an output voltage
US6169310B1 (en) * 1998-12-03 2001-01-02 National Semiconductor Corporation Electrostatic discharge protection device
US6784747B1 (en) 2003-03-20 2004-08-31 Analog Devices, Inc. Amplifier circuit
US6816015B2 (en) 2003-03-27 2004-11-09 Analog Devices, Inc. Amplifier circuit having a plurality of first and second base resistors
US20100072574A1 (en) * 2008-09-25 2010-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor Device and Manufacturing Method Thereof
US9960116B2 (en) * 2008-09-25 2018-05-01 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US20150035097A1 (en) * 2011-05-09 2015-02-05 Kabushiki Kaisha Toshiba Semiconductor storage device
US9064792B2 (en) * 2011-05-09 2015-06-23 Kabushiki Kaisha Toshiba Semiconductor storage device
US20150255506A1 (en) * 2011-05-09 2015-09-10 Kabushiki Kaisha Toshiba Semiconductor storage device
US9224786B2 (en) * 2011-05-09 2015-12-29 Kabushiki Kaisha Toshiba Semiconductor storage device
US9385160B2 (en) * 2011-05-09 2016-07-05 Kabushiki Kaisha Toshiba Semiconductor storage device
US11694742B2 (en) * 2018-09-28 2023-07-04 Micron Technology, Inc. Apparatuses and methods for internal voltage generating circuits

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EP0066263B2 (de) 1991-10-09
DE3273527D1 (en) 1986-11-06
EP0066263B1 (de) 1986-10-01

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