US4641188A - Progressive scan display system employing line and frame memories - Google Patents
Progressive scan display system employing line and frame memories Download PDFInfo
- Publication number
- US4641188A US4641188A US06/760,909 US76090985A US4641188A US 4641188 A US4641188 A US 4641188A US 76090985 A US76090985 A US 76090985A US 4641188 A US4641188 A US 4641188A
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- United States
- Prior art keywords
- signal
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- fields
- input signal
- video
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/14—Picture signal circuitry for video frequency region
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
- H04N7/012—Conversion between an interlaced and a progressive signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0135—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes
- H04N7/0147—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving interpolation processes the interpolation using an indication of film mode or an indication of a specific pattern, e.g. 3:2 pull-down pattern
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S348/00—Television
- Y10S348/911—Line doubler adapted for reproducing program originally from film, e.g. 24 frame per second
Definitions
- This invention relates to television display systems and particularly to receivers or monitors the type employing "progressive scanning" to reduce the visibility of vertical line structure of displayed images.
- Progressive scan television receivers have been proposed wherein the horizontal line rate is doubled and each line of video is displayed twice thereby providing a displayed image having twice the usual number of scan lines and thus reduced visibility of vertical line structure.
- each incoming horizontal line of video signal is stored in one of two line memorys. As one line is being stored in one memory the line previously stored in the other memory is recovered or "read" twice thereby providing two lines of time compressed video within one standard line interval.
- the memory output is applied to a display having a doubled horizontal sweep rate synchronized with readout of the memory thereby doubling the number of displayed lines of the video signal.
- field or frame memorys may be used to advantage in doubling the line rate in a progressive scan receiver.
- an entire frame of the video input signal is stored in a memory and recovered during one field interval for display thereby providing a full 525 lines of the incoming video signal during each field of the displayed signal.
- the advantage of such an arrangement is that the displayed signal is not subject to interpolation errors and preserves the full resolution of the transmitted signal.
- a disadvantage of such arrangements is that visual artifacts tend to be produced such as double images and serrated edge effects when there is motion in the scene due to field-to-field differences of the information stored in the memory.
- a solution to the problem of motion artifacts proposed by Powers is to apply the video input signal to a motion detector and utilize the output of the motion detector to automatically switch between frame store progressive scan processing and line store progressive scan processing when motion is present.
- Motion is detected in the Powers arrangement by comparing a number of currently received picture elements (pixels) with corresponding picture elements delayed by one field and summing the result of the comparisons to produce a weighed average. The average is compared against a minimum motion threshold value to generate the motion indicating output signal for selecting between line and frame type progressive scan processing.
- the present invention is directed to meeting the need for an adaptive progressive scan display system which automatically switches between frame store and line store type processing as a function of field-to-field motion and which is relatively tolerant of noise which may accompany the video input signal.
- a progressive scan display system embodying the invention includes and input means for receiving a video input signal of a given line rate and including an identification signal for signifying the presence in the video input signal of at least two sequential fields derived from a common scene.
- a first progressive scan processor doubles the line rate of the video input signal by storing each line and recovering the stored line twice during one line interval to provide a first video output signal.
- a second progressive scan processor doubles the line rate of the video input signal by storing each frame thereof and recovering the stored frame twice during one frame interval to provide a second video output signal.
- a detector coupled to the input means detects the identification signal and provides a control signal to a switch means for selectively coupling the video output signals to a display means.
- FIG. 1 is a block diagram of a receiver embodying the invention
- FIGS. 2 and 3 are block diagrams of camera and telecine sources, respectively suitable for use with the receiver of FIG. 1;
- FIG. 4 is a block diagram of a flag encoder suitable for use with the sources of FIGS. 2 and 3;
- FIGS. 5 and 6 are block diagrams of line and frame type progressive scan processors suitable for use in the receiver of FIG. 1;
- FIG. 7 is a block diagram of the flag signal decoder suitable for use in the receiver of FIG. 1;
- FIG. 8 is a block diagram of a switch synchronizer suitable for use in the frame store processor of FIG. 6.
- the receiver of FIG. 1 includes the tuner, IF amplifier and detector unit 10 of conventional design having an input terminal 12 for connection to a source (e.g., antenna, cable, etc.) of video input signal S1 and an output for providing a baseband video output signal S2 to a luma/chroma separator (Y/C) 14.
- Unit 14 supplies a chrominance output signal C to chroma processing unit 16 which doubles the line rate of the chroma signal.
- unit 16 may comprise a line repeating type progressive scan processor described in the aforementioned Dischert patent and illustrated herein as FIG. 5. Briefly, in FIG.
- a video input signal is alternatively applied by an video input switch 502 to a pair of one line memorys 504 and 506 and recovered from the memories by means of an output switch 508.
- Clock signals for controlling the memory read/write operations are provided by a clock source 510 which provides a write clock signal FW to a multiplier 512 which doubles the frequency of the write clock signal to produce a read clock signal FR.
- the read and write clock signals FW and FR are applied to respective ones of memorys 504 and 506 by means of a write clock switch 514 synchronized with the input and output switches 502 and 508 such that the memory which is reading is clocked at twice the rate of memory which is writing thereby doubling the line rate of the video output signal.
- the double line rate chroma signal C' produced by processor 16 is combined with a double line rate luma signal Y' in a matrix unit 18 of conventional design which in turn supplies a double line rate video output signal S3 in component form (R, G, B) to a display unit 20.
- the luminance signal provided by luma/chroma separator 14 is applied to a sync separator 22 which supplies line rate (FH) and field rate (FV) sync signals to display 20.
- a frequency doubler 24 doubles the frequency of the line rate sync signals FH to thereby provide a raster on display 20 having 525 lines per field for displaying the double line rate RGB component signal in progressively scanned (non-interlaced) fashion.
- the line rate of the luma signal Y is doubled by means of a line type progressive scan processor 26 and a frame type progressive scan processor 28 (FIGS. 5 and 6, respectively) having outputs coupled via a selector switch 30 to matrix 18.
- Switch 30 is controlled to select the output of processor 28 for each pair of fields of the video input signal S1 which are representative of the same scene and to select the output of processor 26 otherwise.
- Control for switch 30 is provided by a flag detector (FIG. 7) which detects the presence of an identification signal ("flag" hereinafter) in the vertical blanking interval of the input signal which signifys that the previous two frames are taken from exactly the same scene and supplies a set signal to the set input of a flip flop 34 which controls switch 30.
- flip-flop 34 selects the output of processor 28 and when reset it selects the output of processor 26.
- Flip-flop 34 is initially reset at the start of each odd field by means of detector 36 coupled to receive the vertical sync signal FV from sync separator 22. Thus, if the flag signal is not present, operation reverts to line progressive scan processing.
- the flag signal for controlling switch 30 may be generated as shown in FIGS. 2 or 3.
- a camera 202 is specially modified so as to provide an interlaced video output signal having 262.5 lines per field, 60 fields per second in which each pair of odd and even fields is derived from exactly the same scene.
- a flag encoder (FIG. 4) 204 adds the indentifying signal on flag to a line (e.g., line 21) in the vertical blanking interval of odd fields provided by camera 202.
- Camera 202 comprises an imager 206 coupled to a sync signal generator 208 for receiving vertical (FV) and horizontal (FH) sync signals.
- the vertical sync signal FV is divided by two by means of divider 210.
- imager 206 thus provides noninterlaced output signals having 525 lines per field and a field rate of 30 Hertz.
- An interlace convertor 212 of conventional design converts the output of imager 206 to interlace form of the standard 262.5 lines per field, 60 fields per second. Accordingly, each pair of fields produced by converter 212 is derived from a single 525 line scan of imager 206. These field pairs are identified by encoder 204 which inserts the identification signal in the vertical blanking interval of every other field of the signal provided by interlaced converter 212.
- Encoder 204 may be constructed as shown in FIG. 4.
- the encoder includes a switch 408 which normally couples the output of camera 202 to other studio equipment but selects the output of a flag signal genertor 410 when enabled during line 21 of odd fields by means of AND gate 406.
- One input of gate 406 is coupled to a control terminal for receiving an enable (High)/inhibit (low) control signal.
- Another input is coupled to the output of a decoder which identifies line 21 by decoding the output of a counter 402 that is clocked by signal FH and reset by signal FV.
- a third input of gate 406 is coupled to receive odd field identification signals from an odd field detector 403 which identifies odd fields by detecting the half line offset of the video input signal.
- the second input of gate 406 is connected to a source of positive voltage such that the output signal of gate 406 causes switch 408 to insert the flag signal in line 21 of the vertical blanking interval of odd fields.
- the purpose of terminal 407 is to inhibit the operation of the flag encoder for "mixed" fields.
- a “mixed” field means a pair of fields that come from different scenes. This becomes a consideration, as will be explained, when the video source is a telecine machince (rather than a camera) when converting film to NTSC format output signals.
- Switch 408 normally couples the output camera 202 to a recorder or broadcast transmitter for transmission to the receiver of FIG.
- Signal generator 40 may be of conventional design but for maximum noise immunity it may include error check encoding circuitry for enhancing the noise immunity of the flag signal.
- the signal source of FIG. 3 comprises a telecine machine having a sprocket hole counter 304 that identifies each film frame scanned by the machine.
- the film frame signal is supplied to terminal 407 of encoder 204 by a two field delay line (e.g., mono-stable multi-vibrator) 306 for inhibiting insertion of the flag signal during "mixed" fields.
- a two field delay line e.g., mono-stable multi-vibrator
- the spocket hole counter provides a film frame identifying signal which is delayed by two fields in element 306 for enabling flag encoder 204 to identify the first pair of fields from each film frame produced by telecine machine 302.
- the telecine machine 302 provides two video fields from a first frame of film and 3 video fields from a second frame of film.
- the first two fields are always taken from the same frame and encoded by flag encoder 204 with the special identifying signal in the vertical blanking interval.
- telecine machine 302 may be modified for reducing the number of mixed fields in the film to NTSC conversion by changing the "pull down factor" from 2-3-2-3 to a different factor.
- a pull down sequence of 2-3-3-2 causes only one frame out of five to be mixed. If a pull down sequence of 2-2-4-2 is used no mixed frame will be produced but a motion artifact may be generated in some cases due to four fields being taken from the same film frame.
- Processor 28 may be constructed as shown in FIG. 6.
- the luminance signal Y is sequentially applied by input signal switch 602 to four one-field memories 604 through 610.
- Switch 602 is synchronized by means of a switch synchronizer 612 to store odd lines in field memories 604 and 608 and even lines in field memories 606 and 610.
- a switching circuit (indicated generally as 612) supplies read and write clock signals FR and FW respectively to memorys 604-610 in sychronizism with switch 602.
- the write clock signal is produced by clock generator 614 and the read clock signal is produced by a frequency doubler 616 which doubles the output of clock 614.
- switch 612 supplies a write clock signal to field memory 604 and alternatively supplies read clock signals to memories 608 and 610 which contain the previous two fields of the video input signal with odd lines being stored in memory 608 and even lines being stored in memory 610.
- An output switch (indicated generally as 618) alternatively couples the odd and even lines of memories 608 and 610 to an output terminal 620 to provide the double line rate video output signal Y'.
- Switch 602 is advanced at the field rate of the video input signal to thereby sequentially store odd frames in memories 604 and 606 and even frames in memories 608 and 610. After one frame of the video input signal has been stored in memories 604 and 606, the output switch connects these memories to the output terminal for producing the double line rate video output signal and storage of the next frame begins in field memories 608 and 610.
- Switch synchronizer 612 may be constructed as shown in FIG. 8.
- the control signals A, B, C and D for switches 602 and 612 are provided by means of a 1 of 4 decoder 802 coupled to the output of a divide by 4 counter 804 which is clocked by the vertical sync signal FV.
- counter 804 is reset by means of a vertical sync detector 806.
- the output of detector 806 comprises a pulse for each odd field of the video input signal Y. This is applied to a flip flop 808 which changes state for every other odd sync pulse and triggers a mono stable multi vibrator 810 that resets counter 804. Since counter 804 is reset for every other odd field it is ensured odd lines are always stored in memorys 604 and 608 and even lines in memorys 606 and 610.
- the flag signal described herein may be conveyed in portions of the video signal other than the vertical blanking interval (e.g., the horizontal blanking interval, the sound carrier, etc.). Also, although odd fields are flagged herein, the flag may be placed in even error fields. Further, video sources other than the disclosed camera and telecine machince may be used for generating the video signal provided that the flag signal is clearly associated with fields derived from exactly the same scene. To ensure that the double line-rate video output signals of processor 16, 26 and 28 are properly registered, the video input or output signals of processors 16 and 26 may be delayed by an amount such that the overall delay substantially equals the processing delay of the frame processor 28.
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Abstract
Description
Claims (4)
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/760,909 US4641188A (en) | 1985-07-31 | 1985-07-31 | Progressive scan display system employing line and frame memories |
CA000513501A CA1282165C (en) | 1985-07-31 | 1986-07-10 | Progressive scan display system employing line and frame memories |
GB8618102A GB2178922B (en) | 1985-07-31 | 1986-07-24 | Progressive scan display system employing line and frame memories |
KR1019860006247A KR940011063B1 (en) | 1985-07-31 | 1986-07-30 | Progressive scan display system employing line and frame memories |
FR868611061A FR2585914B1 (en) | 1985-07-31 | 1986-07-30 | PROGRESSIVE SCAN VIEWING SYSTEM EMPLOYING LINE AND IMAGE MEMORIES |
JP61181209A JPH0783466B2 (en) | 1985-07-31 | 1986-07-30 | Progressive scan display |
DE3625932A DE3625932C2 (en) | 1985-07-31 | 1986-07-31 | Image display system for continuous scanning |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/760,909 US4641188A (en) | 1985-07-31 | 1985-07-31 | Progressive scan display system employing line and frame memories |
Publications (1)
Publication Number | Publication Date |
---|---|
US4641188A true US4641188A (en) | 1987-02-03 |
Family
ID=25060540
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US06/760,909 Expired - Lifetime US4641188A (en) | 1985-07-31 | 1985-07-31 | Progressive scan display system employing line and frame memories |
Country Status (7)
Country | Link |
---|---|
US (1) | US4641188A (en) |
JP (1) | JPH0783466B2 (en) |
KR (1) | KR940011063B1 (en) |
CA (1) | CA1282165C (en) |
DE (1) | DE3625932C2 (en) |
FR (1) | FR2585914B1 (en) |
GB (1) | GB2178922B (en) |
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US4853765A (en) * | 1987-04-30 | 1989-08-01 | Hitachi, Ltd. | Sequential scanning converter with frame comb filter and freeze frame feature |
US4868656A (en) * | 1987-07-04 | 1989-09-19 | Deutsche Thomson-Brandt Gmbh | Method and apparatus for reducing visibility of scanning lines in television picture |
US4881125A (en) * | 1988-10-14 | 1989-11-14 | General Instrument Corporation | Progressive scan display of video derived from film |
EP0367929A2 (en) * | 1988-11-11 | 1990-05-16 | GRUNDIG E.M.V. Elektro-Mechanische Versuchsanstalt Max Grundig holländ. Stiftung & Co. KG. | Device for reducing flicker in television receivers |
EP0370500A2 (en) * | 1988-11-23 | 1990-05-30 | GRUNDIG E.M.V. Elektro-Mechanische Versuchsanstalt Max Grundig GmbH & Co. KG | Circuitry for selecting between different methods of flicker reduction in a television receiver |
US4933765A (en) * | 1988-08-30 | 1990-06-12 | General Electric Company | Enhanced TV system using transmitted error signals |
US4998287A (en) * | 1988-10-14 | 1991-03-05 | General Instrument Corporation | Determination of sequential positions of video fields derived from film |
US5027206A (en) * | 1988-09-16 | 1991-06-25 | U.S. Philips Corporation | High-definition television systems |
WO1991013520A1 (en) * | 1990-02-23 | 1991-09-05 | Massachusetts Institute Of Technology | Video frame reduction/reconstruction method and apparatus |
WO1992002102A1 (en) * | 1990-07-26 | 1992-02-06 | Massachusetts Institute Of Technology | Method for decoding television signals |
US5140420A (en) * | 1990-10-05 | 1992-08-18 | General Electric Company | Information in vertical blanking interval of video sync signal |
US5187575A (en) * | 1989-12-29 | 1993-02-16 | Massachusetts Institute Of Technology | Source adaptive television system |
US5260787A (en) * | 1991-05-14 | 1993-11-09 | Sony Electronics Inc. | Film-to-video frame image conversion apparatus and method for selectively identifying video fields and frames |
US5343248A (en) * | 1991-07-26 | 1994-08-30 | Sony Corporation | Moving image compressing and recording medium and moving image data encoder and decoder |
US5355178A (en) * | 1991-10-24 | 1994-10-11 | Eastman Kodak Company | Mechanism for improving television display of still images using image motion-dependent filter |
US5369441A (en) * | 1989-07-06 | 1994-11-29 | Canon Kabushiki Kaisha | Reproducing apparatus with simultaneous parallel processing of different image signals |
US5406333A (en) * | 1994-03-14 | 1995-04-11 | Thomson Consumer Electronics, Inc. | Method and device for film-mode detection |
US5444491A (en) * | 1993-02-26 | 1995-08-22 | Massachusetts Institute Of Technology | Television system with multiple transmission formats |
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US5485280A (en) * | 1992-10-30 | 1996-01-16 | Sony Corporation | Apparatus and method for producing downwards compatible video signals with increased vertical resolution, and apparatus for reproducing and displaying same |
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US6108041A (en) * | 1997-10-10 | 2000-08-22 | Faroudja Laboratories, Inc. | High-definition television signal processing for transmitting and receiving a television signal in a manner compatible with the present system |
US6437828B1 (en) * | 1997-09-30 | 2002-08-20 | Koninklijke Philips Electronics N.V. | Line-quadrupler in home theater uses line-doubler of AV-part and scaler in graphics controller of PC-part |
US6670994B2 (en) * | 1997-04-01 | 2003-12-30 | Hewlett-Packard Development Company, L.P. | Method and apparatus for display of interlaced images on non-interlaced display |
US20040130660A1 (en) * | 2000-12-20 | 2004-07-08 | Crabb Michael Evan | Decoding information for interlaced to progressive scan conversion |
US6791623B1 (en) | 1994-10-24 | 2004-09-14 | Hitachi, Ltd. | Image display system |
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US20060153473A1 (en) * | 2005-01-13 | 2006-07-13 | Ruggiero Carl J | Video processing system and method with dynamic tag architecture |
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- 1986-07-30 JP JP61181209A patent/JPH0783466B2/en not_active Expired - Fee Related
- 1986-07-30 FR FR868611061A patent/FR2585914B1/en not_active Expired - Fee Related
- 1986-07-30 KR KR1019860006247A patent/KR940011063B1/en not_active IP Right Cessation
- 1986-07-31 DE DE3625932A patent/DE3625932C2/en not_active Expired - Fee Related
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Cited By (83)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4843485A (en) * | 1983-12-23 | 1989-06-27 | General Electric Company | Multiple format digital video tape record and replay system |
US4698675A (en) * | 1986-09-29 | 1987-10-06 | Rca Corporation | Progressive scan display system having intra-field and inter-field processing modes |
US4853765A (en) * | 1987-04-30 | 1989-08-01 | Hitachi, Ltd. | Sequential scanning converter with frame comb filter and freeze frame feature |
US4868656A (en) * | 1987-07-04 | 1989-09-19 | Deutsche Thomson-Brandt Gmbh | Method and apparatus for reducing visibility of scanning lines in television picture |
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Also Published As
Publication number | Publication date |
---|---|
JPS6231287A (en) | 1987-02-10 |
FR2585914A1 (en) | 1987-02-06 |
JPH0783466B2 (en) | 1995-09-06 |
DE3625932C2 (en) | 1997-09-04 |
GB2178922A (en) | 1987-02-18 |
DE3625932A1 (en) | 1987-02-12 |
GB2178922B (en) | 1989-08-16 |
GB8618102D0 (en) | 1986-09-03 |
KR940011063B1 (en) | 1994-11-22 |
CA1282165C (en) | 1991-03-26 |
KR870001724A (en) | 1987-03-17 |
FR2585914B1 (en) | 1991-01-18 |
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