US4616402A - Method of manufacturing a semiconductor device with a stacked-gate-electrode structure - Google Patents

Method of manufacturing a semiconductor device with a stacked-gate-electrode structure Download PDF

Info

Publication number
US4616402A
US4616402A US06729660 US72966085A US4616402A US 4616402 A US4616402 A US 4616402A US 06729660 US06729660 US 06729660 US 72966085 A US72966085 A US 72966085A US 4616402 A US4616402 A US 4616402A
Authority
US
Grant status
Grant
Patent type
Prior art keywords
gate
silicon
layer
film
method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
US06729660
Inventor
Seiichi Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Grant date

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer, carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in H01L21/20 - H01L21/268
    • H01L21/28273Making conductor-insulator-conductor-insulator-semiconductor electrodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/788Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881Programmable transistors with only two possible levels of programmation
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/156Sonos

Abstract

A method of manufacturing a semiconductor device with a stacked-gate-electrode structure which includes; forming source and drain regions in the surface portion of a semiconductor substrate in a spaced-apart relationship, forming a floating gate such that it overlies the channel region between the source and drain regions with a gate insulating film therebetween, and forming a control gate such that it overlies the floating gate with an insulating film therebetween. An oxidation-resistant film pattern having a predetermined opening is formed over a non-monocrystalline silicon layer. The non-monocrystalline silicon layer within the opening is selectively oxidized with the oxidation-resistant film pattern as a mask to form a separation insulating film. In this way, a floating gate layer is formed with the portion of the non-monocrystalline silicon layer insulatingly separated. With the oxidation-resistant film pattern left over the floating gate layer and with the separation insulating film left within the opening, a control gate layer is formed over the surface of the resultant surface to permit the whole surface of the resultant surface to be planarized.

Description

BACKGROUND OF THE INVENTION

This invention relates to a method of manufacturing a semiconductor device and, in particular, a method of manufacturing a semiconductor device having a stacked-gate-electrode structure.

An EPROM (Erasable Programmable Read Only Memory) includes a two-layered gate electrode structure: a floating gate and control gate. Conventionally, the floating gate is formed by etching a polycrystalline silicon layer which is formed on a first gate insulating film. In this connection it is to be noted that an opening is formed by an etching step in the polycrystalline silicon layer. At the same time, there occur cases where protruding ends are formed on the polycrystalline silicon layer. Thereafter, a conductive layer is so formed that it overlies the etched polycrystalline silicon layer with a second gate insulating film therebetween. In this way, a control gate is formed.

According to the conventional method, there occur cases where no such second gate insulating film of an adequate thickness is formed at the ends of the opening and thus the critical field strength of the second gate insulating film is lowered. Furthermore, if the end of the etched polycrystalline silicon layer protrudes, an electric field is concentrated there, thus lowering the critical field strength of the second gate insulating film. If the conductive layer is formed at the location of the opening, there is disadvantage that a breakage occurs at the stepped portion of the opening. This phenomenon prominently occurs if the conductive layer, in particular, is formed of, for example, a metal layer having a high melting point, a layer of a silicide of the metal having high melting point or a polycide layer (i.e., a two-layered structure comprised of a polycrystalline silicon layer and a layer of a silicide of the metal having a high melting point).

U.S. Pat. No. 4,412,310 to George J. Korsh et al. discloses the process of forming an oxide layer between a floating gate and an overlying control gate, in which the oxide layer is thicker at the edges of the floating gate than in the central portion thereof. According to this invention, however, the above-mentioned problem is solved by another method.

SUMMARY OF THE INVENTION

It is accordingly an object of this invention to provide a method of manufacturing a semiconductor device with a stacked-gate-electrode structure, which can improve critical field strength across gate electrodes and can prevent a breakage in the stepped portion of two or more gate electrodes.

To attain the above-mentioned advantage, there is provided a method of manufacturing a semiconductor device which comprises the steps of forming source and drain regions in the surface portion of a semiconductor substrate in a spaced-apart relation, forming a floating gate such that it overlies a channel region between the source and drain regions with a gate insulating film formed therebetween and forming a control gate such that it overlies the floating gate with an insulating film formed between the control gate and the floating gate, the improvement further comprising the steps of forming an oxidation-resistant film pattern having a predetermined opening over a non-monocrystalline silicon layer, forming a floating gate layer by selectively oxidizing the non-monocrystalline silicon layer within the predetermined opening with the oxidation-resistant film pattern as a mask to form a separation insulating film with a portion of the non-monocrystalline silicon layer insulatingly separated therefrom, and forming the control gate formation layer over the resultant structure with the oxidation-resistant film pattern left over the floating gate layer and with the separation insulating film left within the opening to permit the surface of the resultant structure to be planarized.

In the method of this invention, since an oxidation-resistant pattern of, for example, Si3 N4, which has been used as a mask, is used also as a gate insulating film, it is possible to improve the critical field strength of a gate insulating film. Furthermore, the non-monocrystalline silicon layer is selectively oxidized to form the floating gate layer with the portion of the non-monocrystalline silicon layer insulatingly separated, reducing the stepped portion of the control gate layer and thus preventing a breakage at that stepped portion. The end of the floating gate is smoothly formed due to the selective oxidation, preventing an electric field from being concentrated at the end of the floating gate.

BRIEF DESCRIPTION OF THE DRAWINGS

The other objects and advantages will be apparent from the following description taken in conjunction with the accompanying drawings in which:

FIGS. 1A to 1E are cross-sectional views for explaining a method of manufacturing a semiconductor device according to a first embodiment of this invention;

FIG. 2 is a plan view showing a semiconductor device manufactured according to the method of this invention; and

FIG. 3 is a cross-sectional view as taken along line III--III in FIG. 2.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The method of manufacturing an EPROM according to this invention will be explained below by referring to FIGS. 1A to 1E, 2 and 3.

As shown in FIG. 1A, an element separation area 12 is formed by a well known technique on the surface portion of a p type silicon substrate 10 and a first gate insulating film 16 is formed by, for example, a thermal oxidation method on a channel region in an island region 14 of the silicon substrate 10 which is surrounded by the element separation area 12. Then, a first polycrystalline silicon layer 18 made of non-monocrystalline silicon is deposited, with a thickness of, for example, 0.2 μm (2000 Å), on the whole surface of the resultant structure and then the silicon layer 18 is heavily doped either by an ion implantation method or by a thermal diffusion method using a POCl3 as a diffusion source, to attain a high concentration level of 3×1020 to 8×1020 /cm3. In the thermal diffusion method, heat treatment can be effected in the POCl3 atmosphere for 30 to 70 minutes at 900° C. to 950° C.

Then, as shown in FIG. 1B, a first silicon oxide film 50 about 20 nm (200 Å) thick is formed on a first polycrystalline silicon layer 18 by adopting a diluted oxygen method at a temperature of, for example, 900° C. to 1100° C. Then, as shown in FIG. 1C, a silicon nitride film about 15 nm (150 Å) thick is formed on the whole surface of the resultant structure by an LPCVD (Low Pressure Chemical Vapor Deposition), a plasma CVD method or thermal nitridation and the silicon nitride film portion overlying a predetermined portion of the element separation area 12 is selectively removed by a photolithography and a RIE method to obtain a silicon nitride film pattern 22 having an opening 20. An area of the opening 20 is smaller than that of the portion of the element separation area 12, as shown in FIG. 1C.

Then, as shown in FIG. 1D, a thermal oxidation step is carried out with a silicon nitride film pattern 22 as a mask, under the condition that the portion of the first polycrystalline silicon layer 18 within the opening 20 of the silicon nitride film pattern 22 is completely oxidized. As a result, the first polycrystalline silicon layer portion below the opening 20 of the silicon nitride pattern 22 is thermally oxidized to provide a second silicon oxide film 24 and a third silicon oxide film 52 on the silicon nitride film pattern 22. In this way, the whole surface of the silicon substrate 10 is substantially planarized. The remaining unoxidized first polycrystalline silicon layer 18 provides a first polycrystalline silicon layer pattern 26 as a floating gate with its end 28 smoothly formed.

As shown in FIG. 1E, a second polycrystalline silicon layer is deposited on the whole surface of the resultant structure and, after being subjected to a patterning step, provides a control gate 38. Then, with the control gate as a mask an n-type impurity is ion-implanted into the silicon substrate 10 to provide N+ type source and drain regions 40 and 42. An insulating film, though not shown, is formed on the whole surface of the resultant structure and the portions of the insulating film overlying the source and drain regions 40 and 42 are opened to provide corresponding contact holes over which an Al interconnection layer is formed. In this way, an EPROM is fabricated for which reference is invited to FIGS. 2 and 3.

According to this embodiment, since the first polycrystalline silicon layer pattern 26 (left unoxidized at the step of the selective oxidation of the first polycrystalline silicon layer 18) provides the floating gate and since the second silicon oxide film 24 is formed over the opening 20 and the third silicon oxide film 52 is formed on the silicon nitride film pattern 22, it is possible to substantially planarize the whole surface of the device. This specific arrangement can overcome a problem, that is, a reduction in critical field strength between the control gate and the floating gate which may be involved in the conventional method of forming the floating gate by the RIE step. Furthermore, the end 28 of the first polycrystalline silicon layer pattern 26 is convexly and smoothly formed, preventing an electric field from being concentrated there. The three-layered insulating film structure, that is, the first silicon oxide film 50, silicon nitride film pattern 22 and third silicon oxide film 52 are formed between the floating gate 26 and the control gate 38 with the result that the silicon nitride film pattern 22 deposited alleviates a non-uniformity in the film thickness of the first silicon oxide film 50 and has its own high critical field strength. It is therefore possible to improve the critical field strength of the gate insulating film between the floating gate 26 and the control gate 38. It is also possible to obtain a greater capacitance between the floating gate 26 and the control gate 38 due to the presence of the silicon nitride film pattern 22 of a high electric constant or permittivity.

This embodiment can be modified as follows. The control gate 38 may be formed of a metal layer, metal silicide layer or polycide layer, having high melting points. In this case, the whole surface of the semiconductor device can be substantially planarized, prominently avoiding any possible breakage in the stepped portion of the control gate.

As a gate insulating film between the floating gate 26 and the control gate 38 use may be made of a silicon nitride film pattern 22 only, or a two-layered structure comprised of the silicon oxide film (50 or 53) and silicon nitride film pattern. The floating gate is not restricted to the polycrystalline silicon layer and may be formed an amorphous semiconductor layer.

Although this embodiment has been explained as being applied to the EPROM, it is not restricted thereto. This invention is also applicable to the manufacture of a semiconductor device having two or more gate electrodes.

Claims (14)

What is claimed is:
1. A method of manufacturing a semiconductor device with a stacked-gate-electrode structure, comprising the steps of:
forming an element separation area in the surface portion of a semiconductor substrate;
forming a gate insulating film on an island region of said semiconductor substrate surrounded by the element separation area;
forming a non-monocrystalline silicon layer on the whole surface of the resultant structure;
forming over the non-monocrystalline silicon layer an oxidation-resistant film pattern having an opening at a portion thereof corresponding to a portion of the element separation area, an area of said opening being smaller than that of said portion of the element separation area;
forming a first gate electrode by selectively oxidizing a non-monocrystalline silicon layer within the opening with the oxidation-resistant film pattern as a mask to form a separation insulating film with a portion of the non-monocrystalline silicon layer insulatingly separated; and
forming, with said oxidation-resistant film pattern left over the first gate electrode and with said separation insulating film left within the opening, a second gate electrode over the surface of the resultant structure to permit the whole surface of the resultant structure to be planarized.
2. A method according to claim 1, in which said oxidation-resistant film pattern is a silicon nitride film pattern.
3. A method according to claim 1, further comprising the steps of heavily doping an impurity into the non-monocrystalline silicon layer before said non-monocrystalline silicon layer is selectively oxidized.
4. A method according to claim 3, in which phosphorus is heavily doped, as the impurity, in the order of 3×1020 to 8×1020 /cm3.
5. A method according to claim 1, in which said non-monocrystalline silicon layer is a polycrystalline silicon layer or an amorphous silicon layer.
6. A method according to claim 1, in which said second gate electrode is formed of a silicide of a metal having a high melting point.
7. A method according to claim 1, in which said second gate electrode is made of a polycide layer.
8. A method according to claim 1, in which said oxidation-resistant film pattern is formed so as to overlie said non-monocrystalline silicon layer with an insulating film therebetween.
9. A method according to claim 8, in which said oxidation-resistant film pattern is a silicon nitride film pattern.
10. A method according to claim 8, further comprising the step of heavily doping an impurity into said non-monocrystalline silicon layer before said non-monocrystalline silicon layer is selectively oxidized.
11. A method according to claim 10, in which phosphor is heavily doped, as said impurity, in the order of 3×1020 to 8×1020 /cm3.
12. A method according to claim 8, in which said non-monocrystalline silicon layer is a polycrystalline silicon layer or an amorphous silicon layer.
13. A method according to claim 8, in which said second gate electrode is formed of a metal having a high melting point or a silicide of said metal.
14. A method according to claim 8, in which said second gate electrode is formed of a polycide layer.
US06729660 1984-05-07 1985-05-02 Method of manufacturing a semiconductor device with a stacked-gate-electrode structure Expired - Lifetime US4616402A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP9041484A JPS60234372A (en) 1984-05-07 1984-05-07 Manufacture of semiconductor device
JP59-90414 1984-05-07

Publications (1)

Publication Number Publication Date
US4616402A true US4616402A (en) 1986-10-14

Family

ID=13997930

Family Applications (1)

Application Number Title Priority Date Filing Date
US06729660 Expired - Lifetime US4616402A (en) 1984-05-07 1985-05-02 Method of manufacturing a semiconductor device with a stacked-gate-electrode structure

Country Status (2)

Country Link
US (1) US4616402A (en)
JP (1) JPS60234372A (en)

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4892840A (en) * 1986-03-27 1990-01-09 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling
US5091327A (en) * 1990-06-28 1992-02-25 National Semiconductor Corporation Fabrication of a high density stacked gate eprom split cell with bit line reach-through and interruption immunity
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
US5266509A (en) * 1990-05-11 1993-11-30 North American Philips Corporation Fabrication method for a floating-gate field-effect transistor structure
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
US5619052A (en) * 1994-09-29 1997-04-08 Macronix International Co., Ltd. Interpoly dielectric structure in EEPROM device
US5928966A (en) * 1996-06-07 1999-07-27 Sony Corporation Method for manufacturing a stacked electrode for a semiconductor device
US6002152A (en) * 1992-01-14 1999-12-14 Sandisk Corporation EEPROM with split gate source side injection with sidewall spacers
US6222762B1 (en) 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US20030052360A1 (en) * 1992-01-14 2003-03-20 Guterman Daniel C. EEPROM with split gate source side injection with sidewall spacers
US20030232507A1 (en) * 2002-06-12 2003-12-18 Macronix International Co., Ltd. Method for fabricating a semiconductor device having an ONO film
US20060246662A1 (en) * 2005-04-28 2006-11-02 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0640588B2 (en) * 1987-03-13 1994-05-25 株式会社東芝 A semiconductor memory device

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4407696A (en) * 1982-12-27 1983-10-04 Mostek Corporation Fabrication of isolation oxidation for MOS circuit
US4412310A (en) * 1980-10-14 1983-10-25 Intel Corporation EPROM Cell with reduced programming voltage and method of fabrication
US4426764A (en) * 1977-04-06 1984-01-24 Hitachi, Ltd. Semiconductor memory device with peripheral circuits
US4495693A (en) * 1980-06-17 1985-01-29 Tokyo Shibaura Denki Kabushiki Kaisha Method of integrating MOS devices of double and single gate structure
US4512074A (en) * 1982-09-09 1985-04-23 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing selective oxidation and diffusion from a polycrystalline source
US4517732A (en) * 1982-10-05 1985-05-21 Fujitsu Limited Method for fabricating an EEPROM

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4426764A (en) * 1977-04-06 1984-01-24 Hitachi, Ltd. Semiconductor memory device with peripheral circuits
US4495693A (en) * 1980-06-17 1985-01-29 Tokyo Shibaura Denki Kabushiki Kaisha Method of integrating MOS devices of double and single gate structure
US4412310A (en) * 1980-10-14 1983-10-25 Intel Corporation EPROM Cell with reduced programming voltage and method of fabrication
US4512074A (en) * 1982-09-09 1985-04-23 Tokyo Shibaura Denki Kabushiki Kaisha Method for manufacturing a semiconductor device utilizing selective oxidation and diffusion from a polycrystalline source
US4517732A (en) * 1982-10-05 1985-05-21 Fujitsu Limited Method for fabricating an EEPROM
US4407696A (en) * 1982-12-27 1983-10-04 Mostek Corporation Fabrication of isolation oxidation for MOS circuit

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
Chen, "Threshold-Alternable Si-Gate MOS Devices", IEEE Transactions Electron Dev., vol. ED-24, No. 5, May 1977.
Chen, Threshold Alternable Si Gate MOS Devices , IEEE Transactions Electron Dev., vol. ED 24, No. 5, May 1977. *
Jacobs et al., "n-Channel Sc-Gate Process for MNOS EEPROM Transistors," Solid State Electronics, vol. 24, pp. 517-522 (1981).
Jacobs et al., n Channel Sc Gate Process for MNOS EEPROM Transistors, Solid State Electronics, vol. 24, pp. 517 522 (1981). *

Cited By (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4892840A (en) * 1986-03-27 1990-01-09 Texas Instruments Incorporated EPROM with increased floating gate/control gate coupling
US5104819A (en) * 1989-08-07 1992-04-14 Intel Corporation Fabrication of interpoly dielctric for EPROM-related technologies
US5266509A (en) * 1990-05-11 1993-11-30 North American Philips Corporation Fabrication method for a floating-gate field-effect transistor structure
US5091327A (en) * 1990-06-28 1992-02-25 National Semiconductor Corporation Fabrication of a high density stacked gate eprom split cell with bit line reach-through and interruption immunity
US6954381B2 (en) 1992-01-14 2005-10-11 Sandisk Corporation EEPROM with split gate source side injection with sidewall spacers
US6856546B2 (en) 1992-01-14 2005-02-15 Sandisk Corporation Multi-state memory
US6317364B1 (en) 1992-01-14 2001-11-13 Sandisk Corporation Multi-state memory
US20030052360A1 (en) * 1992-01-14 2003-03-20 Guterman Daniel C. EEPROM with split gate source side injection with sidewall spacers
US6317363B1 (en) 1992-01-14 2001-11-13 Sandisk Corporation Multi-state memory
US6002152A (en) * 1992-01-14 1999-12-14 Sandisk Corporation EEPROM with split gate source side injection with sidewall spacers
US6222762B1 (en) 1992-01-14 2001-04-24 Sandisk Corporation Multi-state memory
US6275419B1 (en) 1992-01-14 2001-08-14 Sandisk Corporation Multi-state memory
US7898868B2 (en) 1992-01-14 2011-03-01 Sandisk Corporation Multi-state memory
US5580815A (en) * 1993-08-12 1996-12-03 Motorola Inc. Process for forming field isolation and a structure over a semiconductor substrate
US5707889A (en) * 1993-08-12 1998-01-13 Motorola Inc. Process for forming field isolation
US5619052A (en) * 1994-09-29 1997-04-08 Macronix International Co., Ltd. Interpoly dielectric structure in EEPROM device
US5836772A (en) * 1994-09-29 1998-11-17 Macronix International Co., Ltd. Interpoly dielectric process
US7449746B2 (en) 1996-02-28 2008-11-11 Sandisk Corporation EEPROM with split gate source side injection
US6704222B2 (en) 1996-02-28 2004-03-09 Sandisk Corporation Multi-state operation of dual floating gate array
US20040063283A1 (en) * 1996-02-28 2004-04-01 Guterman Daniel C. Eeprom with split gate source side injection
US20060163645A1 (en) * 1996-02-28 2006-07-27 Guterman Daniel C EEPROM With Split Gate Source Side Injection
US6664587B2 (en) 1996-02-28 2003-12-16 Sandisk Corporation EEPROM cell array structure with specific floating gate shape
US7071060B1 (en) 1996-02-28 2006-07-04 Sandisk Corporation EEPROM with split gate source side infection with sidewall spacers
US6861700B2 (en) 1996-02-28 2005-03-01 Sandisk Corporation Eeprom with split gate source side injection
US5928966A (en) * 1996-06-07 1999-07-27 Sony Corporation Method for manufacturing a stacked electrode for a semiconductor device
US6894926B2 (en) 1997-08-07 2005-05-17 Sandisk Corporation Multi-state memory
US6862218B2 (en) 1997-08-07 2005-03-01 Sandisk Corporation Multi-state memory
US20040165431A1 (en) * 1997-08-07 2004-08-26 Guterman Daniel C. Novel multi-state memory
US7088615B2 (en) 1997-08-07 2006-08-08 Sandisk Corporation Multi-state memory
US7573740B2 (en) 1997-08-07 2009-08-11 Sandisk Corporation Multi-state memory
US7187592B2 (en) 1997-08-07 2007-03-06 Sandisk Corporation Multi-state memory
US7289360B2 (en) 1997-08-07 2007-10-30 Sandisk Corporation Multi-state memory
US7345934B2 (en) 1997-08-07 2008-03-18 Sandisk Corporation Multi-state memory
US7457162B2 (en) 1997-08-07 2008-11-25 Sandisk Corporation Multi-state memory
US7385843B2 (en) 1997-08-07 2008-06-10 Sandisk Corporation Multi-state memory
US7443723B2 (en) 1997-08-07 2008-10-28 Sandisk Corporation Multi-state memory
US20050002233A1 (en) * 1997-08-07 2005-01-06 Guterman Daniel C. Novel multi-state memory
US20030232507A1 (en) * 2002-06-12 2003-12-18 Macronix International Co., Ltd. Method for fabricating a semiconductor device having an ONO film
US7371672B2 (en) * 2005-04-28 2008-05-13 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20060246662A1 (en) * 2005-04-28 2006-11-02 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same

Also Published As

Publication number Publication date Type
JPS60234372A (en) 1985-11-21 application

Similar Documents

Publication Publication Date Title
US5742095A (en) Method of fabricating planar regions in an integrated circuit
US5497021A (en) CMOS structure with varying gate oxide thickness and with both different and like conductivity-type gate electrodes
US5739564A (en) Semiconductor device having a static-random-access memory cell
US5292673A (en) Method of manufacturing a semiconductor device
US6340829B1 (en) Semiconductor device and method for manufacturing the same
US6100123A (en) Pillar CMOS structure
US5268326A (en) Method of making dielectric and conductive isolated island
US5057447A (en) Silicide/metal floating gate process
US5310693A (en) Method of making self-aligned double density polysilicon lines for EPROM
US5389808A (en) Non-volatile semiconductor memory with increased capacitance between floating and control gates
US5411909A (en) Method of forming a planar thin film transistor
US5254489A (en) Method of manufacturing semiconductor device by forming first and second oxide films by use of nitridation
US4757028A (en) Process for preparing a silicon carbide device
US4527181A (en) High density semiconductor memory array and method of making same
US6172395B1 (en) Method of manufacture of self-aligned floating gate, flash memory cell and device manufactured thereby
US4686000A (en) Self-aligned contact process
US4497106A (en) Semiconductor device and a method of manufacturing the same
US4471525A (en) Method for manufacturing semiconductor device utilizing two-step etch and selective oxidation to form isolation regions
US5227855A (en) Semiconductor memory device having a ferroelectric substance as a memory element
US4812885A (en) Capacitive coupling
US5108937A (en) Method of making a recessed gate MOSFET device structure
US5753555A (en) Method for forming semiconductor device
US5969393A (en) Semiconductor device and method of manufacture of the same
US4992389A (en) Making a self aligned semiconductor device
US5405806A (en) Method for forming a metal silicide interconnect in an integrated circuit

Legal Events

Date Code Title Description
AS Assignment

Owner name: KABUSHIKI KAISHA TOSHIBA, 72 HORIKAWA-CHO, SAIWAI-

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:MORI, SEIICHI;REEL/FRAME:004401/0720

Effective date: 19850418

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12