US3750004A - Instantaneous current control for static inverters - Google Patents
Instantaneous current control for static inverters Download PDFInfo
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- US3750004A US3750004A US00228632A US3750004DA US3750004A US 3750004 A US3750004 A US 3750004A US 00228632 A US00228632 A US 00228632A US 3750004D A US3750004D A US 3750004DA US 3750004 A US3750004 A US 3750004A
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- inverter
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- inverters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/483—Converters with outputs that each can have more than two voltages levels
- H02M7/49—Combination of the output voltage waveforms of a plurality of converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/505—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means
- H02M7/515—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a thyratron or thyristor type requiring extinguishing means using semiconductor devices only
Definitions
- An improvement is made to stepped wave static inverters in the form of an instantaneous current control cir- [52] 3 0;; 3 cuit.
- this circuit acts to limit current in the power I 58] m d 9 R H 4 switching devices of the inverter. Its performance is an e 3 3 5 5 improvement over previous current limit circuits in that it acts instantly to limit overload current and instantly to release that limit so that normal output volt- [56] References Cited age is restored immediately when the overload is re- UNITED STATES PATENTS moved.
- FIG. 2 shows a one line diagram which might be a portion of a real time computer installation.
- a fault in any of the various Ioads such as the one shown at Memory No. 3 may dips to 70 percent of normal. If the various portions of the critical load are protected-by current limiting fuses, the large available current will assure that the fuse will clear'quickly and the fault will be isolated within the two millisecond duration specified.
- UPS power source
- large fault currents are not available. It is a characteristic of thyristor inverters that there is a certain instantaneous peak current which can be carried (commutated). This current is typically in the range of twice rated peak current. If this current is exceeded even transiently, the inverter will be subject to a commutation failure or shoot-through. The commutation failure places a short across thebattery which must be cleared by current limiting fuses in the inverter cabinet. In order to pre- 7 vent commutation failures, theUPS must have some feature to limitoutput current by depressing out voltage quickly. The maximum short circuit current of UPS inverters will be limited by'this feature to about 1.75
- the selection of a proper fuse rating requires close coordination between the characteristics of the fuse and the fault current response of the inverter.
- the largest fuse which can be cleared within the voltage dip limits may be as small as 10 percent of the UPS rating.
- the largest fuse may be increased to 25 percent or more of the UPS rating.
- Static Interrupter Impedance Inserter A static interrupter impedance inserter consists of a fault limiting resistance shunted by a pair of antiparallel thyristors with forced commutation. It is connected between the UPS and the load so that normal load current flows through the anti-parallel thyristors. When the fault occurs, the interrupter can be opened in a fraction of a millisecond by commutating the thyristors. The fault current delivered will then be controlled by the value of the resistor and the impedance of the fault. This approach meets the design requirements A and B in that it limits current immediately without reducing it to zero.
- Design requirement C is harder to meet in this case because of the risk of commutation failure.
- the circuit should reapply gate pulses to the main thyristors in the static interrupter and restore normal voltage to the load.
- the problem which arises is that of determining when the fault has cleared. If the instantaneous load current drops below rated current, the circuit must distinguish between a normal zero crossing of theAC fault current and a true removal of the fault. The interrupter must not be allowed to reclose until it is certain that the fault is cleared or that the interrupter has regained its commutating capability and can'reopen immediately if the fault has not cleared.
- the inverter in accordance with the invention uses a fault current control approach which changes the firing of the inverter thyristors to control fault current, rather than depending on an external static interrupter impedance inserter for this function. It does not, however, change the setting of the inverter voltage regulator during the fault. Rather, it uses a signal level "subcycle current control". This circuit senses instantaneous current at the inverter thyristors and changes the firing times of the overloaded thyristors to deliver maximum output current rather than normal output voltage.
- FIG. 4 The external performance features resulting from the mode of inverter control in accordance with the invention are shown on FIG. 4.
- the figure shows that:
- the inverter can clear a dead fault and restore normal voltage within the time limits of FIG. 1.
- Branch fuse ratings up to 25 percent of total UPS capacity can be used and still meet FIG. 1 limits.
- the structural implementation of a preferred embodiment of the invention comprises in combination with an inverter of the type comprising a set of at least two single phase sub-inverters whose outputs are combined to form the total inverter output and which includes a multiphase transformer having primary and secondary windings and means to limit the instantaneous current of the subinverters to a predetermined value in the event of an overload in one or more of the sub-inverters, the improvement which comprises: means for modifying the operation of one or more of the sub-inverters in the event of an overload condition in one or more of the sub-inverters such as to limit the instantaneous current in the sub-inverters to a predetermined magnitude higher than said predetermined value during an overload condition in one or more of the sub-inverters.
- the means includes a plurality of 35 current sensing means.
- Each current sensing means is operatively connected to a sub-inverter and each operatively connected in circuit with the primary winding of the multiphase transformer associated with each subinverter for sensing current at each sub-inverter.
- the arrangement is such that the means is insensitive to total inverter output current and the total inverter output current may be safely considerably larger than said predetermined value than if the current sensing means were located in circuit with the secondary winding of the multiphase transformer associated with each sub-inverter and the means to limit the instantaneous current to a predetermined value was set to limit the V instantaneous current in the most overloaded subinverter.
- FIG. 1 illustrates a typical limit on voltage dip for computer loads
- FIG. 2 illustrates a fault in one branch of a critical load distribution network
- FIG. 3 illustrates a response of a typical stepped wave inverter to a line-to-line fault on phase AB.
- the fault is isolated by a fast fuse;
- FIG. 5 is a diagrammatic or skeleton schematic of an inverter power circuit
- FIG.5(a) illustrates the normal line-to-line 'output from the inverter of FIG. 5;
- FIG. 6 Illustrates a block diagram of inverter controls
- FIG. 7 illustrates a single phase bridge inverter showing operation of instantaneous fault current control
- FIG. 7(a) illustrates the operation of a single phase inverter of the type shown in FIG. 7 utilizing a prior art method of instantaneous current limit
- FIG. 7 (b) illustrates the waveforms in the circuit of FIG. 7 under normal operating conditions
- FIG. 7 (c) illustrates the waveforms in the circuit of FIG. 7 when a severe overload is applied to the inverter
- FIG. 8 illustrates the stepped wave voltage resulting when the current control described with reference to FIGS. 7, 7(a), 7(b) and 7(c) is applied to the individual sub-inverters of a stepped wave inverter;
- FIG. 8(a) illustrates one implementation of the commutation limit in accordance with the invention; also shown is a sequential truth table for the flip-flops of FIG. 8(a);
- FIG. 8(b) is a timing diagram for the circuit of FIG.
- FIG. 9 illustrates three phase voltage and current showing clearing of a fault on phase AB through a fuse of 25 percent of UPS rating (100 KVA preload);
- FIG. 10 illustrates details from the fault clearing test shown in FIG. 9;
- FIG. 11 illustrates a 10 second fault applied to phase AB through no protective device
- FIG. 12 illustrates current inrush on energizing a power transformer from a utility power source
- FIG. 13 illustrates current inrush on energizing a power transformer from the UPS inverter with subcycle current control
- FIG. 14 illustrates a diagrammatic representation of a recorded inrush on energizing a 75 KVA transformer from a 480 volt utility power source.
- Upper trace is voltage, 480 RMS.
- Lower trace is current, 300 amperes peak per vertical division;
- FIG. 15 illustrates a diagrammatic representation of a recorded inrush of the same 75 KVA transformer energized from the 200 KVA UPS inverter with subcycle current control. (Scales same as FIG. 14)
- the module configuration is of the floating battery continuous type with the battery always connected across the inverter input.
- the input rectifier is controlled to act as charger to the battery and simultaneously to supply the inverter during normal operation.
- Inverter Configuration The inverter power section is made up of 24 thyristorsoperated to form two conventional 12 step waves with first harmonic the 11th.
- Corey Methods of Optimining the Waveform of Stepped-Wave Static Inverters, AIEE Paper CP62-I 147, Denver, June 17-22, 1962.
- the two 12 step waves are operated at variable phase displacement from one another, ancl the resulting waves are combined to produce a three phase output wave whose amplitude is controlled by the value of the relative phase displacement.
- the thyristors are controlled by an all digital logic control. This digital control precisely determines the firing of each thyristor based on a digital voltage com mand.
- the subcycle current control logic is a part of this digital control.
- Power Circuit The connection of the power components is a shown in FIG. 5.
- the schematic shown in FIG. 5 with the exception of the six current transformers CTI through CT6 illustrates the power stage configuration of a typical 12 stepped wave inverter.
- the 24 thyristors are arranged in four three phase bridge inverters. Within each three phase bridge the thyristors are fired at precisely intervals.
- the two bridges associated with an output transformer are operated at variable phase with respect to one another, so that the voltage appearing on each transformer primary is a quasi-square wave of variable pulse width.
- the 12 thyristors associated with three transformer T2 are each fired at exactly 30 after the corresponding thyristor in the set of thyristors connected to transformer T1.
- the secondaries of the two transformers are combined in a zig-zag connection to construct a line-to-line voltage waveform of the desired step heights and times.
- the power filter consists of a series inductance and parallel capacitance to attenuate the 11th, 13th, and higher, harmonics.
- the series inductance is composed of the leakage reactance of the transformer and a small lumped reactance in each phase.
- FIG. 5(a) illustrates normal line-to-line output.
- FIG. 6 shows a block diagram of the controls. Analog Section
- the inverter output voltage and current are sensed by normal analog means. The sensed voltage is compared to a reference, and the error voltage is amplified to become the voltage command. When the output current exceeds the current limit reference, the takeover circuit allows the current sensing to control the voltage command. This voltage command is changed to a digital number between zero and 768 by the analog-todigital converter. This number determines the phase displacement between the two sets of stepped waves forming the output, and thus determines the output Frequency Control
- the frequency of inverter'output is determined by a high frequency crystal referenced oscillator. If the frequency or phase of the inverter must be trimmed to match another source, the oscillator can be biased away from crystal frequency by 12% percent (2 1.5 Hz at 60 Hz) to accomplish this matching.
- Subcycle Current Control does not act on the voltage command, but rather imposes changes in the thyristor firing signals after they have been determined by the voltage command and frequency reference.
- the hold signal from the subcycle current control causes the voltage control functions to maintain a constant stepping pattern when the subcycle current control is active;
- the digital thyristor timing control takes the digital information from the frequency reference clock and from the digital voltage command and forms timing signals for firing the 24 thyristors.
- the output signals of the digital thyristor timing control consists of two sets of six square waves. Within each set the waves are separated by exactly 30 electrical The leading set is phased ahead of a reference phase by an electrical angle proportional to the voltage command, alpha. The lagging set is phased behind the reference by this same angle.
- the 184 KHZ frequency reference clock pulses are counted down to form a digitalreference ramp which sweeps from zero to full count during each 16.667 millisecond cycle.
- the magnitude of the digital voltage command is continuously added to this digital reference ramp to form a displaced ramp. Twelve decoders monitor this displaced ramp to select times for firing the 12 leading thyristors.
- the digital voltage command is subtracted from the reference ramp and the resulting displaced ramp is decoded by circuitry identical to that on the leading side.
- the subcycle current control logic is interposed between the lagging decoders and the gating signals. In normal operation thesubcycle current control logic passes these signals-unchanged.
- Logic Hardware Although the operation of the digital logic is precise and of high resolution, it is not complex to implement. The digital blocks are chosen to use standard TL complex function logic. These standard logic functions are available in dual in-line packages from several vendors.
- the total thyristor timing logic including subcycle current control is built on three 8 inch square printed circuit boards.
- a major advantage of the all-digital thyristor control is the flexibility it allows in the control of overload curneous in action. It senses currents at the inverting thyristors and intervenes in the logic to control the firing of the lagging thyristors to limit instantaneous current to a value which can be commutated. It does not affect the firing times of all the lagging thyristors, but only those which must be changed in order to maintain commutation margin.
- Each single phase bridge inverter would be identical to that shown in FIG. 7 if so drawn. Shown in FIG. 7 are the reverse diodes (CR-1, CR-l', CR-4 and CR4) in parallel with each SCR which are not shown in FIG. 5, but are essential to operation of the inverter. Not shown in FIG. 5 or 7 are the commutating circuits necessary to turn off the inverter SCRs. Many commutating circuit configurations would be suitable.
- FIG. 7(a) shows the operation of such a single phase inverter using this method of instantaneous current limit. The lagging side thyristors are caused to commutate at the instant the current exceeds the limitvalue, thus terminating the power pulse.
- the waveforms illustrated therein are the waveforms in the circuit of FIG. 7 under normal operating conditions.
- the magnitude of the phase displacement 11: between the leading and lagging inverter half-bridges determines the magnitude of the fundamental component of the output voltage of this single phase bridge.
- the current waveform shown in FIG. 7(b) is partitioned and labeled as to which of the semiconductorson the lagging side carriers each portion of the current cycle.
- FIG. 7(c) shows the waveforms in the circuit of FIG. 7 (the numerals l,l',4,4', in the figure designate the SCRs, SCR], SCRl', SCR4, SCR4) when a severe overload is applied to the inverter.
- the overload is applied at time one.
- SCRl and SCR4 are in conduction.
- the current rapidly begins to rise.
- the limit level at which the subcycle current control acts.
- the subcycle current control circuit senses that the current in SCRl and SCR4 has reached the limit level, it puts out a pulse (last line of FIG. 7(c)) which causes SCRl' to begin to conduct and SCR4 to extinguish.
- the next half cycle starts, initiated by the normal switching of the leading SCRs, SCRl and 9 SCR4.
- the current is still slightly higher than the limit setting.
- the subcycle current control does not act because the current polarity disagrees with the voltagepolarity. That is, the current is flowing in diodes CR4 and CR1 rather than SCRs, so there is no action from the commutation limit.
- the current reverses after time 3, it does flow in a lagging SCRrBefore the output load current rises 'to the limit setting, the output power transformer in the inverter saturates. This is due to the unsymmetrical voltage applied to this transformer due to the previous short half cycle.
- commutation limit continues to control the action of the lagging side of the inverter to limit SCR current due to the overload, or due to transformer saturation until the overload is removed at time eight. After one more transformer saturation event, the operation of the circuit returns to normal.
- filter impedance must be much smaller than that on a single phase bridge inverter. This allows fault currents to rise rapidly and requires fast action to prevent commutation failures.
- the terminating of one power pulse in a 12 step inverter doesnot snap the output voltage to zero, but merely reduces it somewhat. If the fault is a single .phase fault, only a few sets of thyristors may be overloaded. The voltage contributed to the faulted phase by the other thyristors will cause the current in the overloaded thyristors to continue to rise even after the power pulse is terminated on the overloaded thyristors.
- FIG. 8 there is shown the effect on the output stepped wave when a line-to-line fault is applied on phase A-B.
- the circled number represent the SCRs which are commutated off by the action of the subcycle current control to suppress the output voltage as shown.
- the unlabeled steps are normal steps of the SCR firing pattern.
- the resulting current waveform at the inverter output is also shown on FIG. 8.
- the subcycle current control acts on each SCR when the current in that SCR reaches the limit setting.
- the limit settings are the same number of amperes at each SCR. They appear different when observed as inverter output current because the various SCRs have different turns ratios in their output transformer windings.
- the inverter resumes its normal stepping pattern each time the output current falls below the limit value. Even though the low output current is due to a normal 'zero crossing of the fault current, the inverter tries to resume full output voltage. This is the only way to be able to recover from a fault in much less than a half cycle.
- FIG. 8(a shows one simple implementation of the subcycle current control function.
- FIG. 8(b) is a timing diagram showing wave form during the operation of the circuit of FIG. 8(a).
- the conduction of the four SCRs in the single phase bridge of FIG. 7 is controlled by the Q and 6 outputs of the flip-flops FF 1 and F F2.
- evenly spaced timing pulses control the position of these flip-flps.
- the current signal I exceeds the reference V in positive p0 larity
- a pulse P is generated. If FFl is in the Q position then the limit pulse P will change the position of FF2 to agree with that of FF 1.
- FIG. 8(b) is a timing diagram for the, circuit of FIG. 8(a) and although the operation of circuit of FIG. 8(a) is not set forth in detail herein, the steps of operation thereof are shown in the timing diagram and may be readily understood by those skilled in the art with reference to the description of the paragraph entitled Implementation, immediately above. Obvious Variations
- the subcycle current control approach described herein can also be used in inverters where the single phase inverter which is controlled by subcycle current control does not also vary in timing to control output 1 voltage level.
- the subcycle current control approach
- the reference potential V is not necessarily a fixed potential, but may vary with the commutation capability of the inverter stage (or with any other suitable variable).
- FIG. 9 shows a diagram oscillogram of three phase voltages and currents during a line -to-line fault on phase AB. The detail on the oscillogram is hard to follow so a section of the traces has been redrawn as FIG. l0.'When the fault is applied, the current immediately rises to almost double rated value on phases A and B. Voltage on phases BC and CA is almost undisturbed.
- the subcycle current control depresses output voltage on phase AB to a very low value to control thyristor current while the fuse is melting. After 3.1 milliseconds the fuse melts and begins to arc. The voltage jumps up to the value of the fuse arc drop voltage immediately. After about I millisecond of arcing the fuse current extinguishes. Immediately the disturbance is over; all phase voltages and currents are essentially normal. Note that the duration of the voltage dip was controlled by the fuse, not by the inverter. The inverter is ready to resume full voltage immediately.
- FIG. 1 1 is sketched from oscillographic recordings of a phase A to B line-to-line fault with no fuse or circuit breaker to remove the fault.
- the fault current is limited only by the subcycle current control and peak current reaches twice rated. This current is delivered on the first half cycle of the fault and on all subsequent cycles for the first 0.30 seconds.
- Voltage on phase CA isnormal; that on phase BC is depressed by percent. If the fault had been removed at any time during the initial 0.30 seconds, voltage would have immediately returned to normal.
- any protective fuses or circuit breakers will have opened by 0.30 seconds after the fault. If the overload or fault persists beyond 0.30 seconds, the slow current limit acts to gradually reduce the output voltage of all phases until the current drops low enough to cease action of the subcycle current control.
- FIG. 13 shows a typical trace of voltage and current when the inverter with subcycle fault current control supplies this inrush.
- the first cycle inrush causes the inverter to reduce output voltage for a portion of the cycle. This notch missing from the positive half cycle helps the transformer to center its flux and causes subsequent half cycles to have smaller inrush currents than would have occurred without the notch.
- FIGS. 14 and 15 show diagrammatic records of current and voltage when a KVA 480 V transformer is energized from a utility line and from the 200 KVA inverter with subcycle fault current control.
- FIG. 15 shows the notched voltage waveform and the transformer inrush current peak reduced from 750 amperes on the utility to 350 amperes on the inverter. Note in FIG. 15 that the voltage distortion which is caused by the limiting of inrush current does not affect the peak of any voltage cycle. Thus critical loads which were already connected when this transformer was energized should not have been disturbed by this transient.
- the digitally controlled stepped wave,inverter with subcycle current control is a significant improvement in trouble-free application of UPS systems to critical loads.
- the inverter produces unusually precise power in normal operation and the best possible response in overloads, inrush loads, and faults. In case of a fault, it provides the maximum possible fault current and minimum possible outage time. In case of inrush loads exceeding the inverter capability, it acts to limit the inrush with a minimum degradation of power quality to other loads.
- inverter being characterized as comprising a plurality of single phase sub-inverters whose outputs are combined to form the total inverter output wherein the harmoniccontent of the total inverter output is lower than the output of one single phase sub-inverter, the improvement which comprises:
- an inverter of the type comprising a set of at least two single phase sub-inverters whose outputs are combined to form the total inverter output and, in which, the output of each of the subinverters is of the same frequency but at a different time phase with respect to each other such that the combined output of the sub-inverters has lower harmonic content than the output of a single sub-inverter, and wherein the voltage regulation means of the inverter causes changes in the output waveform of each subinverter such that the waveforms of the subinverters remain substantially identical to each other at all positions of the voltage regulating function, and further wherein, means are provided for producing control signals which control the sub-inverters and the output voltage of each of them, the improvement which comprises:
- means responsive to load faults for limiting instantaneous current in each of the sub-inverters to a predetermined value during load faults, said means being operative, as required, to limit current in one or more overloaded sub-inverter of the set, said means comprising:
- a. electric circuit apparatus operatively connected to each sub-inverter for sensing current at each subinverter
- detection means operatively connected to .the electric circuit apparatus for detecting when the current magnitude of each sub-inverter is approaching the predetermined value
- electric circuit logic means operatively connected to the detection means for modifying the signals controlling the sub-inverters such as to cause the output voltage of the sub-inverters to be changed in a manner tending to reduce any overcurrent in the one or more sub-inverters in which there is an overcurrent resulting from a load fault.
- inverter whose unfiltered output waveform contains no harmonics lower than the 11th, said inverter being further characterized as comprising at least one three phase transformer having primary and secondary windings, and a set of six single phase subinverters whose outputs are combined to form the'total inverter output, the improvement which comprises:
- each current transformer being operatively connected to a sub-inverter and each being operatively connected in circuit with the primary winding of the three phase transformer associated with each sub-.
- inverter for sensing current at each sub-inverter in the circuit of the primary winding in each subinverter
- the inverter being regulated by vector addition at the three phase transformer primary windings thereof, said inverter being further characterized as comprising a set of six single phase sub-inverters whose outputs are combined to form the total inverter output which appears across the output terminals of the three phase secondary windings of the transformer, the improvement which comprises:
- each current transformer bieng operatively connected to a sub-inverter and each being operatively connected in circuit with the primary winding of the three phase transformer associated with each subinverter for sensing current at each sub-inverter in the ciruit of the primary winding in each subinverter;
- detector means operatively connected to each current transformer means for detecting when the current magnitude of each subinverter is approaching the predetermined value
- electric circuit logic means operatively connected to the detector means for modifying the output voltage of the sub-inverters in a manner which reduces any overcurrent in the one or more sub-inverters in which there is an overcurrent resulting from a load fault.
- an inverter of the type comprising a set of at least two single phase sub-inverters whose outputs are combined to form the total inverter output and which includes a multiphase transformer having primary and secondary windings and means to limit the instantaneous current of thesub-inverters to a predetermined value in the event of a load fault, which load fault if reflected as an overload in one or more of the sub-inverters, the improvement which comprises: i i
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US22863272A | 1972-02-23 | 1972-02-23 |
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US9477568B2 (en) | 2013-09-27 | 2016-10-25 | International Business Machines Corporation | Managing interconnect electromigration effects |
US9735616B2 (en) | 2014-03-13 | 2017-08-15 | General Electric Company | Systems and methods for providing increased fault current capability in uninterruptible power supply systems |
WO2022167863A1 (en) * | 2021-02-04 | 2022-08-11 | Abb Schweiz Ag | Inrush current limiting transformer energization apparatuses, methods, systems and technique |
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Cited By (31)
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US3875491A (en) * | 1972-07-26 | 1975-04-01 | Bbc Brown Boveri & Cie | Arrangement for supplying multi-phase electric power consumers by means of converters |
US3838330A (en) * | 1973-04-13 | 1974-09-24 | Westinghouse Electric Corp | Arrangement and method for converting electrical power without external supply of reactive power requirements |
US3932764A (en) * | 1974-05-15 | 1976-01-13 | Esb Incorporated | Transfer switch and transient eliminator system and method |
US4032832A (en) * | 1975-07-14 | 1977-06-28 | Bunker Ramo Corporation | Dc to ac inverter with unregulated input and regulated output |
US4475150A (en) * | 1982-04-28 | 1984-10-02 | General Electric Company | Coordinated load commutated inverter protection system |
US4618810A (en) * | 1983-02-04 | 1986-10-21 | Emerson Electric Company | Variable speed AC motor control system |
US4956762A (en) * | 1989-01-13 | 1990-09-11 | S-V Technology, Inc | Controlled switched bridge-based power reconfiguring apparatus |
US5508905A (en) * | 1992-08-06 | 1996-04-16 | Metropolitan Pump Company | Low distortion variable output power supply |
US5434479A (en) * | 1992-09-22 | 1995-07-18 | Matsushita Electric Works, Ltd. | Full-bridge inverter for discharge lamp lighting device with varied transistor zero voltage period |
US6560128B1 (en) * | 1999-02-12 | 2003-05-06 | Satcon Power Systems Canada Ltd. | Ferroresonance-suppressing static transfer switch |
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US20040125523A1 (en) * | 2002-12-31 | 2004-07-01 | John Edwards | Fault-tolerant three-level inverter |
US7145268B2 (en) * | 2002-12-31 | 2006-12-05 | The Boeing Company | Fault-tolerant three-level inverter |
US20110109465A1 (en) * | 2008-04-03 | 2011-05-12 | Siemens Aktiengesellschaft | Method and arrangement for generating an error signal |
US8462004B2 (en) * | 2008-04-03 | 2013-06-11 | Siemens Aktiengesellschaft | Method and arrangement for generating an error signal |
US20130265806A1 (en) * | 2010-12-16 | 2013-10-10 | Nanjing Hurricane Electric Control Automation Equi pment Manufacturing Co., Ltd | Intelligent power control unit for low voltage ride through and its application |
CN103843226B (en) * | 2011-09-28 | 2018-04-10 | 伊顿公司 | The AC power supplies apparatus and method of variable voltage waveform are provided under the conditions of load transient |
US9166445B2 (en) | 2011-09-28 | 2015-10-20 | Eaton Corporation | AC power supply apparatus and methods providing variable voltage waveforms for load transient conditions |
CN103843226A (en) * | 2011-09-28 | 2014-06-04 | 伊顿公司 | Ac power supply apparatus and methods providing variable voltage waveforms for load transient conditions |
WO2013049285A3 (en) * | 2011-09-28 | 2013-07-18 | Eaton Corporation | Ac power supply apparatus and methods providing variable voltage waveforms for load transient conditions |
US9146597B2 (en) | 2011-11-03 | 2015-09-29 | International Business Machines Corporation | Minimizing aggregate cooling and leakage power with fast convergence |
US9141159B2 (en) | 2011-11-03 | 2015-09-22 | International Business Machines Corporation | Minimizing aggregate cooling and leakage power with fast convergence |
US20140021790A1 (en) * | 2012-07-23 | 2014-01-23 | Cyber Power Systems Inc. | Method for controlling output waveforms of an uninterruptible power supply |
US9268347B2 (en) | 2013-02-12 | 2016-02-23 | International Business Machines Corporation | Implementing dynamic regulator output current limiting |
US9477568B2 (en) | 2013-09-27 | 2016-10-25 | International Business Machines Corporation | Managing interconnect electromigration effects |
US9735616B2 (en) | 2014-03-13 | 2017-08-15 | General Electric Company | Systems and methods for providing increased fault current capability in uninterruptible power supply systems |
EP2980959A1 (en) * | 2014-07-30 | 2016-02-03 | General Electric Company | Systems and methods for exploiting current capability in static ups |
US10135237B2 (en) | 2014-07-30 | 2018-11-20 | Abb Schweiz Ag | Systems and methods for exploiting current capability in static ups |
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