US3654612A - Display system using a cathode-ray tube - Google Patents

Display system using a cathode-ray tube Download PDF

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Publication number
US3654612A
US3654612A US22639A US3654612DA US3654612A US 3654612 A US3654612 A US 3654612A US 22639 A US22639 A US 22639A US 3654612D A US3654612D A US 3654612DA US 3654612 A US3654612 A US 3654612A
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United States
Prior art keywords
counter
display
logical operation
cathode
ray tube
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US22639A
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Katsuhiko Ohara
Kazuchiyo Matsuzawa
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Takachiho Koheki KK
Unisys Corp
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Takachiho Koheki KK
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Assigned to BURROUGHS CORPORATION reassignment BURROUGHS CORPORATION MERGER (SEE DOCUMENT FOR DETAILS). DELAWARE EFFECTIVE MAY 30, 1982. Assignors: BURROUGHS CORPORATION A CORP OF MI (MERGED INTO), BURROUGHS DELAWARE INCORPORATED A DE CORP. (CHANGED TO)
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/06—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows
    • G09G1/14—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data using single beam tubes, e.g. three-dimensional or perspective representation, rotation or translation of display pattern, hidden lines, shadows the beam tracing a pattern independent of the information to be displayed, this latter determining the parts of the pattern rendered respectively visible and invisible
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
    • G06F3/153—Digital output to display device ; Cooperation and interconnection of the display device with other functional units using cathode-ray tubes

Definitions

  • ABSTRACT [30] F reign Application Pri it D t A display system for displaying information patterns on the screen of a cathode-ray tube obtained in a logical operation M31. 29, 1969 Japan device, such as a calculator where counters and registers r commonly used for both the logical operation of the logical [52] US.
  • Display systems of this type can display a large amount of information and have a display screen which is within the field of view of the operator.
  • the cost of the display system of this type is higher than the price of other display systems using indicator tubes, such as a Nixie tube.
  • display systems of this type are usually employed in more sophisticated calculators, whose high prices may be attributed to the following reasons.
  • registers and counters used solely for the display operation are provided to eliminate disturbances and fluctuations of patterns displayed on the screen of the cathode-ray tube.
  • deflecting circuits for the cathode-ray tube comprise direct-coupling amplifiers.
  • these direct-coupling amplifiers are necessarily provided to eliminate drift, with complicated compensation circuitry for eliminating fluctuations by deviation of temperature(i.e., a temperature-compensating network). Accordingly, the deflecting circuits become expensive.
  • An object of this invention is to provide a display system using cathode-ray tube for a logical operation device capable of reduction to practice by the use of a set of counters and registers commonly used for the logical operation and the display operation in an alternately switched manner.
  • Another object of this invention is to provide a display system using a cathode-ray tube for logical operation device capable of displaying patterns necessary for the logical operation by the use of non-direct-coupled deflection-amplifiers without fluctuation and disturbance of the displayed pattern.
  • standard pattern signals each indicative of a predetermined standard pattern
  • necessary'patterns relating to logical operations performed by the use of counters and registers are displayed on the screen of a cathode-ray tube by blanking the respective standard pattern signals so as to obtain the necessary patterns.
  • the aforementioned counters and registers are commonly employed for the display operation and the above-mentioned logical operation, and the display function of the cathode-ray tube is interrupted during the period of the logical operation.
  • the direct-current voltages applied respectively to the deflection amplifiers at the logical operation time are respectively adjusted so as to be equal to the respective average DC value of the voltages applied to the deflection amplifiers at the display time.
  • the generating time of each of the standard pattern signals is determined so as to be shorter than a display time for a unit displayed pattern and so as to be slightly delayed from the start of the display time.
  • FIG. 1 is a block diagram illustrating an embodiment of this invention
  • FIG. 2 is block diagram illustrating an example of control means for counters in the system of this invention
  • FIG. 3A is a diagram explanatory of a standard pattern used in the system of this invention.
  • FIG. 3B shows patterns indicative of numerals which are displayed in the system of this invention
  • FIG. 3C shows time charts explanatory of slope waves used in the system of this invention
  • FIG. 4A is a circuit diagram illustrating an example of an adder used in the system of this invention.
  • FIG. 4B shows time charts explanatory of the logical operation time and the display time in the system of this invention
  • FIGS. 5A, 5B, 5C, SD, SE and SF are time charts explanatory of the operations of the system of this invention
  • FIG. 6 shows time charts explanatory of the operations of the system of this invention at the logical operation mode
  • FIGS. 7A and 7B show time charts explanatory of the operations of the system of this invention at an instant when the operation mode of the system is switched from the logical operation to the display operation.
  • the operation of the system of this invention is started by controlling a keyboard 5 to instruct a control circuit 1 to control counters 2, 3 and 4 so as to perform logical operations and display operations.
  • the counter 2 is a scale-of-four counter
  • the counter 3 a scale-of-ZO counter
  • the counter 4 a scale-of-l6 counter.
  • Input data are applied from the keyboard 5 to a register 9 under control of the counters 2, 3 and 4 to store the input data in the register 9.
  • a register 6 is a memory for temporarily storing necessary data.
  • Each of these registers 6, 7 and 8 has a capacity of 16 bits.
  • a vertical slope wave W and a horizontal slope wave W are at first generated, by the use of the output pulses of the counter 3, at a vertical slope generator 11 and a horizontal slope generator 12 respectively as standard pattern signals which are successively generated and each representative of a standard pattern shown in FIG. 3A.
  • the output pulses of the counter 3 are synchronized with successive changes of the counting state of the counter 3.
  • the vertical slope wave W is applied through a buffer amplifier 15 to a V-adder 20 and added to a vertical step wave w of four steps which is generated at a vertical step generator 14 in response to the output pulses of the counter 2.
  • the vertical step wave W is employed to successively switch lines of the displayed pattern of numerals.
  • the horizontal slope wave W is applied through a buffer amplifier 17 to a H-adder 22 and added to both the vertical slope wave w applied through a buffer amplifier l6 and a horizontal step wave w of 16 steps which is generated at a horizontal step generator 18 in response to the output pulses of the counter 4.
  • These output pulses of the counter 4 are synchronized with successive changes of the counting states of this counter 4.
  • the horizontal step wave w is employed to switch digits of the displayed pattern of numerals.
  • the vertical slope wave w, applied to the l-l-adder 22 is employed to incline the displayed patterns of numerals with respect to the vertical direction of the displayed pattern.
  • the output of the V-adder 20 and the output of the I-l-adder 22 are applied to deflection coils of a cathode-ray tube 27 through a vertical signal amplifier 25 and a horizontal signal amplifier 26 respectively to display standard patterns on the screen of the cathode-ray tube 27 without blanking signals.
  • the contents of the registers 6, 7, 8 and 9 are successively read out, for one digit of four bits, to a buffer register 10 from the least significant bit positions of each register and applied to a decoder 13, in which each digit read out is decoded.
  • the decoded output of the decoder 13 is applied to a read-only memory 19 storing blanking signals, so that one of the stored blanking signals corresponding to the decoded output of the decoder 13 is applied from the readonly memory 19 to a blanking circuit 23.
  • This blanking circuit 23 controls the cathode-ray tube 27 to blank the unnecessary parts (shown by dotted line in each numeral pattern in FIG. 3B) of the above-mentioned standard pattern so as to obtain a pattern of numeral (shown in FIG. 3B) corresponding to the digits read out from of the registers 6, 7, 8 or 9.
  • the displayed patterns of numerals are disturbed or fluctuated at the switching instant from the logical operation time 1,, to the display time t due to the time constants of the deflection circuits (25 and 26) and the deflection coil of the cathode-ray tube 27.
  • a signal DISPLAY (W) shown in FIG. 4B is applied to an inverter 21 to obtain a signal DISPLAY (W6) shown in FIG. 4B.
  • the signal w is applied to both the V-adder 20 and the H- adder 22 to maintain, at respective stable values, the respective direct-current average voltages of the inputs of the horizontal signal amplifier 26 and the vertical signal amplifier 25 at both the logical operation time t and the display time t Moreover, the starts of the slope waves w, and W2 are delayed by four clock pulses from the start of a display time t, for a displayed unit-pattern, so that a digit to be displayed at a just-succeeding digit display time 2,, is read out to the buffer register from one of the register 6, 7, 8 and 9.
  • the signal DISPLAY (W5) and its inverted signal DISPLAY (w are applied to the adders 20 and 22 so as to maintain, at respectively stable values, the respective average DC value of voltages of the inputs of the horizontal signal amplifier 26 and the vertical signal amplifier 25 at both the logical operation time t and the display time t and that a digit to be displayed at a succeeding digit display time t, is read out to the buffer register 10 at the delayed time t, (e.g., a time of four clock pulses) to eliminate the effect caused by the time constant of the deflection circuit of the cathode-ray tube 27.
  • the delayed time t e.g., a time of four clock pulses
  • AND gates G, and G and an OR gate OR are provided at the input side of the counter 2 (i.e., a scale-of-4 counter).
  • the signal DISPLAY (W5), clock pulses CP, and the carry outputs of the counters 3 and 4 are applied from terminals T, and T and counters 3 and 4 respectively.
  • the signal DISPLAY (W6) and a first counting pulse train P are applied from terminals T and T.,.
  • the outputs of the AND gates G, and G are applied to the counter 2 through the OR gate OR,.
  • AND gates G and G, and an OR gate 0R are provided.
  • the signal DISPLAY (W5) and the clock pulses C? are applied from the terminals T, and T respectively.
  • the signal DISPLAY (W5) and a second counting pulse train P are applied from the terminal T and a tenninal T
  • the outputs of the AND gates G and G are applied to the counter 3 through the OR circuit OR,.
  • the counter 4 i.e., a scale-of 16 counter
  • AND gates G and G and an OR circuit 0R are provided.
  • the signal DISPLAY (W5), the clock pulses CP and the carry output of the counter 3 are applied from the terminals T, and T and the counter 3 respectively.
  • the signal DISPLAY (w and a third counting pulse train P are applied from the terminal T, and a terminal T
  • the outputs of the AND gates G and G are applied to the counter 4 through the OR gate OR,,.
  • the above-mentioned AND gates G,, G G 6,, G and G the OR circuits OR,, CR and CR and the terminals T T T T.,, T and T are provided in the control circuit 1 shown in FIG. 1.
  • the carry pulses of the counter 2 are applied to the terminal T, as the second pulse train P in the control circuit 1.
  • the number of pulses of the second pulse train P is counted by the counter 3.
  • serial date obtained at the outputs of the registers 6,7,8 and 9 at the counting state are determined as a first digit.
  • serial date obtained at outputs of the registers 6,7 ,8 and 9 at the counting state are determined as a 16th digit.
  • the counter 4 is employed for counting the number of shifts so as to detect how many digits are shifted in the registers from lower to higher. Accordingly, the pulse train P, is applied to the terminal T from the control circuit 1 when the number of shifts is to be detected.
  • FIGS. 7A and 7B show the clock pulses CP, states of the counters 2,3 and 4 and the signal DISPLAY (W5) at an instant when the operation mode of the system is switched from the logical operation time t to the display operation time ID.
  • the scaIe-of-ZO counter 3 counts the clock pulses CP applied through the AND gate 6,, opened by the signal DIS- PLAY (W5).
  • carry pulse of the counter 3 indicates the play for one digit.
  • the carry output of the counter 3 is applied to the AND gate G together with the signal DISPLAY (W5) and the clock pulses CP. Accordingly, the scale-of-16 counter 4 counts the number of digits displayed by counting the number of carry pulses of the counter 3. Accordingly, the count-up of the counter 4 indicates the completion of display for sixteen digits displayed in one line of the displayed pattern.
  • the carry output of the counter 4 is applied to the AND gate G together with the signal DISPLAY (W5), the clock pulses CP and the carry output of the counter 3. Accordingly, the scale-of-4 counter 2 counts the number of lines of the displayed pattern by counting the number of carry pulses of the counter 4.
  • the four counting states of the counter 2 are employed for designating respectively the registers 9, 8, 7 and 6 to be read out to the buffer register 10. Accordingly, a carry pulse of the counter 4 indicates the completion of display for four lines of the displayed pattern.
  • the lines of displayed pattern are switched successively in response to each of the carry pulses of the counter 4.
  • the bias potential in the vertical completion of dissignal applied from the vertical signal amplifier 25 to the cathode-ray tube 27 must be deviated, by a large deviation voltage, in response to each of successive switching of the displayed lines.
  • a bias current flowing through the vertical deflection coil of the cathode-ray tube is deviated, by a large deviation current, in response to successive switching of the displayed lines. This deviation current has the largest value at the switching from the highest line to the lowest line of the displayed pattern.
  • the step change of the bias current cannot be perfectly carried out due to transient by the time constant of the deflection circuit and the delay of change of a current flowing through the vertical deflection coil. Accordingly, numerals displayed at the beginning part of the switched line are disturbed and fluctuated by the above-mentioned transient at the switching to the next line. To eliminate these undesirable phenomena, the slope waves W and w are generated after four clock pulses from the switching instant changed to the next line of the displayed pattern. Moreover, four bits of information can be transfered to one of the registers 6, 7, 8 and 9 to the buffer register 10 at the time t, of four clock pulses.
  • the counters 2, 3 and 4 and the registers 6, 7, 8 and 9 are commonly used both for the logical operation and for the display operation in the system of this invention. Accordingly, the patterns are not at all displayed on the screen of the cathode-ray tube 27 at the keying operation of the keyboard 5 for instructing data to the calculating means illustrated in FIG. 1 by chain lines or at the logical operation in the above-mentioned calculating means.
  • the system is so designed that the logical operation time is shorter as far as possible, an operator can manipulate this system without embarrassment since the blanking time of the displayed pattern becomes very short.
  • each of the adders and 22 are constructed as shown in FIG. 4A by way of example.
  • the adder 22 is mainly described.
  • the adder 20 is similar, in principle, to the adder 22.
  • the adder 22 comprises an ADDER-l and and ADDER-Z.
  • the ADDER-l comprises a diode D,, resistors R, and R connected together to a common junction .1, to combine the signal DISPLAY (W8) supplied from a terminal T (connected to the inverter 21), the horizontal step wave w applied from a terminal T (connected to the horizontal step generator 18) as shown in FIG. 5A, and the horizontal slope wave w, applied from a terminal T (connected to the buffer amplifier 17).
  • the output of the buffer amplifier 16 is applied to the common junction J 1 through a resistor.
  • this connection means is not shown in FIG. 4A for simple illustration.
  • the signal DISPLAY (W5) assumes zero volt (0 V) at the display time t and a predetermined plus voltage VV) at the logical operation time t as shown in FIG. 4B.
  • the combined output of the ADDER-l is further combined with the signal DIS- PLAY (w supplied from a terminal T (connected to the input of the inverter 21) at the ADDER-2 which comprises a resister R and a series-connection of a diode D and a resistor R The resistor R and the series-connection are connected together to a common junction J
  • the signal DISPLAY (w assumes zero volt (0 V) at the display time n; and a predetermined minus voltage VV) at the logical operation time 1,, respectively.
  • 5C is also obtained at the output of the ADDER-Z at this display time r If the condition of the system is changed from the display time to the logical operation time t under control of the control circuit I started in response to the keying of any key on the keyboard 5, the signal DISPLAY (w assumes the voltage +VV as shown in FIGS. 58 and 5D since the diode D becomes conductive. Accordingly, the output of the ADDER- 1 assumes the voltage +VV as shown in FIG. 5D. On the other hand, the output of the ADDER-2 assumes a constant voltage determined by the resistances of the resistors R and R as shown in FIG.
  • a display system for displaying an information pattern in a logical operation device comprising:
  • a keyboard for generating instructions of an operation mode of a logical operation device
  • counters for performing said logical operation in accordance with said instructions comprising a first counter for generating a first timing pulse train and carry pulses, a second counter for generating carry pulses and a second timing pulse train timed with each digit of the displayed pattern by stepping said carry pulses of the first counter, and a third counter for generating a third timing pulse train timed with each line of the displayed pattern by stepping said carry pulses of the second counter,
  • a plurality of registers for temporarily storing digital information indicative of process results of said logical operatron, means for switching the inputs of said counters, means for generating a vertical slope wave in response to the first timing pulse train, means for generating a horizontal slope wave in response to the first timing pulse train,
  • a first adder for combining the vertical step wave with the vertical slope wave
  • a cathode-ray tube comprising vertical deflection means, horizontal deflection means, and a brightness modulation means
  • a vertical signal amplifier of a non-direct coupling type for amplifying the output of said first adder for application to the vertical deflection means of the cathode-ray tube
  • horizontal signal amplifier of a non-direct coupling type for amplifying the output of the second adder for application to the horizontal deflection means of the cathode-ray tube
  • buffer register for temporarily storing one digit read out 25 from any of said registers within a predetermined time synchronized with pulses of the first timing pulse train
  • a display system in which four of said registers are to store four lines of said displayed pattern, and the third counter is used as a scale-of-four counter.
  • a display system in which the first counter is a scale-of-20 counter with which the first four counting states are employed to read out said one digit to the buffer register, the next thirteen counting states are employed for generating the vertical slope wave and the horizontal slope wave, and the last three counting states are employed as an idle time.
  • a display system in which the second counter is a scale-of-n counter, so that n digits are displayed on one line of the displayed pattern.
  • an improvement comprising: counters and registers used in common for both a logical operation of the logical operation device and the display operation of the system, means for alternately switching said counters and registers between periods of the logical operation and the display operation, means for maintaining the average voltages of respective inputs of a vertical signal amplifier and a horizontal signal amplifier for the cathode-ray tube at stable values in both the period of logical operation and the period of the display operation, means for delaying, by a predetermined time, start of slope waves for each digit from the start of a digit display time, and means for temporarily storing digital information indicative of a just-succeeding displayed digit in said predetermined time, whereby disturbance and fluctuation of the displayed pattern at an instant when the operation mode of the system is switched from the logical operation to the display operation are effectively eliminated.

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US22639A 1969-03-29 1970-03-25 Display system using a cathode-ray tube Expired - Lifetime US3654612A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3818457A (en) * 1971-10-20 1974-06-18 Walther Bueromasch Gmbh Data processing unit having a digital readout indicator

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US2931022A (en) * 1954-06-16 1960-03-29 Ibm Spot sequential character generator
US3248725A (en) * 1961-02-21 1966-04-26 Ibm Apparatus for displaying characters as a sequence of linear visible traces
US3320595A (en) * 1964-06-16 1967-05-16 Burroughs Corp Character generation and control circuits
US3403286A (en) * 1966-12-27 1968-09-24 Ibm Digital cathode ray tube deflection system
US3419750A (en) * 1965-07-28 1968-12-31 Air Force Usa Constant rate incremental positioning circuit for crt x-y plotter display
US3453601A (en) * 1966-10-18 1969-07-01 Philco Ford Corp Two speed arithmetic calculator
US3476973A (en) * 1968-01-15 1969-11-04 Ibm Display system
US3479553A (en) * 1967-09-22 1969-11-18 Burroughs Corp Deflection amplifier
US3479552A (en) * 1968-06-04 1969-11-18 Wyle Laboratories Deflection circuits
US3483425A (en) * 1967-08-31 1969-12-09 Burroughs Corp Controlled-bias current amplifier
US3488551A (en) * 1966-09-23 1970-01-06 Raytheon Co Magnetic deflection amplifier with circuit accommodating for the back emf

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US2931022A (en) * 1954-06-16 1960-03-29 Ibm Spot sequential character generator
US3248725A (en) * 1961-02-21 1966-04-26 Ibm Apparatus for displaying characters as a sequence of linear visible traces
US3320595A (en) * 1964-06-16 1967-05-16 Burroughs Corp Character generation and control circuits
US3419750A (en) * 1965-07-28 1968-12-31 Air Force Usa Constant rate incremental positioning circuit for crt x-y plotter display
US3488551A (en) * 1966-09-23 1970-01-06 Raytheon Co Magnetic deflection amplifier with circuit accommodating for the back emf
US3453601A (en) * 1966-10-18 1969-07-01 Philco Ford Corp Two speed arithmetic calculator
US3403286A (en) * 1966-12-27 1968-09-24 Ibm Digital cathode ray tube deflection system
US3483425A (en) * 1967-08-31 1969-12-09 Burroughs Corp Controlled-bias current amplifier
US3479553A (en) * 1967-09-22 1969-11-18 Burroughs Corp Deflection amplifier
US3476973A (en) * 1968-01-15 1969-11-04 Ibm Display system
US3479552A (en) * 1968-06-04 1969-11-18 Wyle Laboratories Deflection circuits

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3818457A (en) * 1971-10-20 1974-06-18 Walther Bueromasch Gmbh Data processing unit having a digital readout indicator

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