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Video display apparatus

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US3643252A
US3643252A US3643252DA US3643252A US 3643252 A US3643252 A US 3643252A US 3643252D A US3643252D A US 3643252DA US 3643252 A US3643252 A US 3643252A
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means
row
display
characters
memory
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Richardson S Roberts Jr
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ULTRONIC SYSTEMS CORP
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ULTRONIC SYSTEMS CORP
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    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/007Circuits for displaying split screens
    • GPHYSICS
    • G09EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09GARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/34Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
    • G09G5/343Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a character code-mapped display memory

Abstract

Coded characters from a plurality of input sources are stored in different intervals of a recirculating memory, each interval containing the characters for a row of the display. Characters for a display row are loaded into buffer register means which is then recirculated and the contents encoded during successive recirculations to produce signals representing the portions of the characters to be displayed on respective lines of the display row. Information from one source is displayed in the plurality of rows which are upshifted to rows thereabove and new information displayed in the bottom row, by delaying the vertical sweep relative to said encoding during upshift. Information from another source is displayed in rows which do not upshift, by delaying the decoding so that it remains unchanged with respect to the vertical sweep.

Description

hid Mates Water Roberts, iii, 11 1210. 115, 11972 [54] i /111511 21111 iiliiiSiPiLfiiY AsPiFfiiiEi/h'ifiilfi 3,487,308 12/1969 Johnson .340/324 [72] Inventor. islnvcghurdsou ikoheriis, 11s., Cherry H111, Primary Emmmwwjohn W. C 81 dwell Assistant Examiner-Marshall M. Curtis [73] Assignee: 1J1hronic Systems Corp, Mount Laurel, AltOrney-Th$OdOfe Ja Jr, and N rm n J OMan NJ. 22 Filed: Aug. 11, 1%? [571 AEWMCT [21] Appl. N05 6516M, Coded characters from a plurality of input sources are stored 1111 different intervals of a recirculating memory, each interval containing the characters for a row of the display. Characters [52] ILLS. 1C1 "lid WEN A, 178/75 D, 340/154 f a display row are w d into b ff register means which is [51] (W911i 3/14} then recirculated and the contents encoded during successive [58] Ii ieid off fiesireh ..l78/7.5 1D, 6, 6.8; 340/3241, recirculations to produce Signals representing the portions of 340/152 154 the characters to be displayed on respective lines of the display row. information from one source is displayed in the plu- [56] Meflwmms 0mm rality of rows which are upshifted to rows thereabove and new UNITED STATES PATENTS information dispiayed in the bottom row, by delaying the vertlcal sweep relative to said encoding during upshift. 1nforma- {ion from another source is in rows do not 3,426,344 2/ 1969 Clam 340/324 upshift, by delaying the decoding so that it remains unchanged 1 Wel'me respect to the ertical weep 3,453,384- 7/1969 Donner et a1.'..... ....340/324.1 3,439,218 4/1969 Savinese et a1. ..315/18 311 diliaims, 21 Drawing, Figures s NEW YOAA ,3- E0, i 8 52 I fiac x (a w 8 1% i la %9 2374 i 9 $3 I a I; I flMm/m/v .9 1 I0 E i i 4 W i my FNG w 1 g 6622 x22 5 r5 1 .QrE i z 6 ,E 1 I [-5 I; l r 7 F3 #7 77/2 MoMEA f w 4 5 I a I 5) THIS WMAE' 1 c? 2 I l 9 13 1 QWV fx zcr E -21 l 1W9 00 NOT 1 5 17 i 1/ I}? IEVE/V 71-7005 -J 5 5Z 1 i /a 5L fffli w 111:1: :1: 1: 11:11-55 :1 6 as M5 6 m w 7 PATENTEDFEB 15 I972 SHEET OZUF 16 WK Wk 19* mi EPSdBPZEZ PMENTEUFEB 15 I972 SHEET OBUF i6 PAIENTEDFEB 15 1972 SHEET Wm 16 SHEET 05 [1F 16 PATWEDFEB 15 I972 PAIENTEDFEB 15 m2 SHEET 07 [1F 16 PATENTEDFEB 15 1972 SHEET 12 0F 16 l i m 3 2 as: w m wwawwwwws mm wns, a:

7 14 did MWNEY-5 lll 1 m wk E E E I fiea a w gma a QR m sts gm 3 sum IBOF 1e PATENTED EB 1 5 I972 VlllDlEU DllSlPlLAY APPARATUS BACKGROUND OF THE INVENTION This invention relates to video display apparatus for receivin g information in the form of coded characters and displaying it on a television-type display unit. it is particularly useful for the display of stock market quotations and like information, along with news or general market information.

Quotations on stocks, bonds, commodities, etc., are now commonly available by coded ticker tape transmissions from stock exchanges and other commercial sources. Teletype service is also available from commercial sources giving news and other information of interest to stockbrokers, investors, etc., Different types of equipment are used for the display of this information, including paper tape recorders, Teletype equipment, quotation boards and television-type display equipment.

The present invention is directed to television-type display equipment and provides means for storing information to be displayed and developing corresponding video signals which yield a highly satisfactory and legible display, and which can accommodate both quotation and news broadcasts with provision for independently changing the displayed information in a manner appropriate to each.

SUMMARY OF THE lNVENTlON In accordance with the invention a recirculating memory is supplied with coded characters from one or more input sources. The memory stores the characters in memory row intervals each containing the characters for a row of the display. The characters in different memory row intervals are successively loaded into a row buffer register means which is recirculated between successive loadings thereof to yield outputs during a plurality of cycles corresponding to a plurality of display line sweeps. Advantageously, the row buffer register means comprises a plurality of registers loaded in bit-parallel, character-series form, each register containing like-order bits of the characters. The outputs are supplied to a display character encoder which produces signals iine-by-line representing the portions of the characters to be displayed on respective scanning lines of a display row. Advantageously the characters are formed by dots on each scanning line, a predetermined number of dots and lines being allocated to a character and used as required. The output of the encoder is used to form a video signal, and preferably line and field synchronizing signals are incorporated therein to enable conventional television video monitors to be used as display units.

For news broadcasts and the like, a plurality of display rows are employed and the characters entered at the bottom of the display and upshifted to a higher row as a new row is written. This is accomplished by producing a relative delay of the display field sweep with respect to the line-by-line encoding of the characters in the rows to be upshifted, the delay being one scanning line per field for a number of fields equal to the line spacing of the rows in which information is displayed.

The upshift cycle is initiated by a signal indicating that a new row of characters is to be displayed. if characters arrive during the course of an upshift cycle, they are entered in an entry memory row interval occurring after the memory interval that contains characters for the normally lowest display row. They are then read out of the recirculating row buffers and encoded for a normally hidden display row, and upshiftecl to the normally lowest display row as the characters in that row are upshifted to the row above.

As the upshift cycle is completed, the relative timing of the memory row intervals and the field synchronization is changed so that information in the memory row intervals is loaded into and read out of the row buffers for the display rows to which the respective information has been upshifted. Additional new characters are then entered into the memory in the row interval allocated to the normally lowest display row, until the row is completed.

Advantageously the delay between the input and output of the recirculating memory is equal to one-half a display field period, and memory row intervals allocated to information for display rows in the upper half of the display are interleaved with intervals allocated to information for display rows in the lower half. The total number of memory row intervals is an odd integer. Thus the row characters in alternate intervals may be loaded into the buffer registers and the intervals therebetween are available for buffer recirculation, readout and line-by-line encoding.

if desired, the entire display may be devoted to rows which are upshifted as new rows are written. However, the present invention particularly contemplates upshifting only part of the display, without upshifting the other part, This enables information from two or more sources to be displayed at different parts of the display screen, and one part changed independently of the other. 1

Thus, for example, the upper half of the display may be arranged not to be upshifted, and devoted to stock quotations and the like. These may be written from left to right, and new quotations entered at the left of the same row with erasure of the old. Or, stock indices in tabular form may be displayed as long as desired. The lower half of the display may be devoted to news broadcasts and the like, and upshifted as required to display new rows.

For this operation, coded characters from a plurality of input sources are entered into the recirculating memory in different memory row intervals corresponding to display rows in different parts of the display. For'example, Teletype news broadcasts may be entered into a memory row interval corresponding to the normally lowest display row, or an entry memory row interval during an upshift cycle, as described above. The display rows in the lower half of the display may be devoted to these broadcasts and will be filled upon successive upshifts. After all rows are filled, information in the uppermost row disappears during the next upshift cycle and is replaced by that in the next lower row, and new information appears in the bottom row. Quotations from the New York and American stock exchanges may be written in the upper half of the display, and replaced as required without regard to the upshifting of the lower half.

To prevent upshifting of the upper half during upshift of the lower, provision is made to delay the row buffer recirculation, readout and encoding of the corresponding row information by amounts equal to the delay of the field sweep during an upshift cycle. Then, after the upshift cycle, the information is relocated in the memory so that it thereafter occurs at the memory output at the proper time with respect to the vertical sweep to be displayed in the same rows as previously.

Stock quotations have letters identifying a stock, followed by figures giving the quotation. It is desired to have the letters displayed in one row and the figures in the next lower row. To accomplish this, the row buffers are recirculated a number of times corresponding to two rows of the display. The characters include letter and figure-identification, and are recognized to control the encoding. During the recirculation the encoder first produces line-by-line outputs for the letters and then lineby-line outputs for the figures.

Further features of the invention, and specific means for carrying out the above operations, will be described hereinafter in connection with the specific embodiment.

BRTEF DESCRIPTION OF THE DRAWlNGS FlG. ll illustrates a display in accordance with the invention, and HG. Ila illustrates the dot character formation;

F IG. 2 is a simplified overall block diagram of the apparatus;

H65. 3, Fla and d show the input channels in detail;

lFlGS. 5 and h show the recirculating memory and control, and the recirculating buffers and control;

FIGS. '7 and h show the timing arrangements, including upshift;

lFllGS. and Ni show the manner of generating signals used in other figures;

FIG. 11 shows the character encoder and video output arrangement;

FIG. 12 is explanatory of signal storage and readout during normal and upshift cycles; and

FIGS. 13-19 illustrate waveforms used in preceding figures.

DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 illustrates the type of display on the face of the television picture tube. The upper half of the display is for stock information, such as quotations obtained from the New York Stock Exchange (NYSE) and American Stock Exchange (AMEX) ticker tapes. The lower half is for news and other information obtained, for example, over a teletype line.

The number of scanning lines, number of rows of display information, and field repetition rate may be selected to meet the requirements of a particular application. In this embodiment a 60 Hz. (Hertz) field frequency with 260 lines per field is employed so'that conventional television monitors can be used for display. However, interlacing is not used. The 260 lines are divided into 26 rows of IO lines each. These numerical values will be used hereinafter for convenience, although it will be understood that they can be changed if desired.

As indicated at the left margin, the 26 rows are divided into 13 S-rows alternating with 13 R-rows. In the lower half of the picture the S-rows correspond to memory and the R-rows to readout. In the upper half this is not always true.

At the right margin the order in which information is stored in the'recirculating memory is indicated. It will be noted that memory sections 1,2,3, etc., are interleaved with memory sections 8,9,10, etc., and that the memory'cycle occurs twice during a field period. Fixed titles New York" and American" are displayed in rows S1 and R3 with dividing lines 20 to separate the titles from the displayed information. Although the title and line information could be stored in the memory, in this embodiment separate title and line generators are employed for the purpose. The NYSE information is displayed in rows S2 and R2, the stock identifying letters appearing in S2 and the quotation figures in R2. Both letters and figures are stored in one memory row, but are displayed in two rows as shown. Similarly, information from AMEX is displayed in rows R4 and S5. The information from each exchange is written from left to right. When the rows are completed, quotations at the left are erased and replaced by new quotations.

The lower half of the screen displays TTY information. Only six rows R7-Rl2 are actually displayed, R13 being conveniently considered to be out of sight at the bottom of the screen. At the beginning of a TTY message, characters are normally written in row R12. When the row is completed, new information is written in hidden row R13 and upshifted one line per field until it appears in R12. If characters initially arrive during an upshift cycle, they are first written in R13 and upshifted to R12. Inasmuch as the TTY character frequency is slow compared to the field frequency, the upshifting from R13 and R12 is completed during the first few character intervals. Thereafter row R12 is completed. As additional information arrives, it starts again in R13 and is upshifted into R12, the material in R12 being upshifted to R11 at the same time. This operation continues until the top information has been upshifted to R7 and six rows of information are displayed, as shown. Thereafter, as further information appears in R13 and is upshifted into R12, the top row R7 is upshifted and gradually disappears.

Referring to FIG. la, the displayed characters are written by a suitable dot pattern. The 1 lines of a display row are designated Y1-Y10. Five horizontal dots in vertical columns Xl-XS are available for each character, and characters are separated by two columns at dot frequency. The construction of the letters A and B by dot patterns is shown. In general, letters are written in seven lines Y2-Y8, as indicated. Fractions, and arbitrary characters if used, may use all of the Y-lines.

Referring to FIG. 2, a simplified block diagram shows the overall arrangement of the apparatus. Input channels 25 receive ticker information from NYSE and AMEX, together with 'I'I'Y information. The information is then transferred by memory input control 26 to a recirculating memory 27. The period of the memory recirculation cycle is selected as onehalf the TV field period, specifically 8% milliseconds for a 60 Hz. field frequency. The memory stores characters in serial digital bit form, and the input information is fed into the proper memory character cells under the control of timing signals from timing circuits 28.

Information in memory 27 is supplied serially to memory output register 29. As each character is registered in 29, the bits thereof are transferred in parallel to a buffer input register 31. Then, the character bits are transferred in parallel to a plurality of recirculating row buffers 32. In this embodiment sixbit characters are employed in the memory, and six-row buffers are employed. Each row buffer accommodates one coding bit of each character of a display row. Here, 48 characters per display row are used for stock information and 50 characters for TTY information.

The outputs of the row buffers 32 are supplied in parallel to a character encoder 33. Inasmuch as 10 lines are allocated to a display row, the row buffers 32 recirculate 10 times per display row so that the character encoder 33 can form the row dot patterns line by line for display purposes. Since NYSE and AMEX quotations occupy two rows, the buffers recirculate 20 times. For a given line, as each character is encoded the corresponding line dot pattern is transferred in parallel to the video output register 34.

Al! the registers and buffers, etc., are supplied with suitable timing signals from 28, as indicated. Timing signals are also supplied to sync generator 35 which produces conventional vertical and horizontal sync signals in accordance with present television standards. The synchronizing signals and the video signals are supplied to mixer 36 to form a composite TV signal which is fed to TV display 37.

The upshift cycle is initiated by a line feed character from the TIY input channel to upshift control 38. During this cycle the display rows in the lower half of the display are upshifted, but the display rows within the upper half are not. Broadly, the upshifting of the lower half of the display is produced by delaying the vertical sync pattern relative to memory readout one line at a time for successive fields until a total upshiftin g of 20 lines has been produced. During this upshift the utilization of information from the row buffers 32 by the character encoder 33 for the upper half of the display is delayed by one H (horizontal line period) per frame so that the upper half does not upshift. At the end of the upshift, the relative timing of memory readout and vertical synchronization is changed to reestablish the normal relationship between memory rows and display rows, and information in the memory for the upper half of the display is relocated. The relocation involves resync register 41, EOU (End Of Upshift) transfer register gate 42 and gate 43, as will be described later.

The memory character format is shown at the bottom of FIG. 2. The sixth bit indicates whether the preceding five data bits are for figures or letters. A two-bit space occurs between successive memory characters.

The logic diagrams shown in subsequent figures use digital logic elements. Many types of elements are known in the art and may be used as desired to perform the functions hereinafter described. The specific embodiment here shown uses NOR logic units extensively, examples of which are given in U.S. Pat. No. 3,28l,788, FIGS. 6-8. Their functioning will be described at this time to facilitate understanding the diagrams.

A gate such as shown at 55 in FIG. 3 has a plurality of inputs and one output. If any input line is high (say ground potential), the output line is low (say negative). If all input lines are low, the output line will be high. Thus, the gate functions as an AND gate with polarity inversion for input signals whose assertion levels are low, and as an OR circuit with inversion for signals whose assertion levels are high. An OR use is indicated by as at 72. If only one input line is used and the others left unconnected, the gate functions as a polarity inverter.

Two such gates may be cross connected as shown at 51 to form a DC flip-flop. A high input signal to either side (with the input to the other side low) will cause the output of that side to go low and the output of the other side to go high. The terms set" and *reset" will be used hereinafter to designate the two possible states of the flip-flop and are selected arbitrarily as seems convenient.

An AC flip-flop such as shown at 62 in FIG. 3 is a bistable multivibrator having steering inputs A and A,, and corresponding outputs Il and I. The FF is triggered by a positivegoing signal to the T-input and reset by a high signal to the R- input. In the reset state the output is high and the l output low. In the set state the outputs are reversed. If the steering inputs are high to A and low to A a trigger signal will set the flip-flop. If the steering inputs are low to A and high to A,, a trigger signal will reset the flip-flop. A shift register such as shown at 52 may be constructed of a number of AC flip-flops interconnected in known manner. Counters may also be made of AC flip-flops in known manner.

Both barred and unbarred signals are shown in the drawings, and are the inverse of each other. Usually the assertion level of an unbarred signal is high, and that of a barred signal is low. One signal may be obtained from the other by passing it through an inverter, or both outputs of a flip-flop may be used to provide the two signals, etc.

Certain portions of the apparatus such as the row buffers 32, character encoder 335 and video output register 3d operate at high speed. In such case integrated circuit logic elements are employed in practice. Several types are available commercially and vary somewhat in the polarity of signals required to produce a desired result, and in other operating details. To avoid confusion herein, the description is in terms of NOR logic as described above. The changes required for other types of logic elements will be understood by those skilled in the art.

Many signals used in earlier figures are developed in later figures. Usually their functioning will be described as they are used, leaving detailed development until later.

Referring now to FIG. 3, this shows a portion of the input channel for TTY signals, sometimes designated C3 (for Channel 3). The TTY signals are assumed to be of conventional five-level type having five data bits preceded by a start space and followed by a stop mark for each character.

The line TTr signals are supplied through DC FEM to input register 52. The register has seven AC FE stages of the type described above, shifted by TlRIG pulses. Marks and lbits are assumed high at the A, input and low at the A input. Spaces and O-bits are high at the A input and low at the A input.

A TTY line normally marks between characters, resetting the stages of register 52 and yielding a high W from the last stage. When a start space arrives, line 53 will go high. This makes the A input of FEM high, and the high I??? to gate fad is inverted to make the A, input low, thus steering FEM toward set. A 2.4 kl-lz. oscillator 56 drives a 3 counter d? to supply 800 Hz. pulses to the T-input of FEM and to gate 58. One pulse sets FEM, making its O-output low and enabling gate 1%. Subsequent pulses pass through gate dd to a 16 counter 59, thereby yielding 50 Ill. TRICv pulses corresponding to a 50 Baud rate for the TTY signals. Counter 59 is arranged to give a TING pulse at each count ofti, so that the TRIG pulses occur i the middle of bit intervals. These shift register $2. The high I17 to gate 55 maintains the A input low during the shifting so that FEM cannot be reset.

When a TTY character has been fully shifted into register 52, the start space in the last stage will makeWlow. The stop mark will make line fill low. This reverses the steering of lFEtid and it will be reset by the next pulse to its T input, closing gate Mi and stopping the shifting of register 52. Gate till senses when the shift clock is cut off. The resetting of lFEfi l and the low E77 makes both inputs low, and the gate output will be high. This steers FEM; toward set.

Sync tl pulses are produced at the beginning of each memory character cycle (FIG. Mb) and will set lFFtiZ. The resulting low O-output enables gate 653 to pass the next sync ll may pulse .(EIG. lldc), assuming XEER INI-I is low. The high gate output is inverted to produce a low DATA XEER which opens transfer gates M- to transfer the five data bits in register 52 to memory register 6% in parallel. The latter has set steering in puts by making A of the first stage high and A low, as indicated, so that a previous shift out will leave all stages set. Thus the transferred data bits need only reset the appropriate stages.

Before proceeding further with the memory transfer opera tion, the special character decoding will be described. TTY signals include special characters for carriage return, indicating the end of a line; for figures and letters, indicating the nature of subsequent characters until changed; and for line feed, indicating the start of a new line. The states of the five data stages in register 52 are supplied to the special character decoder 16h, along with R7 to indicate when the character is ready for decoding, and yields one or another of the outputs indicated. If carriage return is denoted, EEbT is steered toward set. A high CHAR. READY signal is produced by the setting of H 62 and sets H 67 to produce a high C/R RESET signal used in lFlG. Zia.

A figures character steers ElFtSIl toward set, and the CI-IAR. READY signal sets it to produce a low FIGS. INS. signal. A letters character produces the opposite steering and FFMI is reset. Either character is remembered until the opposite character is received.

A line feed character produces a high signal which is inverted to be a low signal to gate 69. RCLZ INII. (FIG. lltli inverted) is high except during upshift, and is inverted to be low to gate 6h. Thus, the gate output to A of FF'l'tl is high. The A input is held low by -V. lFE70 is set by the next SYNC Ii pulse to produce a high LINE FEED ADV. signal which initiates upshift. If a second l ine feed is received while upshift is proceeding, RCIJL INl-l. causes it to be ignored. The inversion of this signal goes high at the beginning of upshift, and is differentiated and used to reset lFF'Nl.

The special TTY characters are not inserted in the memory. Accordingly all lines from as are connected to OR'IZ to produce a low output when any line is high. This is inverted to give a high XEEiR INII which inhibits gate 63, thereby making DATA XIFER high to prevent the transfer from register 52 to 65. FEW is steered to be set by the next SYNC fl pulse, thereby giving a high write inhibit signal.

Returning to the memory transfer operation, the output of lFEtih is supplied to the sixth transfer gate in 64 and thus introduces the proper sixth bit in the memory register 65 at the time of data transfer. Shiftout of the register is timed with the memory cycle by W RITE C3, and this will now be described.

When is set to transfer data to the memory register. it steers lFEW-ll toward set and the next SYNC Ii pulse sets IFFM. The resultant high l-output resets EH52, counter 59, and input register 52., making them ready for a subsequent TTY character. The low O-output is inverted by gate 7d to make the A input of ElFl'ti high, provided WRITE [NH is low to indicate the absence of a special character. WRITE C3 (FIG. .ila) to the A input is low at this time, and EEl'b is set by the next SYNC 8 pulse to make the write request tl-output low. This indicates that the character in register 65 is ready for insertion in the memory at the proper time. PETA is reset due to the reversed steering from the reset FEM.

Referring to FIG. 3a, the WRITE REQ. signal is supplied to gate 7'7. IBUTT. IEILUW LD (FIG. 17s) is low when the proper memory row occurs, as will be described. CHAR. COINC goes low when the proper character slot is present at the memory input. This signal is produced by comparator 7%. Character address counter Til counts the characters as they are supplied from register tit-i to the memory. The states of the stages in counter 7%, designated lFSC, are supplied to comparator 7%. Inputs El /SIC to the comparator are obtained from a memory character counter (IFIG. '7). When the counts coincide, a low CI-IAIR. CUINC signal is produced. This actuates gate 77 to steer Elfhll toward set, and the next SYNC ti pulse sets it to make WRITE Cd low. The latter signal enables gate M. (FIG.

101023 mn'l

Claims (30)

1. A video display system comprising: a cathode-ray tUbe; first pulse-generating means for producing horizontal synchronization pulses at a first fixed recurrence frequency, and for producing vertical synchronization pulses, said first means being responsive to control signals to vary the interval between adjacent vertical pulses, and, in the absence of control signals, producing vertical pulses at a second fixed recurrence frequency whereby a fixed interval is established between adjacent vertical pulses in the absence of said control signals; second means coupled between said first means and said tube to produce a raster on the tube face, said raster comprising a fixed number of horizontal scanning lines of like length per frame, each horizontal line scan being initiated by a corresponding horizontal pulse, each frame being initiated by a corresponding vertical pulse; and third means to produce said control signals and to supply same to said first means to lengthen the interval between adjacent vertical pulses by a fixed period as compared to the fixed interval when the control signals are absent, said fixed period being equal to an integral multiple of the line scan interval.
2. A video display system wherein a cathode-ray tube is provided with first and second display regions, each of which extends horizontally across the face of the tube, each display region having a separate preselected number of display lines of changing information of the same length, the line scans being initiated successively first through the first region and then through the second region to complete a frame, each line scan being initiated by a separate horizontal pulse, the horizontal pulses having a fixed recurrence frequency, each frame being initiated by a separate vertical pulse, said horizontal and vertical pulses being produced by pulse-generating means, said tube having an input to which information is supplied in the form of electrical signals, one of said regions receiving new information in the bottom display line thereof and being adapted to clear the previously displayed top line thereof and to shift all other previously displayed lines into successively higher lines whereby the information has an apparent upward motion on the tube face, the other region receiving and displaying changing information without upshifting, said vertical pulses having a first fixed recurrence frequency in the absence of upshifting whereby a fixed interval is established between adjacent vertical pulses in the absence of upshifting, said system comprising: first means to store electrical signals for display in either region; second means to supply said stored signals to said tube input for display; third means responsive to electrical signals representing new information for display in either region and to signals stored in said first means to supply both types of signals to said first means, said second means arranging new information signals and stored signals in proper time sequence for delivery to said first means for display successively in the first and second regions; fourth means responsive to those new information signals which produce a display in said one display region and coupled to said pulse-generating means to lengthen the interval between adjacent vertical pulses by a fixed period as compared to the fixed delay in the absence of upshifting, said fixed period being an integral multiple of the period of a line scan whereby the vertical pulses have a second and lower fixed recurrence frequency when the information in said one display region is changing; and fifth means coupled to said first and second means to inhibit any upshifting in said other display region when upshifting occurs in said one display region.
3. A video display system wherein a cathode-ray tube displays a predetermined number of lines of information of the same length, each line scan being initiated by a separate horizontal pulse, the horizontal pulses having a fixed recurrence frequency, each frame being initiated by a separate vertical pulse, said horizontal and vertical pulses being produced by pulse-generating means, said tube having an input to which said information is supplied in the form of electrical signals, said system being adapted to enter new information on the bottom line of the display, to clear the previously displayed top line and to upshift all other previously displayed lines into successively higher lines, whereby the information has an apparent upward motion on the tube face, said vertical pulses having a first fixed recurrence frequency in the absence of upshifting whereby a fixed interval is established between adjacent vertical pulses in the absence of upshifting, said system comprising: first means to store electrical signals for display; second means to supply said stored signals to said tube input for display; third means responsive to electrical signals representing new information for display and to signals stored in said first means to supply same to said first means, said third means arranging new information signals and stored signals in proper time sequence for delivery to said first means; and fourth means responsive to new information signals and coupled to said pulse generating means to lengthen the interval between adjacent vertical pulses by a fixed period as compared to the fixed interval in the absence of upshifting, said fixed period being an integral multiple of the period of a line scan whereby the vertical pulses have a second and lower fixed recurrence frequency when the displayed information is changing.
4. Video display apparatus which comprises a. input means for receiving coded input characters to be displayed, b. a video display unit having line and field sweeps, said field sweeps being each initiated by a separate vertical pulse, said vertical pulses having a first fixed recurrence frequency in the absence of upshifting whereby a fixed interval is established between adjacent vertical pulses in the absence of upshifting; c. a recirculating memory having an input and an output, d. first means coupled to the memory input for inserting serially in said memory bit-coded representations of said characters, e. second means coupled to the memory output for converting the character bits at the memory output from series to parallel, f. a plurality of row buffer registers having respective inputs and outputs, g. third means coupled to said second means for loading said registers in parallel with respective like-order bits of said parallel bits for a display row of characters, h. fourth means coupled to said registers for recirculating said registers to yield outputs at display character frequency for a plurality of row cycles, i. display character encoding means responsive to said outputs for producing signals line-by-line representing the portions of said characters to be displayed on respective lines, j. fifth means coupled to the encoding means and utilizing the signals from said encoding means for producing a video signal, k. sixth means coupled to the fifth means for supplying said video signal to said display unit, l. and upshifting means for shifting characteristics in one display row to a display row thereabove and displaying new characters in said one display row, m. said upshifting means including means for lengthening the interval between adjacent vertical pulses by a fixed period as compared to the fixed interval in the absence of upshifting, said fixed period being an integral multiple of the period of a line sweep whereby the field sweeps are subjected to a relative delay with respect to the line-by-line encoding of said buffer register outputs by one scanning line in a field for a number of fields equal to the line spacing of said display rows.
5. Apparatus according to claim 4 in which the delay between the input and output of said recirculating memory is substantially equal to one-half a display field period, and including means for allocating predetermined alternate intervals in the recirculating memory cycle to characters to be displayed in the upper portion of the video display and predetermined intervening intervals to characters to be displayed in the lower portion of the display, each of said intervals accommodating characters for a display row and the total number of intervals being an odd integer.
6. Apparatus according to claim 4 in which said means for loading the buffer registers includes means for loading characters for display rows to be upshifted from alternate memory row intervals, and said means for recirculating the registers recirculates each loaded row in the interval between successive loadings for said line-by-line encoding of the outputs thereof.
7. Apparatus according to claim 6 including a source of memory clock pulses for entering character bits in said memory, counting means including means for counting said clock pulses in a memory character interval and means for counting the character intervals in a memory row interval, and means responsive to said character interval counts for entering input characters in a memory row interval.
8. Apparatus according to claim 7 in which said counting means includes a fixed line counter for counting memory intervals equal to display line periods and a fixed row counter for counting outputs of said fixed line counter corresponding to a predetermined number of lines in a display row to yield counts corresponding to display rows, and means for decoding the counts of said fixed row counter to produce fixed row gating signals corresponding to predetermined rows of said display.
9. Apparatus in accordance with claim 8 including means responsive to said upshifting means at substantially the end of said upshifting for changing the count of said fixed row counter by a count equal to the number of rows counted during said upshifting.
10. Apparatus in accordance with claim 9 including means responsive to said fixed row gating signals for controlling the loading of said buffer registers from the memory.
11. Apparatus in accordance with claim 10 in which the means in the upshifting means for producing said relative delay includes a cycle counter for counting fields during an upshift, a comparator for comparing the counts in said cycle and fixed row counters and yielding an output upon coincidence, and means utilizing the coincidence output for producing field synchronization signals for said field sweeps.
12. Apparatus in accordance with claim 11 in which said means for producing field synchronizing signals includes an upshift line counter enabled by said coincidence output for counting display lines, an upshift row counter for counting outputs of said upshift line counter corresponding to said predetermined number of lines in a display row, and means utilizing predetermined outputs of at least one of said upshift line and row counters for producing said field synchronizing signals.
13. Apparatus according to claim 12 including means responsive to said upshifting means at substantially the end of said upshifting for changing the count of said fixed row counter by a count equal to the number of rows counted during said upshifting.
14. Apparatus according to claim 13 in which the delay between the input and output of said recirculating memory is substantially equal to one-half a display field period, and including means for allocating predetermined alternate intervals in the recirculating memory cycle to characters to be displayed in the upper portion of the video display and predetermined intervening intervals to characters to be displayed in the lower portion of the display, each of said intervals accommodating characters for a display row and the total number of intervals being an odd integer.
15. Apparatus according to claim 9 including means utilizing said fixed row gating signals for defining a memory row interval corresponding to the normally lowest display row and an entry memory row interval occuring thereafter corresponding to a display row to be upshifted To said normally lowest display row, means for entering characters into said entry memory row interval during an upshifting cycle and upshifting the characters to said normally lowest display row, and means responsive to substantially the end of said upshifting for entering subsequent characters to be displayed in said normally lowest display row into the memory row interval corresponding thereto.
16. Apparatus according to claim 15 including means for clearing said initial entry memory row interval after the upshifting of characters entered therein.
17. Apparatus according to claim 15 including means for producing a signal indicating the beginning of a new row of characters to be displayed, and means responsive to said signal for actuating said upshifting means.
18. Apparatus according to claim 4 including a. a plurality of said input means, b. means for allocating a plurality of different row intervals in the recirculating memory cycle to characters from one of said input means and another row interval to characters from another of said input means, c. each of said row intervals accommodating memory characters for a display row, d. means for controlling said upshifting means to produce upshifting of rows displaying characters from said one input means, e. and means for preventing upshifting of a row displaying characters from said other input means including means for delaying the line-by-line encoding of the characters in said buffer registers for the corresponding display row by amounts equal to said delay of the field sweeps.
19. Apparatus according to claim 18 in which the characters in said other memory row interval include letter and figure identification, means for recirculating in said buffer registers the characters from said other memory row interval a number of times corresponding to the encoding of two display rows, and means for recognizing said letter and figure characters and controlling said encoding means to decode respective type characters line-by-line for respectively different display rows.
20. Apparatus according to claim 11 including a. a plurality of said input means, b. means for allocating a plurality of different row intervals in the recirculating memory cycle to characters from one of said input means and another row interval to characters from another of said input means, c. each of said row intervals accommodating memory characters for a display row, d. means for controlling said upshifting means to produce upshifting of rows displaying characters from said one input means, e. means for decoding counts of said upshift row counter to produce upshift row gating signals corresponding to predetermined rows of said display, f. said means in the upshifting means for producing a relative delay being responsive to said fixed row gating signals to control the line-by-line encoding of characters in said buffer registers corresponding to said one input means, g. and means responsive to said upshift row gating signals during said upshifting for controlling the line-by-line encoding of characters in the buffer registers corresponding to said other input means to prevent upshifting thereof.
21. Apparatus according to claim 20 including means responsive to at least said upshift row gating signals between said upshifting for controlling said encoding of characters corresponding to said other input means.
22. Apparatus according to claim 20 including means responsive to said upshifting means at substantially the end of said upshifting for reducing the count of said fixed row counter by a count equal to the number of rows counted during said upshifting, and transfer means for transferring the characters in said other memory row interval to a later row interval displaced from the previous interval by an amount corresponding to the number of rows counted during said upshifting.
23. Apparatus according to claim 22 in which said transfer means includes means for recirculating in said buffeR registers the characters in said other memory row, means for converting the buffer register outputs from parallel to series bit characters, and means for supplying the series bit characters to the memory input in said latter row interval.
24. Apparatus according to claim 22 in which the display rows corresponding to said one and said other input means for allocated to relatively lower and upper portions of the display, respectively, and including blanking means responsive to said coincidence output for producing a blanking signal to blank progressively during said upshifting the uppermost display row allocated to said one input means, and means for clearing after said upshifting the memory row interval containing characters displayed in said uppermost display row prior to upshifting.
25. Apparatus according to claim 22 including means for generating coded title characters to be displayed in fixed position on said display, means for supplying said coded title characters to said display character encoding means for line-by-line encoding thereof, and means responsive to at least said upshift row gating signals during upshift for controlling said supplying.
26. Apparatus according to claim 22 including means responsive to said fixed row gating signals and to said upshift row gating signals, respectively, for controlling the recirculation of characters from said one input means and from said other input means, respectively, in said row buffer registers and the supplying of output characters thereof to said display character encoding means during upshift.
27. Apparatus according to claim 22 in which the delay between the input and output of said recirculating memory is substantially equal to one-half a display field period, and including means for allocating predetermined alternate intervals in the recirculating memory cycle to characters to be displayed in the upper portion of the video display and predetermined intervening intervals to characters to be displayed in the lower portion of the display, each of said intervals accommodating characters for a display row and the total number of intervals being an odd integer, said means for loading the buffer registers including means for loading characters for display rows to be upshifted from alternate memory row intervals, and said means for recirculating the registers recirculates each loaded row in the interval between successive loadings for said line-by-line encoding of the outputs thereof.
28. Apparatus according to claim 27 including means for producing a signal indicating the beginning of a new row of characters to be displayed for said one input means, means responsive to said signal for actuating said upshifting means to produce an upshift cycle, means utilizing said fixed row gating signals for defining a memory row interval corresponding to the normally lowest display row for said one input means and an entry memory row interval occurring thereafter corresponding to a display row to be upshifted to said normally lowest display row, means for entering characters from said one input means into said entry memory row interval during an upshifting cycle, and means responsive to substantially the end of said upshifting cycle for entering subsequent characters to be displayed in said normally lowest display row into the memory row interval corresponding thereto.
29. Video display apparatus which comprises a. input means for receiving coded input characters to be displayed, b. a video display unit having line and field sweeps, said field sweeps being each initiated by a separate vertical pulse, said vertical pulses having a fixed fixed recurrence frequency in the absence of upshifting whereby a fixed interval is established between adjacent vertical pulses in the absence of upshifting, c. a recirculating memory having an input and an output, d. first means coupled to the memory for inserting in said memory bit-coded representations of said characters; e. second means coupled to the memory for Allocating a plurality of different row intervals in the recirculating memory cycle to characters from said input means, f. each of said row intervals accommodating memory characters for a display row, g. row buffer register means, h. third means coupled to the register means for successively loading said register means with characters in different memory row intervals, i. fourth means coupled to the register means for recirculating said register means between successive loadings thereof to yield outputs during a plurality of cycles corresponding to a plurality of display line sweeps, j. display character encoding means coupled to the fourth means and responsive to said outputs for producing signals line-by-line representing the portions of said characters to be displayed on respective lines, k. fifth means coupled to the encoding means and utilizing the signals from said encoding means for producing a video signal, l. sixth means coupled to the fifth means for supplying said video signal to said display unit, m. and upshifting means for shifting characters in one display row to a display row thereabove and displaying new characters in said one display row, n. said upshifting means including means for lengthening the interval between adjacent vertical pulses by a fixed period as compared to the fixed interval in the absence of upshifting, said fixed period being an integral multiple of the period of a line sweep whereby the field sweeps are subjected to a relative delay with respect to the line-by-line encoding of the outputs of said buffer register means by one scanning line in a field for a number of fields equal to the line spacing of said display rows.
30. Apparatus according to claim 29 including a a. plurality of said input means, b. said allocating means allocating said plurality of memory row intervals to characters from one of said input means and another memory row interval to characters from another of said input means, c. means for controlling said upshifting means to produce upshifting of rows displaying characters from said one input means, d. and means for preventing upshifting of a row displaying characters from said other input means including means for delaying the line-by-line encoding of the characters in said row buffer register means for the corresponding display row by amounts equal to said delay of the field sweeps.
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US3801961A (en) * 1971-05-21 1974-04-02 Reuters Ltd System for providing a video display having differing video display formats
US3792462A (en) * 1971-09-08 1974-02-12 Bunker Ramo Method and apparatus for controlling a multi-mode segmented display
US3742482A (en) * 1971-09-08 1973-06-26 Bunker Ramo Method and apparatus for generating a traveling display
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US3787833A (en) * 1973-05-04 1974-01-22 Gte Information Syst Inc Upshift control for video display
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US4129858A (en) * 1976-03-25 1978-12-12 Hitachi, Ltd. Partitioned display control system
US4112423A (en) * 1976-09-13 1978-09-05 Kelsey-Hayes Co. Dual-screen data display terminal for data processing units
US4197534A (en) * 1976-12-13 1980-04-08 Organisation Europeenne De Recherches Spatiales Control apparatus for displaying alphanumeric characters
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US4386410A (en) * 1981-02-23 1983-05-31 Texas Instruments Incorporated Display controller for multiple scrolling regions
US4414628A (en) * 1981-03-31 1983-11-08 Bell Telephone Laboratories, Incorporated System for displaying overlapping pages of information
US4458331A (en) * 1981-10-09 1984-07-03 International Business Machines Corporation Interactive display terminal with alternating data processing and text processing sessions with text processing status line operable during data processing session
US4517654A (en) * 1982-08-09 1985-05-14 Igt Video processing architecture
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US4873514A (en) * 1984-12-20 1989-10-10 International Business Machines Corporation Video display system for scrolling text in selected portions of a display
US4803478A (en) * 1986-02-21 1989-02-07 Prime Computer, Inc. Horizontal scroll method and apparatus
US4899136A (en) * 1986-04-28 1990-02-06 Xerox Corporation Data processor having a user interface display with metaphoric objects
US4937036A (en) * 1986-04-28 1990-06-26 Xerox Corporation Concurrent display of data from two different display processors and user interface therefore
US4939507A (en) * 1986-04-28 1990-07-03 Xerox Corporation Virtual and emulated objects for use in the user interface of a display screen of a display processor
US5088033A (en) * 1986-04-28 1992-02-11 Xerox Corporation Data processing system emulation in a window with a coprocessor and I/O emulation
US5113517A (en) * 1986-04-28 1992-05-12 Xerox Corporation Concurrent display of data from two different processors each having different display font and user interface for controlling transfer of converted font data therebetween
US5153577A (en) * 1986-04-28 1992-10-06 Xerox Corporation Mapping character color attributes into grey pixel patterns

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