US3636397A - Single-crystal silicon carbide display device - Google Patents

Single-crystal silicon carbide display device Download PDF

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US3636397A
US3636397A US3636397DA US3636397A US 3636397 A US3636397 A US 3636397A US 3636397D A US3636397D A US 3636397DA US 3636397 A US3636397 A US 3636397A
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wafer
grooves
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Arrigo Addamiano
Ronald J Perusek
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General Electric Co
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/26Materials of the light emitting region
    • H01L33/34Materials of the light emitting region containing only elements of group IV of the periodic system
    • H01L33/343Materials of the light emitting region containing only elements of group IV of the periodic system characterised by the doping materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
    • H01L29/1608Silicon carbide
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/44Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001Core members of the connector
    • H01L2224/45099Material
    • H01L2224/451Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144Gold (Au) as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3025Electromagnetic shielding
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/107Melt
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/148Silicon carbide
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/931Silicon carbide semiconductor

Abstract

The display device is a wafer of N-type silicon carbide having lines or segments of lines scribed into one face in a selected design such as an alpha-numeric or a grid of closely spaced dots. After scribing, the wafer is diffused with P-type dopants such as boron and aluminum. Contact to the P-type material within the scribed lines is made by vacuum evaporation of copper-silver. The wafer faces are then lapped to remove the metallizing and P-type layer except within the scribed lines. A connection is then made to the N-type material, and individual connections to each P-type scribed-line segment. By selective energization of line segments, various luminous letters, numerals or characters may be formed which are seen through the N-type material.

Description

United States Patent Addamiano et al.

[151 3,636,397 51 Jan. 18,1972

[72] Inventors: Arrigo Addamiano, Willoughby; Ronald J.

Perusek, Chardon, both of Ohio [73] Assignee: General Electric Company [22] Filed: Apr. 10, 1969 21 Appl. No.: 815,047

Primary Examiner-John Kominski Assistant ExaminerDavid OReilly Attomey-Emest W. Legree, Henry P. Truesdell, Frank L, Neuhauser, Oscar B. Waddell and Melvin M. Goldenberg [57] ABSTRACT The display device is a wafer of N-type silicon carbide having lines or segments of lines scribed into one face in a selected design such as an alpha-numeric or a grid of closely spaced dots. After scribing, the wafer is diffused with P-type dopants such as boron and aluminum. Contact to the P-type material within the scribed lines is made by vacuum evaporation of copper-silver. The wafer faces are then lapped to remove the metallizing and P-type layer except within the scribed lines. A connection is then made to the N-type material, and individual connections to each P-type scribed-line segment. By selective energization of line segments, various luminous letters, numerals or characters may be formed which are seen through the N-type material.

8 Claims, 1 1 Drawing Figures PATENTEU JAN] 8872 31636.39.

smzu 1 er 2 Figgla. Fi gb lnven tors'. Ar'r'i cp o Addamiano RonaLd J. Perusek by JWW V Their A t torneg PATENTEnJAmnsn 3,636,397

sum ear 2 WWI/114W? ITWVTW tOTSI Arrigo Addamiano Ronatd J. Perusek SINGLE-CRYSTAL SILICON CARBIDE DISPLAY DEVICE CROSS-REFERENCES TO RELATED APPLICATIONS Copending application Ser. No. 732,442, filed May 27, 1968 by Arrigo Addamiano, entitled Formation of Junctions in Silicon Carbide by Selective Diffusion of Dopants and similarly assigned.

Copending application Ser. No. 685,447, filed Nov. 24, I967, now U.S. Pat. No. 3,458,779, by John M. Blank and Ralph M. Potter, entitled Silicon Carbide Light-Emitting Diodes" and similarly assigned.

BACKGROUND OF THE INVENTION The invention relates to solid-state subminiature display apparatus utilizing light-emitting junctions in silicon carbide. Light-emitting diodes or solid-state lamps of silicon carbide comprise a junction between n-type material which may be nitrogen doped and p-type material which may be boron and/or aluminum doped. When the device is suitably energized by the application of a forward potential across the junction, light is generated by the recombination of charge carriers in close proximity to the junction. In commercially available solid-state indicator lamps, a crystal chip containing a PN- junction is mounted P-side down on a header and light is emitted through the N-type top side which is contacted by a fine wire.

Solid-state visual display apparatus may be used for displaying symbols including alphabet letters, numerals and symbols of various kinds. Such apparatus is particularly useful in highspeed photographic recording because the response is sub stantially instantaneous. In copending application No. 732,442, filed May 27, 1968 by one of us (Arrigo Addamiano), entitled Formation of Junctions in Silicon Carbide by SelectiveDiffusion of Dopants," a method of creating lighting patterns in a single crystal of silicon carbide is disclosed which comprises diffusion of dopants into selected zones of the crystal. At the same time diffusion of dopants into other zones is prevented by covering or shielding such other zones by a refractory nonporous material, suitably fragments of silicon carbide crystals.

Among the objects of the invention are to provide improved solid-state display apparatus in which the selected designs are clearer and more legible and wherein more information may be conveyed within a given size, and to provide an improved process and technique for creating selected lighting designs in a silicon carbide wafer.

SUMMARY OF THE INVENTION The invention provides a solid-state display device consisting of a wafer of N-type silicon carbide having lines or segments of lines scribed into one face and forming a selected design such as an alpha-numeric or a grid of closely spaced dots. The lines are shallow grooves or V-cuts which may be made by a diamond saw. After scribing, the wafer is diffused with P-type dopants such as boron and aluminum. Contact to the P-type material within the grooves is made by vacuum evaporation of suitable metals such as copper and silver. In order to have individual lighting control of the various grooves or portions of grooves, masking of portions is done prior to the metallizing by vacuum evaporation. An alternative technique suitable for making a grid of closely spaced dots is to cross groove after metallizing. The wafer faces are then lapped to remove the metallizing and P-type layer except in the grooves or V-cuts. Individual connections to each P-type groove segment are then made and a single connection is also made to the N'type material. The luminous design is seen by looking at the grooves through the N-type wafer.

DESCRIPTION OF DRAWING FIG. la shows a silicon carbide crystal ground flat and FIG. lb shows a rectangular wafer cut therefrom.

FIG. 2 illustrates a diamond saw scribing a line into a wafer.

FIG. 3 shows a silicon carbide wafer having an alpha-numeric scribed into one face.

FIG. 4 is a cross section through a scribed line on a wafer after P-type diffusion and metal deposition.

FIG. 5 shows the same cross section as FIG. 4 after lapping and attachment of a wire lead.

FIG. 6 is a pictorial view of an alpha-numeric SiC indicator.

FIGS. 70, b, c and d show successive stages in making an SiC grid indicator.

DETAILED DESCRIPTION The starting material to prepare a single crystal alpha-numeric indicator may be a platelet of green, nitrogen-doped SiC. A typical platelet I is well formed as a hexagon on five sides; it is ground flat and polished with a metal-bonded diamond lap to achieve plane surfaces perpendicular to the c axis as shown in FIG. la; by way of example, the platelet may be as much as I5 millimeters across and about 0.5 millimeter thick after grinding and polishing. It may be desirable to cut the platelet to some standard size such as a 5X l O-mm. wafer as illustrated at 2 in FIG. lb and this may be done using a diamond saw.

An alpha-numeric indicator 3 is illustrated in FIG. 3 wherein the pattern consists of rectangular framing lines 4, crosslines 5, and diagonal lines 6. Lines or V-grooves are cut or scribed into the face of the wafer by cementing it to a suitable support 7 and running a diamond saw across the upper face to create the pattern, as shown in FIG. 2. The diamond saw may consist of a phosphor bronze disc 8 having a thin knife edge impregnated with diamond dust. The width of the luminous lines may be-increased by making the cuts deeper and this also increases the visibility of the indicator, but-of course the cuts or grooves cannot exceed in depth the thickness of the wafer. Where a fine line indicating device is desired or where a grid pattern of many closely spaced dots is desired, the depth of the cuts may be reduced and this permits the lines to be placed closer together.

After the selected design has been scribed into the wafer, P type dopants, preferably boron and aluminum, are diffused into it. This may be done by placing the wafer within a doublewalled graphite crucible of which the outer vessel wall consists of dense graphite while the inner vessel wall is made of porous graphite or carbon. The wafer is placed within the inner vessel and a protective charge of silicon and carbon with which are admixed the boron and aluminum dopants is located in the in tramural cavity between outer and inner walls. By way of example, suitable proportions for the protective charge are silicon and carbon in equal molar proportions plus 0.] atom percent Al and 0.1 mole percent H The crucible is placed within a carbon tube furnace which is located within a vacuum chamber. Reference may be made to copending application Ser. No. 685,447, filed Nov. 24, 1967, now US. Pat. No. 3,458,779, by John M. Blank and Ralph M. Potter for more details regarding diffusion of dopants and suitable furnace equipment for so doing. Diffusion may take place at a temperature of about 2,000 C. and results in a P-type surface layer, from 0.1 to 10 microns thick depending upon diffusion time and temperature. P-type layers are formed on both faces of the wafer and extend into the SiC from the grooves; the layers are shown by stippling at I1 and 12 in FIG. 4.

In an alpha-numeric indicator, each half of a framing, cross and diagonal line of the pattern must be separately controlla ble to form all thecharacters desired. This requires that each half-line or segment be insulated and this may be accomplished by suitable masking. A dot of silicon carbide paint consisting of fine grit SiC dispersed in mineral oil is applied to the midpoint and to the ends of each of the lines or V-cuts, as indicated by stippling at 13 in FIGS. The wafer is then placed on a graphite resistance heater strip in a bell jar which is evacuated. The heater strip is heated by passing current through it to approximately 500 C. for 10 minutes to eliminate the oil, leaving only the SiC fine grit in place as a mask. Contact to the P-type side is now made by vacuum evaporation of suitable metals, for instance aluminum-silicon alloy, preferably close to the eutectic composition, or nickelchromium or copper and silver. The entire upper surface of the wafer carrying the pattern becomes metallized as shown at 14 in FIG. 4. Both faces of the wafer are then ground and polished to remove the metallizing and P-type layer from all areas except within the grooves. At this stage the SiC fine grit is also removed by the polishing and this results in a discontinuity in the metallizing within the grooves at the places where the dots of SiC grit were applied.

Individual connections to each P-type groove or line segment may be made by attaching wires IS to the metallized contact layer within the groove. The wires may be attached by soldering or by thermocompression bonding when fine gold wires are used. An ohmic contact is also made to the N-type material using suitable N-type contacting material such as silicon-phosphorus or gold-tantalum alloy. The N-type material has good conductivity and a single small area contact to it suffices to which a wire may be attached, as indicated at 16 in FIG. 5.

Upon applying a few volts in the forward direction across the contacts (positive to P-side and negative to N-side), the line segments light up and are seen by looking down upon them from the opposite side through the thickness of the wafer, as in FIG. 6. The letters and numbers which can be formed by selective energization of the segments can readily be seen in a normally illuminated room. By choosing different types of SiC crystals and different dopants, displays of various colors can be obtained, for instance green, yellow, orange and red.

FIGS. 7a to d illustrate successive stages in making a solidstate indicator consisting of a grid of closely spaced dots or luminous spots subject to individual control. Referring to FIG. 7a, there is shown an N-type silicon carbide wafer 22 having relatively shallow closely spaced lines or V-grooves 23 cut or scribed in the top face. The scribed wafer is next subject to diffusion of P-type dopants creating top and bottom P-type layers 24,25, and thereafter to vacuum evaporation of copper and silver to provide a contact layer 26 on the top face, as shown in FIG. 7b. The top face is next cross grooved by cuts 27 running at right angles to the original V-cuts, as shown in FIG. 7c. The wafer is then flat ground on the top face to remove both metallizing and P-type layers except within the grooves, and is also ground on the bottom face to remove the P-type layer, as shown in FIG. 7d. This restores the bottom face to N- type and leaves the P-type material in the groove segments only on the top face. Each groove is broken up into isolated segments, each short segment being a small P-type area or clot backed up by a metallizing layer of copper and silver. Individual connections to each P-type dot may now be made,

either by using a contactor with conductors spatially arranged to contact the metallized segments of the wafer, or altematively by thermocompression bonding fine gold wires to the metallized dots. Upon energization, a luminous pattern is created which is seen by looking at the dots through the thickness of the N-type material. By selective energization of the various dots, moving patterns may be created to convey infonnation.

What we claim as new and desire to secure by Letters Patent of the United States is:

l. A single-crystal display device comprising a wafer of N- type silicon carbide, grooves scribed in a face of the wafer forming line segments adapted to create intelligence-conveying patterns, P-type dopant difi'used into the wafer from the groove surfaces and forming P-type material along the grooves, contact metal deposited in said grooves and attached to the P-type material, a connection to exposed N-type material and individual connections to the contact metal attached to the P-type material within line segments.

2. A display device as in claim 1 wherein the grooves are disposed as framing, cross and diagonal lines to form an alphanumeric indicator. I

3. A display device as in claim 1 wherein the grooves are disposed in parallel and closely spaced, and cross grooves break up the original grooves into segments to form a grid indicator of closely spaced luminous spots.

4. A display device as in claim 1 wherein the P-type dopant comprises boron and aluminum.

5. A display device as in claim 1 wherein the contact metal deposited in the grooves comprises copper and silver.

6. The method of making a single-crystal display device which comprises obtaining a wafer of N-type silicon carbide, scribing one face of the wafer with grooves forming lines disposed to create intelligence-conveying patterns, diffusing a P-type dopant into said wafer, said grooves penetrating into said wafer a depth exceeding the diffusion depth of said P-type dopant, vacuum evaporating contact metal onto said P-type material, removing the contact metal and the P-type material from the face of the wafer except within the scribed grooves, and making a connection to the exposed N-type material and individual connections to the metal contacting the P-type material within the grooves.

7. The method of claim 6 wherein portions of the grooves are masked prior to dopant diffusion and contact metal evaporation in order to have line segments formed by the unmasked portions, and individual connections are made to the line segments.

8. The method of claim 6 wherein said one face is scribed with cross grooves after dopant diffusion and contact metal evaporation in order to break up the original grooves into segments, and individual connections are made to the groove segments. 7

V a: a:

Claims (7)

  1. 2. A display device as in claim 1 wherein the grooves are disposed as framing, cross and diagonal lines to form an alpha-numeric indicator.
  2. 3. A display device as in claim 1 wherein the grooves are disposed in parallel and closely spaced, and cross grooves break up the original grooves into segments to form a grid indicator of closely spaced luminous spots.
  3. 4. A display device as in claim 1 wherein the P-type dopant comprises boron and aluminum.
  4. 5. A display device as in claim 1 wherein the contact metal deposited in the grooves comprises copper and silver.
  5. 6. The method of making a single-crystal display device which comprises obtaining a wafer of N-type silicon carbide, scribing one face of the wafer with grooves forming lines disposed to create intelligence-conveying patterns, diffusing a P-type dopant into said wafer, said grooves penetrating into said wafer a depth exceeding the diffusion depth of said P-type dopant, vacuum evaporating contact metal onto said P-type material, removing the contact metal and the P-type material from the face of the wafer except within the scribed grooves, and making a connection to the exposed N-type material and individual connections to the metal contacting the P-type material within the grooves.
  6. 7. The method of claim 6 wherein portions of the grooves are masked prior to dopant diffusion and contact metal evaporation in order to have line segments formed by the unmasked portions, and individual connections are made to the line segments.
  7. 8. The method of claim 6 wherein said one face is scribed with cross grooves after dopant diffusion and contact metal evaporation in order to break up the original grooves into segments, and individual connections are made to the groove segments.
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US5030583A (en) * 1988-12-02 1991-07-09 Advanced Technolgy Materials, Inc. Method of making single crystal semiconductor substrate articles and semiconductor device
US5726463A (en) * 1992-08-07 1998-03-10 General Electric Company Silicon carbide MOSFET having self-aligned gate structure
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US5726463A (en) * 1992-08-07 1998-03-10 General Electric Company Silicon carbide MOSFET having self-aligned gate structure
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US20060178076A1 (en) * 1999-03-19 2006-08-10 Masayuki Nakamoto Method of manufacturing field emission device and display apparatus
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Also Published As

Publication number Publication date Type
GB1201428A (en) 1970-08-05 application
US3458779A (en) 1969-07-29 grant
DE1810472B2 (en) 1970-12-10 application
DE1810472A1 (en) 1970-03-26 application
FR1592851A (en) 1970-05-19 grant

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